262 lines
12 KiB
ArmAsm
262 lines
12 KiB
ArmAsm
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2011 Perry Hung.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/* STM32F1 performance line ISR weak declarations */
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#include <libmaple/stm32.h>
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.thumb
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/* Default handler for all non-overridden interrupts and exceptions */
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.globl __default_handler
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.type __default_handler, %function
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__default_handler:
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b .
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.weak __exc_nmi
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.globl __exc_nmi
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.set __exc_nmi, __default_handler
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.weak __exc_hardfault
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.globl __exc_hardfault
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.set __exc_hardfault, __default_handler
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.weak __exc_memmanage
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.globl __exc_memmanage
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.set __exc_memmanage, __default_handler
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.weak __exc_busfault
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.globl __exc_busfault
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.set __exc_busfault, __default_handler
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.weak __exc_usagefault
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.globl __exc_usagefault
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.set __exc_usagefault, __default_handler
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.weak __stm32reservedexception7
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.globl __stm32reservedexception7
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.set __stm32reservedexception7, __default_handler
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.weak __stm32reservedexception8
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.globl __stm32reservedexception8
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.set __stm32reservedexception8, __default_handler
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.weak __stm32reservedexception9
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.globl __stm32reservedexception9
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.set __stm32reservedexception9, __default_handler
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.weak __stm32reservedexception10
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.globl __stm32reservedexception10
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.set __stm32reservedexception10, __default_handler
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.weak __exc_svc
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.globl __exc_svc
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.set __exc_svc, __default_handler
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.weak __exc_debug_monitor
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.globl __exc_debug_monitor
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.set __exc_debug_monitor, __default_handler
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.weak __stm32reservedexception13
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.globl __stm32reservedexception13
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.set __stm32reservedexception13, __default_handler
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.weak __exc_pendsv
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.globl __exc_pendsv
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.set __exc_pendsv, __default_handler
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// .weak __exc_systick // __exc_systick() defined in STM32F1/cores/maple/libmaple/systick.c
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// .globl __exc_systick
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// .set __exc_systick, __default_handler
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.weak __irq_wwdg
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.globl __irq_wwdg
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.set __irq_wwdg, __default_handler
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.weak __irq_pvd
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.globl __irq_pvd
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.set __irq_pvd, __default_handler
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.weak __irq_tamper
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.globl __irq_tamper
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.set __irq_tamper, __default_handler
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.weak __irq_rtc
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.globl __irq_rtc
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.set __irq_rtc, __default_handler
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.weak __irq_flash
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.globl __irq_flash
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.set __irq_flash, __default_handler
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.weak __irq_rcc
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.globl __irq_rcc
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.set __irq_rcc, __default_handler
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// .weak __irq_exti0 // __irq_exti0() defined in STM32F1/cores/maple/libmaple/exti.c
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// .globl __irq_exti0
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// .set __irq_exti0, __default_handler
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// .weak __irq_exti1 // __irq_exti1() defined in STM32F1/cores/maple/libmaple/exti.c
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// .globl __irq_exti1
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// .set __irq_exti1, __default_handler
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// .weak __irq_exti2 // __irq_exti2() defined in STM32F1/cores/maple/libmaple/exti.c
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// .globl __irq_exti2
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// .set __irq_exti2, __default_handler
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// .weak __irq_exti3 // __irq_exti3() defined in STM32F1/cores/maple/libmaple/exti.c
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// .globl __irq_exti3
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// .set __irq_exti3, __default_handler
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// .weak __irq_exti4 // __irq_exti4() defined in STM32F1/cores/maple/libmaple/exti.c
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// .globl __irq_exti4
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// .set __irq_exti4, __default_handler
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// .weak __irq_dma1_channel1 // __irq_dma1_channel1() defined in STM32F1/cores/maple/libmaple/dma_f1.c
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// .globl __irq_dma1_channel1
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// .set __irq_dma1_channel1, __default_handler
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// .weak __irq_dma1_channel2 // __irq_dma1_channel2() defined in STM32F1/cores/maple/libmaple/dma_f1.c
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// .globl __irq_dma1_channel2
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// .set __irq_dma1_channel2, __default_handler
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// .weak __irq_dma1_channel3 // __irq_dma1_channel3() defined in STM32F1/cores/maple/libmaple/dma_f1.c
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// .globl __irq_dma1_channel3
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// .set __irq_dma1_channel3, __default_handler
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// .weak __irq_dma1_channel4 // __irq_dma1_channel4() defined in STM32F1/cores/maple/libmaple/dma_f1.c
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// .globl __irq_dma1_channel4
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// .set __irq_dma1_channel4, __default_handler
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// .weak __irq_dma1_channel5 // __irq_dma1_channel5() defined in STM32F1/cores/maple/libmaple/dma_f1.c
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// .globl __irq_dma1_channel5
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// .set __irq_dma1_channel5, __default_handler
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// .weak __irq_dma1_channel6 // __irq_dma1_channel6() defined in STM32F1/cores/maple/libmaple/dma_f1.c
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// .globl __irq_dma1_channel6
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// .set __irq_dma1_channel6, __default_handler
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// .weak __irq_dma1_channel7 // __irq_dma1_channel7() defined in STM32F1/cores/maple/libmaple/dma_f1.c
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// .globl __irq_dma1_channel7
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// .set __irq_dma1_channel7, __default_handler
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// .weak __irq_adc // __irq_adc() defined in STM32F1/cores/maple/libmaple/adc_f1.c
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// .globl __irq_adc
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// .set __irq_adc, __default_handler
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.weak __irq_usb_hp_can_tx
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.globl __irq_usb_hp_can_tx
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.set __irq_usb_hp_can_tx, __default_handler
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// .weak __irq_usb_lp_can_rx0 // __irq_usb_lp_can_rx0() defined in STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c
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// .globl __irq_usb_lp_can_rx0
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// .set __irq_usb_lp_can_rx0, __default_handler
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.weak __irq_can_rx1
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.globl __irq_can_rx1
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.set __irq_can_rx1, __default_handler
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.weak __irq_can_sce
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.globl __irq_can_sce
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.set __irq_can_sce, __default_handler
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// .weak __irq_exti9_5 // __irq_exti9_5() defined in STM32F1/cores/maple/libmaple/exti.c
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// .globl __irq_exti9_5
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// .set __irq_exti9_5, __default_handler
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// .weak __irq_tim1_brk // __irq_tim1_brk() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim1_brk
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// .set __irq_tim1_brk, __default_handler
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// .weak __irq_tim1_up // __irq_tim1_up() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim1_up
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// .set __irq_tim1_up, __default_handler
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// .weak __irq_tim1_trg_com // __irq_tim1_trg_com() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim1_trg_com
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// .set __irq_tim1_trg_com, __default_handler
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// .weak __irq_tim1_cc // __irq_tim1_cc() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim1_cc
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// .set __irq_tim1_cc, __default_handler
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//
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// .weakref __irq_tim2, __default_handler // __irq_tim2() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim2
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// .weakref __irq_tim3, __default_handler // __irq_tim3() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim3
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// .weakref __irq_tim4, __default_handler // __irq_tim4() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim4
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//
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// .weak __irq_i2c1_ev // __irq_i2c1_ev() defined in STM32F1/cores/maple/libmaple/i2c_f1.c
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// .globl __irq_i2c1_ev
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// .set __irq_i2c1_ev, __default_handler
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// .weak __irq_i2c1_er // __irq_i2c1_er() defined in STM32F1/cores/maple/libmaple/i2c_f1.c
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// .globl __irq_i2c1_er
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// .set __irq_i2c1_er, __default_handler
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// .weak __irq_i2c2_ev // __irq_i2c2_ev() defined in STM32F1/cores/maple/libmaple/i2c_f1.c
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// .globl __irq_i2c2_ev
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// .set __irq_i2c2_ev, __default_handler
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// .weak __irq_i2c2_er // __irq_i2c2_er() defined in STM32F1/cores/maple/libmaple/i2c_f1.c
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// .globl __irq_i2c2_er
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// .set __irq_i2c2_er, __default_handler
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.weak __irq_spi1
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.globl __irq_spi1
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.set __irq_spi1, __default_handler
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.weak __irq_spi2
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.globl __irq_spi2
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.set __irq_spi2, __default_handler
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// .weak __irq_usart1 // __irq_usart1() defined in STM32F1/cores/maple/libmaple/usart_f1.c
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// .globl __irq_usart1
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// .set __irq_usart1, __default_handler
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// .weak __irq_usart2 // __irq_usart2() defined in STM32F1/cores/maple/libmaple/usart_f1.c
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// .globl __irq_usart2
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// .set __irq_usart2, __default_handler
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// .weak __irq_usart3 // __irq_usart3() defined in STM32F1/cores/maple/libmaple/usart_f1.c
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// .globl __irq_usart3
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// .set __irq_usart3, __default_handler
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// .weak __irq_exti15_10 // __irq_exti15_10() defined in STM32F1/cores/maple/libmaple/exti.c
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// .globl __irq_exti15_10
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// .set __irq_exti15_10, __default_handler
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.weak __irq_rtcalarm
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.globl __irq_rtcalarm
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.set __irq_rtcalarm, __default_handler
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.weak __irq_usbwakeup
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.globl __irq_usbwakeup
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.set __irq_usbwakeup, __default_handler
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#if defined (STM32_HIGH_DENSITY)
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// .weak __irq_tim8_brk // __irq_tim8_brk() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim8_brk
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// .set __irq_tim8_brk, __default_handler
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// .weak __irq_tim8_up // __irq_tim8_up() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim8_up
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// .set __irq_tim8_up, __default_handler
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// .weak __irq_tim8_trg_com // __irq_tim8_trg_com() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim8_trg_com
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// .set __irq_tim8_trg_com, __default_handler
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// .weak __irq_tim8_cc // __irq_tim8_cc() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim8_cc
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// .set __irq_tim8_cc, __default_handler
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// .weak __irq_adc3 // __irq_adc3() defined in STM32F1/cores/maple/libmaple/adc_f1.c
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// .globl __irq_adc3
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// .set __irq_adc3, __default_handler
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.weak __irq_fsmc
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.globl __irq_fsmc
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.set __irq_fsmc, __default_handler
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.weak __irq_sdio
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.globl __irq_sdio
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.set __irq_sdio, __default_handler
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// .weak __irq_tim5 // __irq_tim5() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim5
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// .set __irq_tim5, __default_handler
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.weak __irq_spi3
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.globl __irq_spi3
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.set __irq_spi3, __default_handler
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// .weak __irq_uart4 // __irq_uart4() defined in STM32F1/cores/maple/libmaple/usart_f1.c
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// .globl __irq_uart4
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// .set __irq_uart4, __default_handler
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// .weak __irq_uart5 // __irq_uart5() defined in STM32F1/cores/maple/libmaple/usart_f1.c
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// .globl __irq_uart5
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// .set __irq_uart5, __default_handler
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// .weak __irq_tim6 // __irq_tim6() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim6
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// .set __irq_tim6, __default_handler
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// .weak __irq_tim7 // __irq_tim7() defined in STM32F1/cores/maple/libmaple/timer.c
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// .globl __irq_tim7
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// .set __irq_tim7, __default_handler
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// .weak __irq_dma2_channel1 // __irq_dma2_channel1() defined in STM32F1/cores/maple/libmaple/dma_f1.c
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// .globl __irq_dma2_channel1
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// .set __irq_dma2_channel1, __default_handler
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// .weak __irq_dma2_channel2 // __irq_dma2_channel2() defined in STM32F1/cores/maple/libmaple/dma_f1.c
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// .globl __irq_dma2_channel2
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// .set __irq_dma2_channel2, __default_handler
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// .weak __irq_dma2_channel3 // __irq_dma2_channel3() defined in STM32F1/cores/maple/libmaple/dma_f1.c
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// .globl __irq_dma2_channel3
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// .set __irq_dma2_channel3, __default_handler
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// .weak __irq_dma2_channel4_5 // __irq_dma2_channel4_5() defined in STM32F1/cores/maple/libmaple/dma_f1.c
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// .globl __irq_dma2_channel4_5
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// .set __irq_dma2_channel4_5, __default_handler
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#endif /* STM32_HIGH_DENSITY */ |