225 lines
5.9 KiB
C
225 lines
5.9 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Perry Hung.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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#ifdef STM32F2
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/**
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* @file gpio.c
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* @brief GPIO initialization routine
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*/
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#include "gpio.h"
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#include "rcc.h"
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/*
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* GPIO devices
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*/
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gpio_dev gpioa = {
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.regs = GPIOA_BASE,
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.clk_id = RCC_GPIOA,
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.exti_port = AFIO_EXTI_PA,
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};
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/** GPIO port A device. */
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gpio_dev* const GPIOA = &gpioa;
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gpio_dev gpiob = {
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.regs = GPIOB_BASE,
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.clk_id = RCC_GPIOB,
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.exti_port = AFIO_EXTI_PB,
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};
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/** GPIO port B device. */
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gpio_dev* const GPIOB = &gpiob;
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gpio_dev gpioc = {
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.regs = GPIOC_BASE,
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.clk_id = RCC_GPIOC,
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.exti_port = AFIO_EXTI_PC,
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};
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/** GPIO port C device. */
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gpio_dev* const GPIOC = &gpioc;
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gpio_dev gpiod = {
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.regs = GPIOD_BASE,
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.clk_id = RCC_GPIOD,
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.exti_port = AFIO_EXTI_PD,
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};
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/** GPIO port D device. */
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gpio_dev* const GPIOD = &gpiod;
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#ifdef STM32_HIGH_DENSITY
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gpio_dev gpioe = {
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.regs = GPIOE_BASE,
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.clk_id = RCC_GPIOE,
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.exti_port = AFIO_EXTI_PE,
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};
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/** GPIO port E device. */
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gpio_dev* const GPIOE = &gpioe;
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gpio_dev gpiof = {
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.regs = GPIOF_BASE,
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.clk_id = RCC_GPIOF,
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.exti_port = AFIO_EXTI_PF,
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};
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/** GPIO port F device. */
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gpio_dev* const GPIOF = &gpiof;
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gpio_dev gpiog = {
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.regs = GPIOG_BASE,
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.clk_id = RCC_GPIOG,
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.exti_port = AFIO_EXTI_PG,
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};
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/** GPIO port G device. */
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gpio_dev* const GPIOG = &gpiog;
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#endif
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/*
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* GPIO convenience routines
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*/
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/**
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* Initialize a GPIO device.
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*
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* Enables the clock for and resets the given device.
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*
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* @param dev GPIO device to initialize.
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*/
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void gpio_init(gpio_dev *dev) {
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rcc_clk_enable(dev->clk_id);
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rcc_reset_dev(dev->clk_id);
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}
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/**
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* Initialize and reset all available GPIO devices.
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*/
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void gpio_init_all(void) {
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gpio_init(GPIOA);
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gpio_init(GPIOB);
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gpio_init(GPIOC);
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gpio_init(GPIOD);
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#ifdef STM32_HIGH_DENSITY
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gpio_init(GPIOE);
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gpio_init(GPIOF);
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gpio_init(GPIOG);
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#endif
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#ifdef ARDUINO_STM32F4_NETDUINO2PLUS
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// PA8 Output the Master Clock MCO1
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gpio_set_af_mode(GPIOA, 8, 0);
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gpio_set_mode(GPIOA, 8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
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// PB4 as alternate MISO Input
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gpio_set_af_mode(GPIOB, 4, 5);
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// PA5 as alternate SCK Output
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gpio_set_af_mode(GPIOA, 5, 5);
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// PA7 as alternate MOSI Output
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gpio_set_af_mode(GPIOA, 7, 5);
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#endif
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}
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/**
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* Set the mode of a GPIO pin.
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*
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* @param dev GPIO device.
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* @param pin Pin on the device whose mode to set, 0--15.
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* @param mode General purpose or alternate function mode to set the pin to.
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* @see gpio_pin_mode
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*/
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void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
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gpio_reg_map *regs = dev->regs;
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//regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 8) & 15) << (4*(pin&7)));
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//gpio_set_af_mode(dev, pin, mode>>8);
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regs->MODER = (regs->MODER & ~( 3 << (2*pin))) | (((mode >> 0) & 3) << (2*pin));
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regs->PUPDR = (regs->PUPDR & ~( 3 << (2*pin))) | (((mode >> 2) & 3) << (2*pin));
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regs->OSPEEDR = (regs->OSPEEDR & ~( 3 << (2*pin))) | (((mode >> 4) & 3) << (2*pin));
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regs->OTYPER = (regs->OTYPER & ~( 1 << (1*pin))) | (((mode >> 6) & 1) << (1*pin));
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}
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/**
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* Set the alternate function mode of a GPIO pin.
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*
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* @param dev GPIO device.
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* @param pin Pin on the device whose mode to set, 0--15.
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* @param mode alternate function mode to set the pin to.
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* @see gpio_pin_mode
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*/
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void gpio_set_af_mode(gpio_dev *dev, uint8 pin, int mode) {
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gpio_reg_map *regs = dev->regs;
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regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 0) & 15) << (4*(pin&7)));
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}
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/*
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* AFIO
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*/
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/**
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* @brief Initialize the AFIO clock, and reset the AFIO registers.
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*/
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void afio_init(void) {
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//rcc_clk_enable(RCC_AFIO);
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//rcc_reset_dev(RCC_AFIO);
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}
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#define AFIO_EXTI_SEL_MASK 0xF
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/**
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* @brief Select a source input for an external interrupt.
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*
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* @param exti External interrupt.
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* @param gpio_port Port which contains pin to use as source input.
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* @see afio_exti_num
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* @see afio_exti_port
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*/
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void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port) {
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__io uint32 *exti_cr = &SYSCFG_BASE->EXTICR1 + exti / 4;
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uint32 shift = 4 * (exti % 4);
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uint32 cr = *exti_cr;
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cr &= ~(AFIO_EXTI_SEL_MASK << shift);
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cr |= gpio_port << shift;
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*exti_cr = cr;
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}
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/**
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* @brief Perform an alternate function remap.
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* @param remapping Remapping to perform.
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*/
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#if 0
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void afio_remap(afio_remap_peripheral remapping) {
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if (remapping & AFIO_REMAP_USE_MAPR2) {
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remapping &= ~AFIO_REMAP_USE_MAPR2;
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AFIO_BASE->MAPR2 |= remapping;
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} else {
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AFIO_BASE->MAPR |= remapping;
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}
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}
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#endif
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#endif
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