82 lines
2.6 KiB
C++
82 lines
2.6 KiB
C++
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2011 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file generic_f407v.cpp
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* @author ala42
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* @brief generic_f407v board file.
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*/
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#ifdef BOARD_generic_f407v
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#include "generic_f407v.h"
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#include "wirish_types.h"
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//static void initSRAMChip(void);
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/*****************************************************************************/
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// Alternate functions, see DocID022152 Rev 8, Table 9.
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/*****************************************************************************/
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void boardInit(void) {
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/* // remap TIMER8 to PC6-9
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gpio_set_af_mode(GPIOC, 6, 3);
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gpio_set_af_mode(GPIOC, 7, 3);
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gpio_set_af_mode(GPIOC, 8, 3);
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gpio_set_af_mode(GPIOC, 9, 3);
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// remap TIMER1 to PE9,11,13,14
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gpio_set_af_mode(GPIOE, 9, 1);
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gpio_set_af_mode(GPIOE, 11, 1);
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gpio_set_af_mode(GPIOE, 13, 1);
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gpio_set_af_mode(GPIOE, 14, 1);
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// remap TIMER3 to PB4,5,0,1
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gpio_set_af_mode(GPIOB, 4, 2);
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gpio_set_af_mode(GPIOB, 5, 2);
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gpio_set_af_mode(GPIOB, 0, 2);
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gpio_set_af_mode(GPIOB, 1, 2);
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//gpio_set_af_mode(GPIOA, 2, 7);
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//gpio_set_af_mode(GPIOA, 3, 7);
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*/
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return;
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}
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/*
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static void initSRAMChip(void) {
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fsmc_nor_psram_reg_map *regs = FSMC_NOR_PSRAM1_BASE;
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fsmc_sram_init_gpios();
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rcc_clk_enable(RCC_FSMC);
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regs->BCR = (FSMC_BCR_WREN | FSMC_BCR_MWID_16BITS | FSMC_BCR_MTYP_SRAM |
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FSMC_BCR_MBKEN);
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fsmc_nor_psram_set_addset(regs, 0);
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fsmc_nor_psram_set_datast(regs, 3);
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}
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*/
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#endif
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