170 lines
6.0 KiB
C
170 lines
6.0 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Bryan Newbold.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file dac.h
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* @brief Digital to analog converter support.
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*/
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/* See notes/dac.txt for more info */
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#ifndef _DAC_H_
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#define _DAC_H_
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#include "rcc.h"
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#ifdef __cplusplus
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extern "C"{
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#endif
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/*
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* Register maps
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*/
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/** DAC register map. */
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typedef struct dac_reg_map {
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__io uint32 CR; /**< Control register */
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__io uint32 SWTRIGR; /**< Software trigger register */
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__io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
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holding register */
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__io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
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holding register */
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__io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data
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holding register */
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__io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
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holding register */
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__io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
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holding register */
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__io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data
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holding register */
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__io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
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holding register */
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__io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
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holding register */
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__io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding
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register */
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__io uint32 DOR1; /**< Channel 1 data output register */
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__io uint32 DOR2; /**< Channel 2 data output register */
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} dac_reg_map;
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/** DAC register map base address */
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#define DAC_BASE ((struct dac_reg_map*)0x40007400)
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/*
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* Devices
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*/
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/** DAC device type. */
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typedef struct dac_dev {
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dac_reg_map *regs; /**< Register map */
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} dac_dev;
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extern const dac_dev *DAC;
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/*
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* Register bit definitions
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*/
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/* Control register */
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/* Channel 1 control */
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#define DAC_CR_EN1 BIT(0) /* Enable */
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#define DAC_CR_BOFF1 BIT(1) /* Output buffer disable */
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#define DAC_CR_TEN1 BIT(2) /* Trigger enable */
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#define DAC_CR_TSEL1 (0x7 << 3) /* Trigger selection */
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#define DAC_CR_WAVE1 (0x3 << 6) /* Noise/triangle wave enable */
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#define DAC_CR_MAMP1 (0xF << 8) /* Mask/amplitude selector */
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#define DAC_CR_DMAEN1 BIT(12) /* DMA enable */
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/* Channel 2 control */
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#define DAC_CR_EN2 BIT(16) /* Enable */
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#define DAC_CR_BOFF2 BIT(17) /* Output buffer disable */
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#define DAC_CR_TEN2 BIT(18) /* Trigger enable */
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#define DAC_CR_TSEL2 (0x7 << 19) /* Trigger selection */
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#define DAC_CR_WAVE2 (0x3 << 22) /* Noise/triangle wave generation*/
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#define DAC_CR_MAMP2 (0xF << 24) /* Mask/amplitude selector */
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#define DAC_CR_DMAEN2 BIT(28) /* DMA enable */
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/* Software trigger register */
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#define DAC_SWTRIGR_SWTRIG1 BIT(0) /* Channel 1 software trigger */
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#define DAC_SWTRIGR_SWTRIG2 BIT(1) /* Channel 2 software trigger */
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/* Channel 1 12-bit right-aligned data holding register */
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#define DAC_DHR12R1_DACC1DHR 0x00000FFF
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/* Channel 1 12-bit left-aligned data holding register */
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#define DAC_DHR12L1_DACC1DHR 0x0000FFF0
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/* Channel 1 8-bit left-aligned data holding register */
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#define DAC_DHR8R1_DACC1DHR 0x000000FF
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/* Channel 2 12-bit right-aligned data holding register */
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#define DAC_DHR12R2_DACC2DHR 0x00000FFF
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/* Channel 2 12-bit left-aligned data holding register */
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#define DAC_DHR12L2_DACC2DHR 0x0000FFF0
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/* Channel 2 8-bit left-aligned data holding register */
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#define DAC_DHR8R2_DACC2DHR 0x000000FF
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/* Dual DAC 12-bit right-aligned data holding register */
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#define DAC_DHR12RD_DACC1DHR 0x00000FFF
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#define DAC_DHR12RD_DACC2DHR 0x0FFF0000
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/* Dual DAC 12-bit left-aligned data holding register */
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#define DAC_DHR12LD_DACC1DHR 0x0000FFF0
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#define DAC_DHR12LD_DACC2DHR 0xFFF00000
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/* Dual DAC 8-bit left-aligned data holding register */
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#define DAC_DHR8RD_DACC1DHR 0x000000FF
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#define DAC_DHR8RD_DACC2DHR 0x0000FF00
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/* Channel 1 data output register */
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#define DAC_DOR1_DACC1DOR 0x00000FFF
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/* Channel 1 data output register */
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#define DAC_DOR2_DACC2DOR 0x00000FFF
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/*
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* Convenience functions
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*/
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/* We take the dev argument in these convenience functions for
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* future-proofing */
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#define DAC_CH1 0x1
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#define DAC_CH2 0x2
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void dac_init(const dac_dev *dev, uint32 flags);
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void dac_write_channel(const dac_dev *dev, uint8 channel, uint16 val);
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void dac_enable_channel(const dac_dev *dev, uint8 channel);
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void dac_disable_channel(const dac_dev *dev, uint8 channel);
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void dac_enable_buffer(const dac_dev *dev, uint32 flags, int status);
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif
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