234 lines
8.2 KiB
C
234 lines
8.2 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Perry Hung.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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#ifdef STM32F1
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/**
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* @file rcc.c
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* @brief Implements pretty much only the basic clock setup on the
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* stm32, clock enable/disable and peripheral reset commands.
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*/
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#include "libmaple.h"
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#include "flash.h"
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#include "rcc.h"
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#include "bitband.h"
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#define APB1 RCC_APB1
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#define APB2 RCC_APB2
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#define AHB RCC_AHB
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struct rcc_dev_info {
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const rcc_clk_domain clk_domain;
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const uint8 line_num;
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};
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/* Device descriptor table, maps rcc_clk_id onto bus and enable/reset
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* register bit numbers. */
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static const struct rcc_dev_info rcc_dev_table[] = {
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[RCC_GPIOA] = { .clk_domain = APB2, .line_num = 2 },
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[RCC_GPIOB] = { .clk_domain = APB2, .line_num = 3 },
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[RCC_GPIOC] = { .clk_domain = APB2, .line_num = 4 },
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[RCC_GPIOD] = { .clk_domain = APB2, .line_num = 5 },
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[RCC_AFIO] = { .clk_domain = APB2, .line_num = 0 },
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[RCC_ADC1] = { .clk_domain = APB2, .line_num = 9 },
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[RCC_ADC2] = { .clk_domain = APB2, .line_num = 10 },
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[RCC_ADC3] = { .clk_domain = APB2, .line_num = 15 },
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[RCC_USART1] = { .clk_domain = APB2, .line_num = 14 },
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[RCC_USART2] = { .clk_domain = APB1, .line_num = 17 },
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[RCC_USART3] = { .clk_domain = APB1, .line_num = 18 },
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[RCC_TIMER1] = { .clk_domain = APB2, .line_num = 11 },
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[RCC_TIMER2] = { .clk_domain = APB1, .line_num = 0 },
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[RCC_TIMER3] = { .clk_domain = APB1, .line_num = 1 },
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[RCC_TIMER4] = { .clk_domain = APB1, .line_num = 2 },
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[RCC_SPI1] = { .clk_domain = APB2, .line_num = 12 },
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[RCC_SPI2] = { .clk_domain = APB1, .line_num = 14 },
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[RCC_DMA1] = { .clk_domain = AHB, .line_num = 0 },
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[RCC_PWR] = { .clk_domain = APB1, .line_num = 28},
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[RCC_BKP] = { .clk_domain = APB1, .line_num = 27},
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[RCC_I2C1] = { .clk_domain = APB1, .line_num = 21 },
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[RCC_I2C2] = { .clk_domain = APB1, .line_num = 22 },
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[RCC_CRC] = { .clk_domain = AHB, .line_num = 6},
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[RCC_FLITF] = { .clk_domain = AHB, .line_num = 4},
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[RCC_SRAM] = { .clk_domain = AHB, .line_num = 2},
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#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
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[RCC_GPIOE] = { .clk_domain = APB2, .line_num = 6 },
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[RCC_GPIOF] = { .clk_domain = APB2, .line_num = 7 },
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[RCC_GPIOG] = { .clk_domain = APB2, .line_num = 8 },
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[RCC_UART4] = { .clk_domain = APB1, .line_num = 19 },
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[RCC_UART5] = { .clk_domain = APB1, .line_num = 20 },
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[RCC_TIMER5] = { .clk_domain = APB1, .line_num = 3 },
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[RCC_TIMER6] = { .clk_domain = APB1, .line_num = 4 },
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[RCC_TIMER7] = { .clk_domain = APB1, .line_num = 5 },
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[RCC_TIMER8] = { .clk_domain = APB2, .line_num = 13 },
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[RCC_FSMC] = { .clk_domain = AHB, .line_num = 8 },
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[RCC_DAC] = { .clk_domain = APB1, .line_num = 29 },
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[RCC_DMA2] = { .clk_domain = AHB, .line_num = 1 },
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[RCC_SDIO] = { .clk_domain = AHB, .line_num = 10 },
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[RCC_SPI3] = { .clk_domain = APB1, .line_num = 15 },
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#endif
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#ifdef STM32_XL_DENSITY
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[RCC_TIMER9] = { .clk_domain = APB2, .line_num = 19 },
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[RCC_TIMER10] = { .clk_domain = APB2, .line_num = 20 },
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[RCC_TIMER11] = { .clk_domain = APB2, .line_num = 21 },
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[RCC_TIMER12] = { .clk_domain = APB1, .line_num = 6 },
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[RCC_TIMER13] = { .clk_domain = APB1, .line_num = 7 },
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[RCC_TIMER14] = { .clk_domain = APB1, .line_num = 8 },
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#endif
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};
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/**
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* @brief Initialize the clock control system. Initializes the system
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* clock source to use the PLL driven by an external oscillator
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* @param sysclk_src system clock source, must be PLL
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* @param pll_src pll clock source, must be HSE
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* @param pll_mul pll multiplier
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*/
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void rcc_clk_init(rcc_sysclk_src sysclk_src,
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rcc_pllsrc pll_src,
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rcc_pll_multiplier pll_mul) {
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uint32 cfgr = 0;
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uint32 cr;
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/* Assume that we're going to clock the chip off the PLL, fed by
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* the HSE */
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ASSERT(sysclk_src == RCC_CLKSRC_PLL &&
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pll_src == RCC_PLLSRC_HSE);
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RCC_BASE->CFGR = pll_src | pll_mul;
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/* Turn on the HSE */
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cr = RCC_BASE->CR;
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cr |= RCC_CR_HSEON;
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RCC_BASE->CR = cr;
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while (!(RCC_BASE->CR & RCC_CR_HSERDY))
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;
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/* Now the PLL */
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cr |= RCC_CR_PLLON;
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RCC_BASE->CR = cr;
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while (!(RCC_BASE->CR & RCC_CR_PLLRDY))
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;
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/* Finally, let's switch over to the PLL */
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cfgr &= ~RCC_CFGR_SW;
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cfgr |= RCC_CFGR_SW_PLL;
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RCC_BASE->CFGR = cfgr;
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while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
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;
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}
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/**
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* @brief Turn on the clock line on a peripheral
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* @param id Clock ID of the peripheral to turn on.
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*/
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void rcc_clk_enable(rcc_clk_id id) {
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static const __io uint32* enable_regs[] = {
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[APB1] = &RCC_BASE->APB1ENR,
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[APB2] = &RCC_BASE->APB2ENR,
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[AHB] = &RCC_BASE->AHBENR,
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};
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rcc_clk_domain clk_domain = rcc_dev_clk(id);
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__io uint32* enr = (__io uint32*)enable_regs[clk_domain];
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uint8 lnum = rcc_dev_table[id].line_num;
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bb_peri_set_bit(enr, lnum, 1);
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}
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/**
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* @brief Reset a peripheral.
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* @param id Clock ID of the peripheral to reset.
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*/
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void rcc_reset_dev(rcc_clk_id id) {
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static const __io uint32* reset_regs[] = {
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[APB1] = &RCC_BASE->APB1RSTR,
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[APB2] = &RCC_BASE->APB2RSTR,
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};
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rcc_clk_domain clk_domain = rcc_dev_clk(id);
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__io void* addr = (__io void*)reset_regs[clk_domain];
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uint8 lnum = rcc_dev_table[id].line_num;
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bb_peri_set_bit(addr, lnum, 1);
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bb_peri_set_bit(addr, lnum, 0);
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}
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/**
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* @brief Get a peripheral's clock domain
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* @param id Clock ID of the peripheral whose clock domain to return
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* @return Clock source for the given clock ID
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*/
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rcc_clk_domain rcc_dev_clk(rcc_clk_id id) {
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return rcc_dev_table[id].clk_domain;
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}
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/**
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* @brief Get a peripheral's clock domain speed
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* @param id Clock ID of the peripheral whose clock domain speed to return
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* @return Clock speed for the given clock ID
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*/
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uint32 rcc_dev_clk_speed(rcc_clk_id id) {
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static const uint32 rcc_dev_clk_speed_table[] = {
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[RCC_AHB] = 72000000,
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[RCC_APB1] = 36000000,
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[RCC_APB2] = 72000000
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};
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return rcc_dev_clk_speed_table[rcc_dev_clk(id)];
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}
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/**
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* @brief Get a peripheral's timer clock domain speed
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* @param id Clock ID of the peripheral whose clock domain speed to return
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* @return Clock speed for the given clock ID
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*/
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uint32 rcc_dev_timer_clk_speed(rcc_clk_id id) {
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return rcc_dev_clk_speed(RCC_APB2); // 72 MHz for all counter
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}
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/**
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* @brief Set the divider on a peripheral prescaler
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* @param prescaler prescaler to set
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* @param divider prescaler divider
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*/
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void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
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static const uint32 masks[] = {
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[RCC_PRESCALER_AHB] = RCC_CFGR_HPRE,
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[RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1,
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[RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2,
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[RCC_PRESCALER_USB] = RCC_CFGR_USBPRE,
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[RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE,
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};
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uint32 cfgr = RCC_BASE->CFGR;
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cfgr &= ~masks[prescaler];
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cfgr |= divider;
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RCC_BASE->CFGR = cfgr;
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}
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#endif
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