177 lines
7.0 KiB
C
177 lines
7.0 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2011,2012 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/stm32f2/include/series/timer.h
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* @author Marti Bolivar <mbolivar@leaflabs.com>
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* @brief STM32F2 timer support.
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*/
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#ifndef _LIBMAPLE_STM32F2_TIMER_H_
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#define _LIBMAPLE_STM32F2_TIMER_H_
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#include <libmaple/libmaple_types.h>
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#include <libmaple/gpio.h> /* for gpio_af */
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/*
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* Register maps and base pointers
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*/
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/**
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* @brief STM32F2 general purpose timer register map type
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*
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* Note that not all general purpose timers have all of these
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* registers. Consult your chip's reference manual for the details.
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*/
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typedef struct timer_gen_reg_map {
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__io uint32 CR1; /**< Control register 1 */
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__io uint32 CR2; /**< Control register 2 */
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__io uint32 SMCR; /**< Slave mode control register */
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__io uint32 DIER; /**< DMA/Interrupt enable register */
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__io uint32 SR; /**< Status register */
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__io uint32 EGR; /**< Event generation register */
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__io uint32 CCMR1; /**< Capture/compare mode register 1 */
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__io uint32 CCMR2; /**< Capture/compare mode register 2 */
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__io uint32 CCER; /**< Capture/compare enable register */
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__io uint32 CNT; /**< Counter */
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__io uint32 PSC; /**< Prescaler */
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__io uint32 ARR; /**< Auto-reload register */
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const uint32 RESERVED1; /**< Reserved */
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__io uint32 CCR1; /**< Capture/compare register 1 */
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__io uint32 CCR2; /**< Capture/compare register 2 */
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__io uint32 CCR3; /**< Capture/compare register 3 */
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__io uint32 CCR4; /**< Capture/compare register 4 */
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const uint32 RESERVED2; /**< Reserved */
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__io uint32 DCR; /**< DMA control register */
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__io uint32 DMAR; /**< DMA address for full transfer */
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__io uint32 OR; /**< Option register. */
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} timer_gen_reg_map;
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struct timer_adv_reg_map;
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struct timer_bas_reg_map;
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/** Timer 1 register map base pointer */
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#define TIMER1_BASE ((struct timer_adv_reg_map*)0x40010000)
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/** Timer 2 register map base pointer */
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#define TIMER2_BASE ((struct timer_gen_reg_map*)0x40000000)
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/** Timer 3 register map base pointer */
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#define TIMER3_BASE ((struct timer_gen_reg_map*)0x40000400)
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/** Timer 4 register map base pointer */
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#define TIMER4_BASE ((struct timer_gen_reg_map*)0x40000800)
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/** Timer 5 register map base pointer */
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#define TIMER5_BASE ((struct timer_gen_reg_map*)0x40000C00)
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/** Timer 6 register map base pointer */
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#define TIMER6_BASE ((struct timer_bas_reg_map*)0x40001000)
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/** Timer 7 register map base pointer */
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#define TIMER7_BASE ((struct timer_bas_reg_map*)0x40001400)
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/** Timer 8 register map base pointer */
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#define TIMER8_BASE ((struct timer_adv_reg_map*)0x40010400)
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/** Timer 9 register map base pointer */
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#define TIMER9_BASE ((struct timer_gen_reg_map*)0x40014000)
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/** Timer 10 register map base pointer */
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#define TIMER10_BASE ((struct timer_gen_reg_map*)0x40014400)
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/** Timer 11 register map base pointer */
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#define TIMER11_BASE ((struct timer_gen_reg_map*)0x40014800)
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/** Timer 12 register map base pointer */
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#define TIMER12_BASE ((struct timer_gen_reg_map*)0x40001800)
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/** Timer 13 register map base pointer */
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#define TIMER13_BASE ((struct timer_gen_reg_map*)0x40001C00)
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/** Timer 14 register map base pointer */
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#define TIMER14_BASE ((struct timer_gen_reg_map*)0x40002000)
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/*
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* Register bit definitions
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*/
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/* TIM2 option register */
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/** Timer 2 option register internal trigger 1 remap */
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#define TIMER2_OR_ITR1_RMP (0x3 << 10)
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/** Timer 2 OR internal trigger 1: TIM8_TRGOUT */
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#define TIMER2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10)
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/** Timer 2 OR internal trigger 1: Ethernet PTP trigger output */
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#define TIMER2_OR_ITR1_RMP_PTP_TRGOUT (0x1 << 10)
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/** Timer 2 OR internal trigger 1: USB OTG full speed start of frame */
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#define TIMER2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
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/** Timer 2 OR internal trigger 1: USB OTG high speed start of frame */
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#define TIMER2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
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/* TIM5 option register */
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/**
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* Timer 5 option register input 4 remap.
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*
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* These bits control whether TIM5_CH4 is connected to a GPIO or a
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* clock. Connecting to a GPIO is the normal mode, useful for e.g. PWM
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* generation or input pulse duration measurement. Connecting to a
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* clock is useful for calibrating that clock.
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*/
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#define TIMER5_OR_TI4_RMP (0x3 << 6)
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/**
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* Timer 5 OR input 4: Timer 5 channel 4 connected to GPIO. */
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#define TIMER5_OR_TI4_RMP_GPIO (0x0 << 6)
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/**
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* Timer 5 OR input 4: low speed internal clock (LSI) is connected to
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* TIM5_CH4. */
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#define TIMER5_OR_TI4_RMP_LSI (0x1 << 6)
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/**
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* Timer 5 OR input 4: low speed external clock (LSE) is connected to
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* TIM5_CH4. */
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#define TIMER5_OR_TI4_RMP_LSE (0x2 << 6)
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/**
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* Timer 5 OR input 4: real time clock (RTC) output is connected to
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* TIM5_CH4. */
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#define TIMER5_OR_TI4_RMP_RTC (0x3 << 6)
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/*
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* Device pointers
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*/
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struct timer_dev;
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extern struct timer_dev *TIMER1;
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extern struct timer_dev *TIMER2;
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extern struct timer_dev *TIMER3;
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extern struct timer_dev *TIMER4;
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extern struct timer_dev *TIMER5;
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extern struct timer_dev *TIMER6;
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extern struct timer_dev *TIMER7;
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extern struct timer_dev *TIMER8;
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extern struct timer_dev *TIMER9;
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extern struct timer_dev *TIMER10;
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extern struct timer_dev *TIMER11;
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extern struct timer_dev *TIMER12;
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extern struct timer_dev *TIMER13;
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extern struct timer_dev *TIMER14;
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/*
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* Routines
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*/
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gpio_af timer_get_af(struct timer_dev *dev);
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#endif
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