256 lines
10 KiB
C
256 lines
10 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2012 LeafLabs, LLC.
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* Copyright (c) 2010 Perry Hung.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/stm32f1/include/series/adc.h
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* @author Marti Bolivar <mbolivar@leaflabs.com>,
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* Perry Hung <perry@leaflabs.com>
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* @brief STM32F1 ADC header.
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*/
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#ifndef _LIBMAPLE_STM32F1_ADC_H_
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#define _LIBMAPLE_STM32F1_ADC_H_
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#include <libmaple/bitband.h>
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#include <libmaple/libmaple_types.h>
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#include <libmaple/rcc.h> /* For the prescalers */
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/*
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* Devices
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*/
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extern adc_dev adc1;
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extern const struct adc_dev *ADC1;
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extern adc_dev adc2;
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extern const struct adc_dev *ADC2;
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#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
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extern adc_dev adc3;
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extern const struct adc_dev *ADC3;
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#endif
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/*
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* Register map base pointers
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*/
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/** STM32F1 ADC1 register map base pointer. */
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#define ADC1_BASE ((struct adc_reg_map*)0x40012400)
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/** STM32F1 ADC2 register map base pointer. */
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#define ADC2_BASE ((struct adc_reg_map*)0x40012800)
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/** STM32F1 ADC3 register map base pointer. */
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#define ADC3_BASE ((struct adc_reg_map*)0x40013C00)
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/*
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* Register bit definitions
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*/
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/* Control register 2 */
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#define ADC_CR2_ADON_BIT 0
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#define ADC_CR2_CONT_BIT 1
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#define ADC_CR2_CAL_BIT 2
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#define ADC_CR2_RSTCAL_BIT 3
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#define ADC_CR2_DMA_BIT 8
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#define ADC_CR2_ALIGN_BIT 11
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#define ADC_CR2_JEXTTRIG_BIT 15
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#define ADC_CR2_EXTTRIG_BIT 20
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#define ADC_CR2_JSWSTART_BIT 21
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#define ADC_CR2_SWSTART_BIT 22
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#define ADC_CR2_TSEREFE_BIT 23
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#define ADC_CR2_ADON (1U << ADC_CR2_ADON_BIT)
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#define ADC_CR2_CONT (1U << ADC_CR2_CONT_BIT)
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#define ADC_CR2_CAL (1U << ADC_CR2_CAL_BIT)
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#define ADC_CR2_RSTCAL (1U << ADC_CR2_RSTCAL_BIT)
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#define ADC_CR2_DMA (1U << ADC_CR2_DMA_BIT)
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#define ADC_CR2_ALIGN (1U << ADC_CR2_ALIGN_BIT)
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#define ADC_CR2_JEXTSEL 0x7000
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#define ADC_CR2_JEXTTRIG (1U << ADC_CR2_JEXTTRIG_BIT)
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#define ADC_CR2_EXTSEL 0xE0000
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#define ADC_CR2_EXTTRIG (1U << ADC_CR2_EXTTRIG_BIT)
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#define ADC_CR2_JSWSTART (1U << ADC_CR2_JSWSTART_BIT)
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#define ADC_CR2_SWSTART (1U << ADC_CR2_SWSTART_BIT)
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#define ADC_CR2_TSEREFE (1U << ADC_CR2_TSEREFE_BIT)
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/*
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* Other types
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*/
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/**
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* @brief STM32F1 external event selectors for regular group
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* conversion.
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*
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* Some external events are only available on ADCs 1 and 2, others
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* only on ADC3, while others are available on all three ADCs.
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* Additionally, some events are only available on high- and
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* XL-density STM32F1 MCUs, as they use peripherals only available on
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* those MCU densities.
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*
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* For ease of use, each event selector is given along with the ADCs
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* it's available on, along with any other availability restrictions.
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*
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* @see adc_set_extsel()
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*/
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typedef enum adc_extsel_event {
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/* TODO: Smarten this up a bit, as follows.
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*
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* The EXTSEL bits on F1 are a little brain-damaged in that the
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* TIM8 TRGO event has different bits depending on whether you're
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* using ADC1/2 or ADC3. We route around this by declaring two
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* enumerators, ADC_EXT_EV_ADC12_TIM8_TRGO and
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* ADC_EXT_EV_ADC3_TIM8_TRGO.
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*
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* The right thing to do is to provide a single
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* ADC_EXT_EV_TIM8_TRGO enumerator and override adc_set_extsel on
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* STM32F1 to handle this situation correctly. We can do that
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* later, though, and change the per-ADC enumerator values to
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* ADC_EXT_EV_TIM8_TRGO to preserve compatibility. */
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/* ADC1 and ADC2 only: */
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ADC_EXT_EV_TIM1_CC1 = 0x00000, /**< ADC1, ADC2: Timer 1 CC1 event */
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ADC_EXT_EV_TIM1_CC2 = 0x20000, /**< ADC1, ADC2: Timer 1 CC2 event */
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ADC_EXT_EV_TIM2_CC2 = 0x60000, /**< ADC1, ADC2: Timer 2 CC2 event */
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ADC_EXT_EV_TIM3_TRGO = 0x80000, /**< ADC1, ADC2: Timer 3 TRGO event */
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ADC_EXT_EV_TIM4_CC4 = 0xA0000, /**< ADC1, ADC2: Timer 4 CC4 event */
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ADC_EXT_EV_EXTI11 = 0xC0000, /**< ADC1, ADC2: EXTI11 event */
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/* Common: */
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ADC_EXT_EV_TIM1_CC3 = 0x40000, /**< ADC1, ADC2, ADC3: Timer 1 CC3 event */
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ADC_EXT_EV_SWSTART = 0xE0000, /**< ADC1, ADC2, ADC3: Software start */
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/* HD only: */
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ADC_EXT_EV_TIM3_CC1 = 0x00000, /**<
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* ADC3: Timer 3 CC1 event
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* Availability: high- and XL-density. */
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ADC_EXT_EV_TIM2_CC3 = 0x20000, /**<
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* ADC3: Timer 2 CC3 event
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* Availability: high- and XL-density. */
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ADC_EXT_EV_TIM8_CC1 = 0x60000, /**<
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* ADC3: Timer 8 CC1 event
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* Availability: high- and XL-density. */
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ADC_EXT_EV_ADC3_TIM8_TRGO = 0x80000, /**<
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* ADC3: Timer 8 TRGO event
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* Availability: high- and XL-density. */
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ADC_EXT_EV_TIM5_CC1 = 0xA0000, /**<
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* ADC3: Timer 5 CC1 event
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* Availability: high- and XL-density. */
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ADC_EXT_EV_ADC12_TIM8_TRGO = 0xC0000, /**<
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* ADC1, ADC2: Timer 8 TRGO event
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* Availability: high- and XL-density. */
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ADC_EXT_EV_TIM5_CC3 = 0xC0000, /**<
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* ADC3: Timer 5 CC3 event
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* Availability: high- and XL-density. */
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} adc_extsel_event;
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/* We'll keep these old adc_extsel_event enumerators around for a
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* while, for backwards compatibility: */
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/** Deprecated. Use ADC_EXT_EV_TIM1_CC1 instead. */
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#define ADC_ADC12_TIM1_CC1 ADC_EXT_EV_TIM1_CC1
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/** Deprecated. Use ADC_EXT_EV_TIM1_CC2 instead. */
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#define ADC_ADC12_TIM1_CC2 ADC_EXT_EV_TIM1_CC2
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/** Deprecated. Use ADC_EXT_EV_TIM1_CC3 instead. */
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#define ADC_ADC12_TIM1_CC3 ADC_EXT_EV_TIM1_CC3
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/** Deprecated. Use ADC_EXT_EV_TIM2_CC2 instead. */
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#define ADC_ADC12_TIM2_CC2 ADC_EXT_EV_TIM2_CC2
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/** Deprecated. Use ADC_EXT_EV_TIM3_TRGO instead. */
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#define ADC_ADC12_TIM3_TRGO ADC_EXT_EV_TIM3_TRGO
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/** Deprecated. Use ADC_EXT_EV_TIM4_CC4 instead. */
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#define ADC_ADC12_TIM4_CC4 ADC_EXT_EV_TIM4_CC4
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/** Deprecated. Use ADC_EXT_EV_EXTI11 instead. */
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#define ADC_ADC12_EXTI11 ADC_EXT_EV_EXTI11
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/** Deprecated. Use ADC_EXT_EV_ADC12_TIM8_TRGO instead. */
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#define ADC_ADC12_TIM8_TRGO ADC_EXT_EV_ADC12_TIM8_TRGO
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/** Deprecated. Use ADC_EXT_EV_SWSTART instead. */
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#define ADC_ADC12_SWSTART ADC_EXT_EV_SWSTART
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/** Deprecated. Use ADC_EXT_EV_TIM1_CC1 instead. */
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#define ADC_ADC3_TIM3_CC1 ADC_EXT_EV_TIM1_CC1
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/** Deprecated. Use ADC_EXT_EV_TIM1_CC2 instead. */
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#define ADC_ADC3_TIM2_CC3 ADC_EXT_EV_TIM1_CC2
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/** Deprecated. Use ADC_EXT_EV_TIM1_CC3 instead. */
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#define ADC_ADC3_TIM1_CC3 ADC_EXT_EV_TIM1_CC3
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/** Deprecated. Use ADC_EXT_EV_TIM2_CC2 instead. */
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#define ADC_ADC3_TIM8_CC1 ADC_EXT_EV_TIM2_CC2
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/** Deprecated. Use ADC_EXT_EV_TIM3_TRGO instead. */
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#define ADC_ADC3_TIM8_TRGO ADC_EXT_EV_TIM3_TRGO
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/** Deprecated. Use ADC_EXT_EV_TIM4_CC4 instead. */
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#define ADC_ADC3_TIM5_CC1 ADC_EXT_EV_TIM4_CC4
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/** Deprecated. Use ADC_EXT_EV_EXTI11 instead. */
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#define ADC_ADC3_TIM5_CC3 ADC_EXT_EV_EXTI11
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/** Deprecated. Use ADC_EXT_EV_TIM8_TRGO instead. */
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#define ADC_ADC3_SWSTART ADC_EXT_EV_TIM8_TRGO
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/** Deprecated. Use ADC_EXT_EV_SWSTART instead. */
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#define ADC_SWSTART ADC_EXT_EV_SWSTART
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/**
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* @brief STM32F1 sample times, in ADC clock cycles.
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*
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* These control the amount of time spent sampling the input voltage.
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*/
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typedef enum adc_smp_rate {
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ADC_SMPR_1_5, /**< 1.5 ADC cycles */
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ADC_SMPR_7_5, /**< 7.5 ADC cycles */
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ADC_SMPR_13_5, /**< 13.5 ADC cycles */
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ADC_SMPR_28_5, /**< 28.5 ADC cycles */
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ADC_SMPR_41_5, /**< 41.5 ADC cycles */
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ADC_SMPR_55_5, /**< 55.5 ADC cycles */
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ADC_SMPR_71_5, /**< 71.5 ADC cycles */
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ADC_SMPR_239_5, /**< 239.5 ADC cycles */
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} adc_smp_rate;
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/**
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* @brief STM32F1 ADC prescalers, as divisors of PCLK2.
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*/
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typedef enum adc_prescaler {
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/** PCLK2 divided by 2 */
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ADC_PRE_PCLK2_DIV_2 = RCC_ADCPRE_PCLK_DIV_2,
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/** PCLK2 divided by 4 */
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ADC_PRE_PCLK2_DIV_4 = RCC_ADCPRE_PCLK_DIV_4,
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/** PCLK2 divided by 6 */
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ADC_PRE_PCLK2_DIV_6 = RCC_ADCPRE_PCLK_DIV_6,
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/** PCLK2 divided by 8 */
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ADC_PRE_PCLK2_DIV_8 = RCC_ADCPRE_PCLK_DIV_8,
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} adc_prescaler;
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/*
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* Routines
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*/
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void adc_calibrate(const adc_dev *dev);
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/**
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* @brief Set external trigger conversion mode event for regular channels
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*
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* Availability: STM32F1.
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*
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* @param dev ADC device
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* @param enable If 1, conversion on external events is enabled; if 0,
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* disabled.
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*/
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static inline void adc_set_exttrig(const adc_dev *dev, uint8 enable) {
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*bb_perip(&dev->regs->CR2, ADC_CR2_EXTTRIG_BIT) = !!enable;
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}
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#endif
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