378 lines
14 KiB
C
378 lines
14 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Perry Hung.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file adc.h
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*
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* @brief Analog-to-Digital Conversion (ADC) header.
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*/
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#ifndef _ADC_H_
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#define _ADC_H_
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#include "libmaple.h"
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#include "bitband.h"
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#include "rcc.h"
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#ifdef __cplusplus
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extern "C"{
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#endif
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typedef struct
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{
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__io uint32 CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
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__io uint32 CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
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__io uint32 CDR; /*!< ADC common regular data register for dual
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AND triple modes, Address offset: ADC1 base address + 0x308 */
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} ADC_Common_TypeDef;
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#define ADC_COMMON ((ADC_Common_TypeDef *) 0x40012300)
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/** ADC register map type. */
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typedef struct adc_reg_map {
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__io uint32 SR; ///< Status register
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__io uint32 CR1; ///< Control register 1
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__io uint32 CR2; ///< Control register 2
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__io uint32 SMPR1; ///< Sample time register 1
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__io uint32 SMPR2; ///< Sample time register 2
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__io uint32 JOFR1; ///< Injected channel data offset register 1
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__io uint32 JOFR2; ///< Injected channel data offset register 2
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__io uint32 JOFR3; ///< Injected channel data offset register 3
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__io uint32 JOFR4; ///< Injected channel data offset register 4
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__io uint32 HTR; ///< Watchdog high threshold register
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__io uint32 LTR; ///< Watchdog low threshold register
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__io uint32 SQR1; ///< Regular sequence register 1
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__io uint32 SQR2; ///< Regular sequence register 2
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__io uint32 SQR3; ///< Regular sequence register 3
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__io uint32 JSQR; ///< Injected sequence register
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__io uint32 JDR1; ///< Injected data register 1
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__io uint32 JDR2; ///< Injected data register 2
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__io uint32 JDR3; ///< Injected data register 3
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__io uint32 JDR4; ///< Injected data register 4
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__io uint32 DR; ///< Regular data register
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} adc_reg_map;
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/** ADC device type. */
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typedef struct adc_dev {
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adc_reg_map *regs; /**< Register map */
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rcc_clk_id clk_id; /**< RCC clock information */
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} adc_dev;
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extern const adc_dev ADC1;
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extern const adc_dev ADC2;
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#ifdef STM32_HIGH_DENSITY
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extern const adc_dev ADC3;
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#endif
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/*
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* Register map base pointers
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*/
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/** ADC1 register map base pointer. */
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#define ADC1_BASE ((struct adc_reg_map*)0x40012000)
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/** ADC2 register map base pointer. */
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#define ADC2_BASE ((struct adc_reg_map*)0x40012100)
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/** ADC3 register map base pointer. */
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#define ADC3_BASE ((struct adc_reg_map*)0x40012200)
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/*
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* Register bit definitions
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*/
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/* Status register */
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#define ADC_SR_AWD_BIT 0
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#define ADC_SR_EOC_BIT 1
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#define ADC_SR_JEOC_BIT 2
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#define ADC_SR_JSTRT_BIT 3
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#define ADC_SR_STRT_BIT 4
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#define ADC_SR_AWD BIT(ADC_SR_AWD_BIT)
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#define ADC_SR_EOC BIT(ADC_SR_EOC_BIT)
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#define ADC_SR_JEOC BIT(ADC_SR_JEOC_BIT)
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#define ADC_SR_JSTRT BIT(ADC_SR_JSTRT_BIT)
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#define ADC_SR_STRT BIT(ADC_SR_STRT_BIT)
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/* Control register 1 */
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#define ADC_CR1_EOCIE_BIT 5
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#define ADC_CR1_AWDIE_BIT 6
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#define ADC_CR1_JEOCIE_BIT 7
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#define ADC_CR1_SCAN_BIT 8
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#define ADC_CR1_AWDSGL_BIT 9
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#define ADC_CR1_JAUTO_BIT 10
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#define ADC_CR1_DISCEN_BIT 11
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#define ADC_CR1_JDISCEN_BIT 12
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#define ADC_CR1_JAWDEN_BIT 22
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#define ADC_CR1_AWDEN_BIT 23
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#define ADC_CR1_AWDCH (0x1F)
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#define ADC_CR1_EOCIE BIT(ADC_CR1_EOCIE_BIT)
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#define ADC_CR1_AWDIE BIT(ADC_CR1_AWDIE_BIT)
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#define ADC_CR1_JEOCIE BIT(ADC_CR1_JEOCIE_BIT)
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#define ADC_CR1_SCAN BIT(ADC_CR1_SCAN_BIT)
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#define ADC_CR1_AWDSGL BIT(ADC_CR1_AWDSGL_BIT)
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#define ADC_CR1_JAUTO BIT(ADC_CR1_JAUTO_BIT)
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#define ADC_CR1_DISCEN BIT(ADC_CR1_DISCEN_BIT)
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#define ADC_CR1_JDISCEN BIT(ADC_CR1_JDISCEN_BIT)
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#define ADC_CR1_DISCNUM (0xE000)
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#define ADC_CR1_JAWDEN BIT(ADC_CR1_JAWDEN_BIT)
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#define ADC_CR1_AWDEN BIT(ADC_CR1_AWDEN_BIT)
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/* Control register 2 */
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#define ADC_CR2_ADON_BIT 0
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#define ADC_CR2_CONT_BIT 1
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#define ADC_CR2_CAL_BIT 2
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#define ADC_CR2_RSTCAL_BIT 3
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#define ADC_CR2_DMA_BIT 8
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#define ADC_CR2_ALIGN_BIT 11
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#define ADC_CR2_JEXTTRIG_BIT 15
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#define ADC_CR2_EXTTRIG_BIT 20
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#define ADC_CR2_TSVREFE_BIT 23
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#define ADC_CR2_JSWSTART_BIT 22
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#define ADC_CR2_SWSTART_BIT 30
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#define ADC_CR2_EXTSEL (0x0F000000)
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#define ADC_CR2_JEXTSEL (0x000F0000)
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#define ADC_CR2_ADON BIT(ADC_CR2_ADON_BIT)
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#define ADC_CR2_CONT BIT(ADC_CR2_CONT_BIT)
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#define ADC_CR2_CAL BIT(ADC_CR2_CAL_BIT)
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#define ADC_CR2_RSTCAL BIT(ADC_CR2_RSTCAL_BIT)
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#define ADC_CR2_DMA BIT(ADC_CR2_DMA_BIT)
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#define ADC_CR2_ALIGN BIT(ADC_CR2_ALIGN_BIT)
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#define ADC_CR2_JEXTTRIG BIT(ADC_CR2_JEXTTRIG_BIT)
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#define ADC_CR2_EXTTRIG BIT(ADC_CR2_EXTTRIG_BIT)
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#define ADC_CR2_JSWSTART BIT(ADC_CR2_JSWSTART_BIT)
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#define ADC_CR2_SWSTART BIT(ADC_CR2_SWSTART_BIT)
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#define ADC_CR2_TSVREFE BIT(ADC_CR2_TSVREFE_BIT)
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/* Sample time register 1 */
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#define ADC_SMPR1_SMP17 (0x7 << 21)
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#define ADC_SMPR1_SMP16 (0x7 << 18)
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#define ADC_SMPR1_SMP15 (0x7 << 15)
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#define ADC_SMPR1_SMP14 (0x7 << 12)
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#define ADC_SMPR1_SMP13 (0x7 << 9)
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#define ADC_SMPR1_SMP12 (0x7 << 6)
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#define ADC_SMPR1_SMP11 (0x7 << 3)
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#define ADC_SMPR1_SMP10 0x7
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/* Sample time register 2 */
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#define ADC_SMPR2_SMP9 (0x7 << 27)
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#define ADC_SMPR2_SMP8 (0x7 << 24)
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#define ADC_SMPR2_SMP7 (0x7 << 21)
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#define ADC_SMPR2_SMP6 (0x7 << 18)
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#define ADC_SMPR2_SMP5 (0x7 << 15)
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#define ADC_SMPR2_SMP4 (0x7 << 12)
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#define ADC_SMPR2_SMP3 (0x7 << 9)
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#define ADC_SMPR2_SMP2 (0x7 << 6)
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#define ADC_SMPR2_SMP1 (0x7 << 3)
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#define ADC_SMPR2_SMP0 0x7
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/* Injected channel data offset register */
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#define ADC_JOFR_JOFFSET 0x3FF
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/* Watchdog high threshold register */
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#define ADC_HTR_HT 0x3FF
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/* Watchdog low threshold register */
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#define ADC_LTR_LT 0x3FF
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/* Regular sequence register 1 */
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#define ADC_SQR1_L (0x1F << 20)
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#define ADC_SQR1_SQ16 (0x1F << 15)
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#define ADC_SQR1_SQ15 (0x1F << 10)
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#define ADC_SQR1_SQ14 (0x1F << 5)
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#define ADC_SQR1_SQ13 0x1F
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/* Regular sequence register 2 */
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#define ADC_SQR2_SQ12 (0x1F << 25)
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#define ADC_SQR2_SQ11 (0x1F << 20)
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#define ADC_SQR2_SQ10 (0x1F << 16)
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#define ADC_SQR2_SQ9 (0x1F << 10)
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#define ADC_SQR2_SQ8 (0x1F << 5)
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#define ADC_SQR2_SQ7 0x1F
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/* Regular sequence register 3 */
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#define ADC_SQR3_SQ6 (0x1F << 25)
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#define ADC_SQR3_SQ5 (0x1F << 20)
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#define ADC_SQR3_SQ4 (0x1F << 16)
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#define ADC_SQR3_SQ3 (0x1F << 10)
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#define ADC_SQR3_SQ2 (0x1F << 5)
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#define ADC_SQR3_SQ1 0x1F
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/* Injected sequence register */
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#define ADC_JSQR_JL (0x3 << 20)
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#define ADC_JSQR_JL_1CONV (0x0 << 20)
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#define ADC_JSQR_JL_2CONV (0x1 << 20)
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#define ADC_JSQR_JL_3CONV (0x2 << 20)
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#define ADC_JSQR_JL_4CONV (0x3 << 20)
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#define ADC_JSQR_JSQ4 (0x1F << 15)
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#define ADC_JSQR_JSQ3 (0x1F << 10)
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#define ADC_JSQR_JSQ2 (0x1F << 5)
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#define ADC_JSQR_JSQ1 0x1F
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/* Injected data registers */
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#define ADC_JDR_JDATA 0xFFFF
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/* Regular data register */
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#define ADC_DR_ADC2DATA (0xFFFF << 16)
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#define ADC_DR_DATA 0xFFFF
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void adc_init(const adc_dev *dev);
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/**
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* @brief External event selector for regular group conversion.
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* @see adc_set_extsel
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*/
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typedef enum adc_extsel_event {
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ADC_ADC12_TIM1_CC1 = (0 << 17), /**< ADC1 and ADC2: Timer 1 CC1 event */
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ADC_ADC12_TIM1_CC2 = (1 << 17), /**< ADC1 and ADC2: Timer 1 CC2 event */
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ADC_ADC12_TIM1_CC3 = (2 << 17), /**< ADC1 and ADC2: Timer 1 CC3 event */
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ADC_ADC12_TIM2_CC2 = (3 << 17), /**< ADC1 and ADC2: Timer 2 CC2 event */
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ADC_ADC12_TIM3_TRGO = (4 << 17), /**< ADC1 and ADC2: Timer 3 TRGO event */
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ADC_ADC12_TIM4_CC4 = (5 << 17), /**< ADC1 and ADC2: Timer 4 CC4 event */
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ADC_ADC12_EXTI11 = (6 << 17), /**< ADC1 and ADC2: EXTI11 event */
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#ifdef STM32_HIGH_DENSITY
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ADC_ADC12_TIM8_TRGO = (6 << 17), /**< ADC1 and ADC2: Timer 8 TRGO
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event (high density only) */
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#endif
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ADC_ADC12_SWSTART = (7 << 17), /**< ADC1 and ADC2: Software start */
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#ifdef STM32_HIGH_DENSITY
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ADC_ADC3_TIM3_CC1 = (0 << 17), /**< ADC3: Timer 3 CC1 event
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(high density only) */
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ADC_ADC3_TIM2_CC3 = (1 << 17), /**< ADC3: Timer 2 CC3 event
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(high density only) */
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ADC_ADC3_TIM1_CC3 = (2 << 17), /**< ADC3: Timer 1 CC3 event
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(high density only) */
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ADC_ADC3_TIM8_CC1 = (3 << 17), /**< ADC3: Timer 8 CC1 event
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(high density only) */
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ADC_ADC3_TIM8_TRGO = (4 << 17), /**< ADC3: Timer 8 TRGO event
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(high density only) */
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ADC_ADC3_TIM5_CC1 = (5 << 17), /**< ADC3: Timer 5 CC1 event
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(high density only) */
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ADC_ADC3_TIM5_CC3 = (6 << 17), /**< ADC3: Timer 5 CC3 event
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(high density only) */
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ADC_ADC3_SWSTART = (7 << 17), /**< ADC3: Software start (high
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density only) */
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#endif
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ADC_SWSTART = (7 << 17) /**< ADC1, ADC2, ADC3: Software start */
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} adc_extsel_event;
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void adc_set_extsel(const adc_dev *dev, adc_extsel_event event);
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void adc_foreach(void (*fn)(const adc_dev*));
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/**
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* @brief ADC sample times, in ADC clock cycles
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*
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* These control the amount of time spent sampling the input voltage.
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*/
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typedef enum {
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ADC_SMPR_1_5, /**< 1.5 ADC cycles */
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ADC_SMPR_7_5, /**< 7.5 ADC cycles */
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ADC_SMPR_13_5, /**< 13.5 ADC cycles */
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ADC_SMPR_28_5, /**< 28.5 ADC cycles */
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ADC_SMPR_41_5, /**< 41.5 ADC cycles */
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ADC_SMPR_55_5, /**< 55.5 ADC cycles */
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ADC_SMPR_71_5, /**< 71.5 ADC cycles */
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ADC_SMPR_239_5 /**< 239.5 ADC cycles */
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} adc_smp_rate;
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void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate);
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void adc_calibrate(const adc_dev *dev);
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uint16 adc_read(const adc_dev *dev, uint8 channel);
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/**
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* @brief Set the regular channel sequence length.
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*
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* Defines the total number of conversions in the regular channel
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* conversion sequence.
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*
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* @param dev ADC device.
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* @param length Regular channel sequence length, from 1 to 16.
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*/
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static inline void adc_set_reg_seqlen(const adc_dev *dev, uint8 length) {
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uint32 tmp = dev->regs->SQR1;
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tmp &= ~ADC_SQR1_L;
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tmp |= (length - 1) << 20;
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dev->regs->SQR1 = tmp;
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}
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/**
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* @brief Set external trigger conversion mode event for regular channels
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* @param dev ADC device
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* @param enable If 1, conversion on external events is enabled; if 0,
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* disabled.
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*/
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static inline void adc_set_exttrig(const adc_dev *dev, uint8 enable) {
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*bb_perip(&dev->regs->CR2, ADC_CR2_EXTTRIG_BIT) = !!enable;
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}
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/**
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* @brief Enable an adc peripheral
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* @param dev ADC device to enable
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*/
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static inline void adc_enable(const adc_dev *dev) {
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*bb_perip(&dev->regs->CR2, ADC_CR2_ADON_BIT) = 1;
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}
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/**
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* @brief Disable an ADC peripheral
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* @param dev ADC device to disable
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*/
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static inline void adc_disable(const adc_dev *dev) {
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*bb_perip(&dev->regs->CR2, ADC_CR2_ADON_BIT) = 0;
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}
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/**
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* @brief Disable all ADC peripherals.
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*/
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static inline void adc_disable_all(void) {
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adc_foreach(adc_disable);
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}
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extern void setupADC_F4(void);
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif
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