225 lines
6.3 KiB
C
225 lines
6.3 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Michael Hope.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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#ifdef STM32F4
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/**
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* @file dmaF4.c
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* @brief Direct Memory Access peripheral support
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*/
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#include "dma.h"
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#include "bitband.h"
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#include "util.h"
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/*
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* Devices
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*/
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static dma_dev dma1 = {
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.regs = DMA1_BASE,
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.clk_id = RCC_DMA1,
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.handlers = {{ .handler = NULL, .irq_line = 11 },
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{ .handler = NULL, .irq_line = 12 },
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{ .handler = NULL, .irq_line = 13 },
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{ .handler = NULL, .irq_line = 14 },
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{ .handler = NULL, .irq_line = 15 },
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{ .handler = NULL, .irq_line = 16 },
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{ .handler = NULL, .irq_line = 17 },
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{ .handler = NULL, .irq_line = 47 }}
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};
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/** DMA1 device */
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dma_dev *DMA1 = &dma1;
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static dma_dev dma2 = {
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.regs = DMA2_BASE,
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.clk_id = RCC_DMA2,
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.handlers = {{ .handler = NULL, .irq_line = 56 },
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{ .handler = NULL, .irq_line = 57 },
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{ .handler = NULL, .irq_line = 58 },
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{ .handler = NULL, .irq_line = 59 },
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{ .handler = NULL, .irq_line = 60 },
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{ .handler = NULL, .irq_line = 68 },
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{ .handler = NULL, .irq_line = 69 },
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{ .handler = NULL, .irq_line = 70 }} /* !@#$ */
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};
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/** DMA2 device */
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dma_dev *DMA2 = &dma2;
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/*
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* Convenience routines
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*/
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/**
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* @brief Initialize a DMA device.
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* @param dev Device to initialize.
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*/
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void dma_init(dma_dev *dev) {
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rcc_clk_enable(dev->clk_id);
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}
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/**
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* @brief Attach an interrupt to a DMA transfer.
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*
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* Interrupts are enabled using appropriate mode flags in
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* dma_setup_transfer().
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*
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* @param dev DMA device
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* @param stream Stream to attach handler to
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* @param handler Interrupt handler to call when channel interrupt fires.
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* @see dma_setup_transfer()
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* @see dma_detach_interrupt()
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*/
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void dma_attach_interrupt(dma_dev *dev,
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dma_stream stream,
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void (*handler)(void)) {
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dev->handlers[stream].handler = handler;
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nvic_irq_enable(dev->handlers[stream].irq_line);
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}
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/**
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* @brief Detach a DMA transfer interrupt handler.
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*
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* After calling this function, the given channel's interrupts will be
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* disabled.
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*
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* @param dev DMA device
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* @param stream Stream whose handler to detach
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* @sideeffect Clears interrupt enable bits in the channel's CCR register.
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* @see dma_attach_interrupt()
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*/
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void dma_detach_interrupt(dma_dev *dev, dma_stream stream) {
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nvic_irq_disable(dev->handlers[stream].irq_line);
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dev->handlers[stream].handler = NULL;
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}
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const uint8 dma_isr_bits_shift[] = { 0, 6, 16, 22};
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uint8 dma_get_isr_bit(dma_dev *dev, dma_stream stream, uint8_t mask) {
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if ( stream&0xFC ) return ((dev->regs->HISR)>>dma_isr_bits_shift[stream&0x03]) & mask;
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else return ((dev->regs->LISR)>>dma_isr_bits_shift[stream&0x03]) & mask;
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}
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void dma_clear_isr_bit(dma_dev *dev, dma_stream stream, uint8_t mask) {
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if ( stream&0xFC ) dev->regs->HIFCR = (uint32)mask << dma_isr_bits_shift[stream&0x03];
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else dev->regs->LIFCR = (uint32)mask << dma_isr_bits_shift[stream&0x03];
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}
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/*
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* IRQ handlers
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*/
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static inline void dispatch_handler(dma_dev *dev, dma_stream stream) {
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void (*handler)(void) = dev->handlers[stream].handler;
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if (handler) {
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handler();
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dma_clear_isr_bits(dev, stream); /* in case handler doesn't */
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}
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}
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//void __irq_dma1_stream0(void) {
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void __irq_dma1_channel1(void) {
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dispatch_handler(DMA1, DMA_STREAM0);
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}
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//void __irq_dma1_stream1(void) {
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void __irq_dma1_channel2(void) {
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dispatch_handler(DMA1, DMA_STREAM1);
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}
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//void __irq_dma1_stream2(void) {
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void __irq_dma1_channel3(void) {
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dispatch_handler(DMA1, DMA_STREAM2);
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}
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//void __irq_dma1_stream3(void) {
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void __irq_dma1_channel4(void) {
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dispatch_handler(DMA1, DMA_STREAM3);
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}
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//void __irq_dma1_stream4(void) {
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void __irq_dma1_channel5(void) {
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dispatch_handler(DMA1, DMA_STREAM4);
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}
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//void __irq_dma1_stream5(void) {
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void __irq_dma1_channel6(void) {
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dispatch_handler(DMA1, DMA_STREAM5);
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}
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//void __irq_dma1_stream6(void) {
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void __irq_dma1_channel7(void) {
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dispatch_handler(DMA1, DMA_STREAM6);
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}
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//void __irq_dma1_stream7(void) {
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void __irq_adc3(void) {
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dispatch_handler(DMA1, DMA_STREAM7);
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}
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//void __irq_dma2_stream0(void) {
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void __irq_dma2_channel1(void) {
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dispatch_handler(DMA2, DMA_STREAM0);
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}
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//void __irq_dma2_stream1(void) {
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void __irq_dma2_channel2(void) {
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dispatch_handler(DMA2, DMA_STREAM1);
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}
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//void __irq_dma2_stream2(void) {
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void __irq_dma2_channel3(void) {
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dispatch_handler(DMA2, DMA_STREAM2);
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}
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//void __irq_dma2_stream3(void) {
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void __irq_dma2_channel4_5(void) {
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dispatch_handler(DMA2, DMA_STREAM3);
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}
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//void __irq_dma2_stream4(void) {
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void __irq_DMA2_Stream4_IRQHandler(void) {
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dispatch_handler(DMA2, DMA_STREAM4);
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}
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//void __irq_dma2_stream5(void) {
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void __irq_DMA2_Stream5_IRQHandler(void) {
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dispatch_handler(DMA2, DMA_STREAM5);
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}
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//void __irq_dma2_stream6(void) {
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void __irq_DMA2_Stream6_IRQHandler(void) {
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dispatch_handler(DMA2, DMA_STREAM6);
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}
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//void __irq_dma2_stream7(void) {
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void __irq_DMA2_Stream7_IRQHandler(void) {
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dispatch_handler(DMA2, DMA_STREAM7);
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}
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#endif
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