414 lines
13 KiB
C
414 lines
13 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Michael Hope.
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* Copyright (c) 2012 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/stm32f1/dma.c
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* @author Marti Bolivar <mbolivar@leaflabs.com>;
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* Original implementation by Michael Hope
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* @brief STM32F1 DMA support.
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*/
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#include <libmaple/dma.h>
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#include <libmaple/bitband.h>
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/* Hack to ensure inlining in dma_irq_handler() */
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#define DMA_GET_HANDLER(dev, tube) (dev->handlers[tube - 1].handler)
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#include "dma_private.h"
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/*
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* Devices
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*/
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static dma_dev dma1 = {
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.regs = DMA1_BASE,
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.clk_id = RCC_DMA1,
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.handlers = {{ .handler = NULL, .irq_line = NVIC_DMA_CH1 },
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{ .handler = NULL, .irq_line = NVIC_DMA_CH2 },
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{ .handler = NULL, .irq_line = NVIC_DMA_CH3 },
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{ .handler = NULL, .irq_line = NVIC_DMA_CH4 },
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{ .handler = NULL, .irq_line = NVIC_DMA_CH5 },
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{ .handler = NULL, .irq_line = NVIC_DMA_CH6 },
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{ .handler = NULL, .irq_line = NVIC_DMA_CH7 }},
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};
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/** STM32F1 DMA1 device */
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dma_dev *DMA1 = &dma1;
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#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
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static dma_dev dma2 = {
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.regs = DMA2_BASE,
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.clk_id = RCC_DMA2,
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.handlers = {{ .handler = NULL, .irq_line = NVIC_DMA2_CH1 },
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{ .handler = NULL, .irq_line = NVIC_DMA2_CH2 },
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{ .handler = NULL, .irq_line = NVIC_DMA2_CH3 },
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{ .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 },
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{ .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }}, /* !@#$ */
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};
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/** STM32F1 DMA2 device */
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dma_dev *DMA2 = &dma2;
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#endif
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/*
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* Auxiliary routines
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*/
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/* Can channel serve cfg->tube_req_src? */
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static int cfg_req_ok(dma_channel channel, dma_tube_config *cfg) {
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return (cfg->tube_req_src & 0x7) == channel;
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}
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/* Can dev serve cfg->tube_req_src? */
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static int cfg_dev_ok(dma_dev *dev, dma_tube_config *cfg) {
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return (rcc_clk_id)(cfg->tube_req_src >> 3) == dev->clk_id;
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}
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/* Is addr acceptable for use as DMA src/dst? */
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static int cfg_mem_ok(__io void *addr) {
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enum dma_atype atype = _dma_addr_type(addr);
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return atype == DMA_ATYPE_MEM || atype == DMA_ATYPE_PER;
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}
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/* Is the direction implied by src->dst supported? */
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static int cfg_dir_ok(dma_tube_config *cfg) {
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/* We can't do peripheral->peripheral transfers. */
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return ((_dma_addr_type(cfg->tube_src) == DMA_ATYPE_MEM) ||
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(_dma_addr_type(cfg->tube_dst) == DMA_ATYPE_MEM));
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}
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static int preconfig_check(dma_dev *dev, dma_channel channel,
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dma_tube_config *cfg) {
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if (!cfg_req_ok(channel, cfg)) {
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return -DMA_TUBE_CFG_EREQ;
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}
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if (cfg->tube_nr_xfers > 65535) {
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return -DMA_TUBE_CFG_ENDATA;
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}
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if (!cfg_dev_ok(dev, cfg)) {
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return -DMA_TUBE_CFG_EDEV;
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}
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if (!cfg_mem_ok(cfg->tube_src)) {
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return -DMA_TUBE_CFG_ESRC;
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}
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if (!cfg_mem_ok(cfg->tube_dst)) {
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return -DMA_TUBE_CFG_EDST;
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}
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if (!cfg_dir_ok(cfg)) {
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return -DMA_TUBE_CFG_EDIR;
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}
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return DMA_TUBE_CFG_SUCCESS;
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}
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static inline void set_ccr(dma_tube_reg_map *chregs,
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dma_xfer_size msize, int minc,
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dma_xfer_size psize, int pinc,
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uint32 other_flags) {
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chregs->CCR = ((msize << 10) | (psize << 8) |
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(minc ? DMA_CCR_MINC : 0) | (pinc ? DMA_CCR_PINC : 0) |
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other_flags);
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}
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static inline uint32 cfg_ccr_flags(unsigned tube_flags) {
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/* DMA_CFG_SRC_INC and DMA_CFG_DST_INC are special */
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return tube_flags & ~(DMA_CFG_SRC_INC | DMA_CFG_DST_INC);
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}
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/* Configure chregs according to cfg, where cfg->tube_dst is peripheral. */
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static int config_to_per(dma_tube_reg_map *chregs, dma_tube_config *cfg) {
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/* Check that ->tube_src is memory (if it's anything else, we
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* shouldn't have been called). */
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ASSERT(_dma_addr_type(cfg->tube_src) == DMA_ATYPE_MEM);
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set_ccr(chregs,
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cfg->tube_src_size, cfg->tube_flags & DMA_CFG_SRC_INC,
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cfg->tube_dst_size, cfg->tube_flags & DMA_CFG_DST_INC,
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(cfg_ccr_flags(cfg->tube_flags) | DMA_CCR_DIR_FROM_MEM));
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chregs->CNDTR = cfg->tube_nr_xfers;
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chregs->CMAR = (uint32)cfg->tube_src;
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chregs->CPAR = (uint32)cfg->tube_dst;
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return DMA_TUBE_CFG_SUCCESS;
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}
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/* Configure chregs according to cfg, where cfg->tube_dst is memory. */
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static int config_to_mem(dma_tube_reg_map *chregs, dma_tube_config *cfg) {
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uint32 mem2mem;
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if ((_dma_addr_type(cfg->tube_src) == DMA_ATYPE_MEM) &&
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(cfg->tube_flags & DMA_CFG_CIRC)) {
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/* Can't do mem-to-mem and circular mode */
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return -DMA_TUBE_CFG_ECFG;
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}
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mem2mem = (_dma_addr_type(cfg->tube_src) == DMA_ATYPE_MEM ?
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DMA_CCR_MEM2MEM : 0);
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set_ccr(chregs,
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cfg->tube_dst_size, cfg->tube_flags & DMA_CFG_DST_INC,
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cfg->tube_src_size, cfg->tube_flags & DMA_CFG_SRC_INC,
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(cfg_ccr_flags(cfg->tube_flags) |
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DMA_CCR_DIR_FROM_PER |
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mem2mem));
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chregs->CNDTR = cfg->tube_nr_xfers;
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chregs->CMAR = (uint32)cfg->tube_dst;
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chregs->CPAR = (uint32)cfg->tube_src;
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return DMA_TUBE_CFG_SUCCESS;
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}
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/*
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* Routines
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*/
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int dma_tube_cfg(dma_dev *dev, dma_channel channel, dma_tube_config *cfg) {
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dma_tube_reg_map *chregs;
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int ret = preconfig_check(dev, channel, cfg);
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if (ret < 0) {
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return ret;
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}
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dma_disable(dev, channel); /* Must disable before reconfiguring */
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dma_clear_isr_bits(dev, channel); /* For sanity and consistency
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* with STM32F2. */
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chregs = dma_tube_regs(dev, channel);
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switch (_dma_addr_type(cfg->tube_dst)) {
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case DMA_ATYPE_PER:
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ret = config_to_per(chregs, cfg);
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break;
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case DMA_ATYPE_MEM:
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ret = config_to_mem(chregs, cfg);
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break;
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default:
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/* Can't happen */
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ASSERT(0);
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return -DMA_TUBE_CFG_ECFG;
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}
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if (ret < 0) {
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return ret;
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}
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chregs->CNDTR = cfg->tube_nr_xfers;
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return DMA_TUBE_CFG_SUCCESS;
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}
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void dma_set_priority(dma_dev *dev,
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dma_channel channel,
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dma_priority priority) {
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dma_channel_reg_map *channel_regs;
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uint32 ccr;
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ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
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channel_regs = dma_channel_regs(dev, channel);
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ccr = channel_regs->CCR;
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ccr &= ~DMA_CCR_PL;
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ccr |= (priority << 12);
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channel_regs->CCR = ccr;
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}
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void dma_set_num_transfers(dma_dev *dev,
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dma_channel channel,
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uint16 num_transfers) {
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dma_channel_reg_map *channel_regs;
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ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
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channel_regs = dma_channel_regs(dev, channel);
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channel_regs->CNDTR = num_transfers;
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}
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void dma_attach_interrupt(dma_dev *dev, dma_channel channel,
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void (*handler)(void)) {
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DMA_GET_HANDLER(dev, channel) = handler;
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nvic_irq_enable(dev->handlers[channel - 1].irq_line);
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}
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void dma_detach_interrupt(dma_dev *dev, dma_channel channel) {
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/* Don't use nvic_irq_disable()! Think about DMA2 channels 4 and 5. */
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dma_channel_regs(dev, channel)->CCR &= ~0xF;
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DMA_GET_HANDLER(dev, channel) = NULL;
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}
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void dma_enable(dma_dev *dev, dma_channel channel) {
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dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel);
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bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 1);
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}
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void dma_disable(dma_dev *dev, dma_channel channel) {
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dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel);
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bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 0);
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}
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dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel) {
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/* Grab and clear the ISR bits. */
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uint8 status_bits = dma_get_isr_bits(dev, channel);
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dma_clear_isr_bits(dev, channel);
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/* If the channel global interrupt flag is cleared, then
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* something's very wrong. */
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ASSERT(status_bits & 0x1);
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/* If GIF is set, then some other flag should be set, barring
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* something unexpected (e.g. the user making an unforeseen IFCR
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* write). */
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ASSERT(status_bits != 0x1);
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/* ISR flags get set even if the corresponding interrupt enable
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* bits in the channel's configuration register are cleared, so we
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* can't use a switch here.
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*
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* Don't change the order of these if statements. */
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if (status_bits & 0x8) {
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return DMA_TRANSFER_ERROR;
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} else if (status_bits & 0x2) {
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return DMA_TRANSFER_COMPLETE;
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} else if (status_bits & 0x4) {
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return DMA_TRANSFER_HALF_COMPLETE;
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}
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/* If we get here, one of our assumptions has been violated, but
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* the debug level is too low for the above ASSERTs() to have had
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* any effect. In order to fail fast, mimic the DMA controller's
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* behavior when an error occurs. */
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dma_disable(dev, channel);
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return DMA_TRANSFER_ERROR;
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}
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void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
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dma_channel_reg_map *chan_regs;
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ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
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chan_regs = dma_channel_regs(dev, channel);
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chan_regs->CMAR = (uint32)addr;
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}
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void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
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dma_channel_reg_map *chan_regs;
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ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
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chan_regs = dma_channel_regs(dev, channel);
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chan_regs->CPAR = (uint32)addr;
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}
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/**
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* @brief Deprecated. Use dma_tube_cfg() instead.
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*
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* Set up a DMA transfer.
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*
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* The channel will be disabled before being reconfigured. The
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* transfer will have low priority by default. You may choose another
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* priority before the transfer begins using dma_set_priority(), as
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* well as performing any other configuration you desire. When the
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* channel is configured to your liking, enable it using dma_enable().
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*
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* @param dev DMA device.
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* @param channel DMA channel.
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* @param peripheral_address Base address of peripheral data register
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* involved in the transfer.
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* @param peripheral_size Peripheral data transfer size.
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* @param memory_address Base memory address involved in the transfer.
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* @param memory_size Memory data transfer size.
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* @param mode Logical OR of dma_mode_flags
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*
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* @see dma_tube_cfg()
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*
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* @sideeffect Disables the given DMA channel.
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* @see dma_xfer_size
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* @see dma_mode_flags
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* @see dma_set_num_transfers()
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* @see dma_set_priority()
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* @see dma_attach_interrupt()
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* @see dma_enable()
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*/
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__deprecated
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void dma_setup_transfer(dma_dev *dev,
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dma_channel channel,
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__io void *peripheral_address,
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dma_xfer_size peripheral_size,
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__io void *memory_address,
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dma_xfer_size memory_size,
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uint32 mode) {
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dma_channel_reg_map *channel_regs = dma_channel_regs(dev, channel);
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dma_disable(dev, channel); /* can't write to CMAR/CPAR otherwise */
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channel_regs->CCR = (memory_size << 10) | (peripheral_size << 8) | mode;
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channel_regs->CMAR = (uint32)memory_address;
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channel_regs->CPAR = (uint32)peripheral_address;
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}
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/*
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* IRQ handlers
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*/
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void __irq_dma1_channel1(void) {
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dma_irq_handler(DMA1, DMA_CH1);
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}
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void __irq_dma1_channel2(void) {
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dma_irq_handler(DMA1, DMA_CH2);
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}
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void __irq_dma1_channel3(void) {
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dma_irq_handler(DMA1, DMA_CH3);
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}
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void __irq_dma1_channel4(void) {
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dma_irq_handler(DMA1, DMA_CH4);
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}
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void __irq_dma1_channel5(void) {
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dma_irq_handler(DMA1, DMA_CH5);
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}
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void __irq_dma1_channel6(void) {
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dma_irq_handler(DMA1, DMA_CH6);
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}
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void __irq_dma1_channel7(void) {
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dma_irq_handler(DMA1, DMA_CH7);
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}
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#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
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void __irq_dma2_channel1(void) {
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dma_irq_handler(DMA2, DMA_CH1);
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}
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void __irq_dma2_channel2(void) {
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dma_irq_handler(DMA2, DMA_CH2);
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}
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void __irq_dma2_channel3(void) {
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dma_irq_handler(DMA2, DMA_CH3);
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}
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void __irq_dma2_channel4_5(void) {
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if ((DMA2_BASE->CCR4 & DMA_CCR_EN) && (DMA2_BASE->ISR & DMA_ISR_GIF4)) {
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dma_irq_handler(DMA2, DMA_CH4);
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}
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if ((DMA2_BASE->CCR5 & DMA_CCR_EN) && (DMA2_BASE->ISR & DMA_ISR_GIF5)) {
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dma_irq_handler(DMA2, DMA_CH5);
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}
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}
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#endif
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