173 lines
6.7 KiB
C
173 lines
6.7 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Perry Hung.
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* Copyright (c) 2011 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/stm32f1/rcc.c
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* @brief STM32F1 RCC.
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*/
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#include <libmaple/rcc.h>
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#include <libmaple/libmaple.h>
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#include <libmaple/bitband.h>
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#include "rcc_private.h"
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#define APB1 RCC_APB1
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#define APB2 RCC_APB2
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#define AHB RCC_AHB
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/* Device descriptor table, maps rcc_clk_id onto bus and enable/reset
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* register bit numbers. */
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const struct rcc_dev_info rcc_dev_table[] = {
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[RCC_GPIOA] = { .clk_domain = APB2, .line_num = 2 },
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[RCC_GPIOB] = { .clk_domain = APB2, .line_num = 3 },
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[RCC_GPIOC] = { .clk_domain = APB2, .line_num = 4 },
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[RCC_GPIOD] = { .clk_domain = APB2, .line_num = 5 },
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[RCC_AFIO] = { .clk_domain = APB2, .line_num = 0 },
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[RCC_ADC1] = { .clk_domain = APB2, .line_num = 9 },
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[RCC_ADC2] = { .clk_domain = APB2, .line_num = 10 },
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[RCC_ADC3] = { .clk_domain = APB2, .line_num = 15 },
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[RCC_USART1] = { .clk_domain = APB2, .line_num = 14 },
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[RCC_USART2] = { .clk_domain = APB1, .line_num = 17 },
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[RCC_USART3] = { .clk_domain = APB1, .line_num = 18 },
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[RCC_TIMER1] = { .clk_domain = APB2, .line_num = 11 },
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[RCC_TIMER2] = { .clk_domain = APB1, .line_num = 0 },
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[RCC_TIMER3] = { .clk_domain = APB1, .line_num = 1 },
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[RCC_TIMER4] = { .clk_domain = APB1, .line_num = 2 },
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[RCC_SPI1] = { .clk_domain = APB2, .line_num = 12 },
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[RCC_SPI2] = { .clk_domain = APB1, .line_num = 14 },
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[RCC_DMA1] = { .clk_domain = AHB, .line_num = 0 },
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[RCC_PWR] = { .clk_domain = APB1, .line_num = 28},
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[RCC_BKP] = { .clk_domain = APB1, .line_num = 27},
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[RCC_I2C1] = { .clk_domain = APB1, .line_num = 21 },
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[RCC_I2C2] = { .clk_domain = APB1, .line_num = 22 },
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[RCC_CRC] = { .clk_domain = AHB, .line_num = 6},
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[RCC_FLITF] = { .clk_domain = AHB, .line_num = 4},
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[RCC_SRAM] = { .clk_domain = AHB, .line_num = 2},
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[RCC_USB] = { .clk_domain = APB1, .line_num = 23},
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#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
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[RCC_GPIOE] = { .clk_domain = APB2, .line_num = 6 },
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[RCC_GPIOF] = { .clk_domain = APB2, .line_num = 7 },
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[RCC_GPIOG] = { .clk_domain = APB2, .line_num = 8 },
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[RCC_UART4] = { .clk_domain = APB1, .line_num = 19 },
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[RCC_UART5] = { .clk_domain = APB1, .line_num = 20 },
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[RCC_TIMER5] = { .clk_domain = APB1, .line_num = 3 },
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[RCC_TIMER6] = { .clk_domain = APB1, .line_num = 4 },
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[RCC_TIMER7] = { .clk_domain = APB1, .line_num = 5 },
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[RCC_TIMER8] = { .clk_domain = APB2, .line_num = 13 },
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[RCC_FSMC] = { .clk_domain = AHB, .line_num = 8 },
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[RCC_DAC] = { .clk_domain = APB1, .line_num = 29 },
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[RCC_DMA2] = { .clk_domain = AHB, .line_num = 1 },
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[RCC_SDIO] = { .clk_domain = AHB, .line_num = 10 },
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[RCC_SPI3] = { .clk_domain = APB1, .line_num = 15 },
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#endif
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#ifdef STM32_XL_DENSITY
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[RCC_TIMER9] = { .clk_domain = APB2, .line_num = 19 },
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[RCC_TIMER10] = { .clk_domain = APB2, .line_num = 20 },
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[RCC_TIMER11] = { .clk_domain = APB2, .line_num = 21 },
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[RCC_TIMER12] = { .clk_domain = APB1, .line_num = 6 },
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[RCC_TIMER13] = { .clk_domain = APB1, .line_num = 7 },
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[RCC_TIMER14] = { .clk_domain = APB1, .line_num = 8 },
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#endif
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};
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__deprecated
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void rcc_clk_init(rcc_sysclk_src sysclk_src,
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rcc_pllsrc pll_src,
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rcc_pll_multiplier pll_mul) {
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/* Assume that we're going to clock the chip off the PLL, fed by
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* the HSE */
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ASSERT(sysclk_src == RCC_CLKSRC_PLL &&
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pll_src == RCC_PLLSRC_HSE);
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RCC_BASE->CFGR = pll_src | pll_mul | (0x3<<22);
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/* Turn on, and wait for, HSE. */
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rcc_turn_on_clk(RCC_CLK_HSE);
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while (!rcc_is_clk_ready(RCC_CLK_HSE))
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;
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/* Do the same for the main PLL. */
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rcc_turn_on_clk(RCC_CLK_PLL);
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while(!rcc_is_clk_ready(RCC_CLK_PLL))
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;
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/* Finally, switch over to the PLL. */
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rcc_switch_sysclk(RCC_CLKSRC_PLL);
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}
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/* pll_cfg->data must point to a valid struct stm32f1_rcc_pll_data. */
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void rcc_configure_pll(rcc_pll_cfg *pll_cfg) {
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stm32f1_rcc_pll_data *data = pll_cfg->data;
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rcc_pll_multiplier pll_mul = data->pll_mul;
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uint32 cfgr;
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/* Check that the PLL is disabled. */
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ASSERT_FAULT(!rcc_is_clk_on(RCC_CLK_PLL));
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cfgr = RCC_BASE->CFGR;
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cfgr &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL);
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cfgr |= pll_cfg->pllsrc | pll_mul;
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RCC_BASE->CFGR = cfgr;
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}
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void rcc_clk_enable(rcc_clk_id id) {
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static __io uint32* enable_regs[] = {
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[APB1] = &RCC_BASE->APB1ENR,
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[APB2] = &RCC_BASE->APB2ENR,
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[AHB] = &RCC_BASE->AHBENR,
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};
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rcc_do_clk_enable(enable_regs, id);
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}
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void rcc_reset_dev(rcc_clk_id id) {
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static __io uint32* reset_regs[] = {
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[APB1] = &RCC_BASE->APB1RSTR,
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[APB2] = &RCC_BASE->APB2RSTR,
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};
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rcc_do_reset_dev(reset_regs, id);
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}
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void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
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static const uint32 masks[] = {
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[RCC_PRESCALER_AHB] = RCC_CFGR_HPRE,
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[RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1,
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[RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2,
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[RCC_PRESCALER_USB] = RCC_CFGR_USBPRE,
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[RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE,
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};
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rcc_do_set_prescaler(masks, prescaler, divider);
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}
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void rcc_clk_disable(rcc_clk_id id) {
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static __io uint32* enable_regs[] = {
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[APB1] = &RCC_BASE->APB1ENR,
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[APB2] = &RCC_BASE->APB2ENR,
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[AHB] = &RCC_BASE->AHBENR,
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};
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rcc_do_clk_disable(enable_regs, id);
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} |