diff --git a/STM32/boards.txt b/STM32/boards.txt
index 2ac05cc..f9ba169 100644
--- a/STM32/boards.txt
+++ b/STM32/boards.txt
@@ -1,7 +1,7 @@
 # See: http://code.google.com/p/arduino/wiki/Platforms
 
 menu.serial=Serial communication
-menu.nucleo_board=Nucleo board
+menu.subboard=Specific Board
 menu.upload_method=Upload method
 menu.usb=USB
 
@@ -134,45 +134,61 @@ BluePill.menu.serial.SerialUART1=SerialUART1
 BluePill.menu.serial.SerialUART1.build.extra_flags_serial=-DMENU_SERIAL=SerialUART1
 
 ################################################################################
-# BLACK_F407VE board
+# BLACK_F407XX board
 
-BLACK_F407VE.name=BLACK F407VE
+BLACK_F407XX.name=BLACK F407VE/ZE/ZG boards
 
-BLACK_F407VE.vid.0=0x0483
-BLACK_F407VE.pid.0=0x5711
+BLACK_F407XX.vid.0=0x0483
+BLACK_F407XX.pid.0=0x5711
 
-BLACK_F407VE.upload.maximum_size=524288
-BLACK_F407VE.upload.maximum_data_size=131072
+BLACK_F407XX.upload.maximum_size=524288
+BLACK_F407XX.upload.maximum_data_size=131072
 
-BLACK_F407VE.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
-BLACK_F407VE.build.core=arduino
-BLACK_F407VE.build.variant=BLACK_F407VE
-BLACK_F407VE.build.board=BLACK_F407VE
-BLACK_F407VE.build.series=STM32F4
-BLACK_F407VE.build.extra_flags=-DSTM32F407VE -DHSE_VALUE=8000000
+BLACK_F407XX.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
+BLACK_F407XX.build.core=arduino
+BLACK_F407XX.build.board=BLACK_F407XX
+BLACK_F407XX.build.series=STM32F4
 
-BLACK_F407VE.upload.tool=stlink_upload
-BLACK_F407VE.upload.protocol=STLink
+BLACK_F407XX.upload.tool=stlink_upload
+BLACK_F407XX.upload.protocol=STLink
 
-BLACK_F407VE.menu.upload_method.STLinkMethod=STLink [Automatic serial = SerialUSB]
-BLACK_F407VE.menu.upload_method.STLinkMethod.upload.protocol=STLink
-BLACK_F407VE.menu.upload_method.STLinkMethod.upload.tool=stlink_upload
-BLACK_F407VE.menu.upload_method.STLinkMethod.build.extra_flags_serial_auto=-DMENU_SERIAL_AUTO=SerialUSB
+BLACK_F407XX.menu.upload_method.STLinkMethod=STLink [Automatic serial = SerialUSB]
+BLACK_F407XX.menu.upload_method.STLinkMethod.upload.protocol=STLink
+BLACK_F407XX.menu.upload_method.STLinkMethod.upload.tool=stlink_upload
+BLACK_F407XX.menu.upload_method.STLinkMethod.build.extra_flags_serial_auto=-DMENU_SERIAL_AUTO=SerialUSB
 
-BLACK_F407VE.menu.upload_method.serialMethod=Serial UART1 [TX/PA9, RX/PA10, BOOT0=1, BOOT1=0]
-BLACK_F407VE.menu.upload_method.serialMethod.upload.protocol=maple_serial
-BLACK_F407VE.menu.upload_method.serialMethod.upload.tool=serial_upload
-BLACK_F407VE.menu.upload_method.serialMethod.build.extra_flags_serial_auto=-DMENU_SERIAL_AUTO=SerialUART1
+BLACK_F407XX.menu.upload_method.serialMethod=Serial UART1 [TX/PA9, RX/PA10, BOOT0=1, BOOT1=0]
+BLACK_F407XX.menu.upload_method.serialMethod.upload.protocol=maple_serial
+BLACK_F407XX.menu.upload_method.serialMethod.upload.tool=serial_upload
+BLACK_F407XX.menu.upload_method.serialMethod.build.extra_flags_serial_auto=-DMENU_SERIAL_AUTO=SerialUART1
 
-BLACK_F407VE.menu.usb.SerialUSB=Serial [Virtual COM port, PA11/PA12 pins]
-BLACK_F407VE.menu.usb.SerialUSB.build.extra_flags_usb=-DMENU_USB_SERIAL
-BLACK_F407VE.menu.usb.Disabled=Disabled, no USB
+BLACK_F407XX.menu.usb.SerialUSB=Serial [Virtual COM port, PA11/PA12 pins]
+BLACK_F407XX.menu.usb.SerialUSB.build.extra_flags_usb=-DMENU_USB_SERIAL
+BLACK_F407XX.menu.usb.Disabled=Disabled, no USB
 
-BLACK_F407VE.menu.serial.Automatic=Automatically selected based on upload method
-BLACK_F407VE.menu.serial.SerialUSB=SerialUSB
-BLACK_F407VE.menu.serial.SerialUSB.build.extra_flags_serial=-DMENU_SERIAL=SerialUSB
-BLACK_F407VE.menu.serial.SerialUART1=SerialUART1
-BLACK_F407VE.menu.serial.SerialUART1.build.extra_flags_serial=-DMENU_SERIAL=SerialUART1
+BLACK_F407XX.menu.serial.Automatic=Automatically selected based on upload method
+BLACK_F407XX.menu.serial.SerialUSB=SerialUSB
+BLACK_F407XX.menu.serial.SerialUSB.build.extra_flags_serial=-DMENU_SERIAL=SerialUSB
+BLACK_F407XX.menu.serial.SerialUART1=SerialUART1
+BLACK_F407XX.menu.serial.SerialUART1.build.extra_flags_serial=-DMENU_SERIAL=SerialUART1
+
+BLACK_F407XX.menu.subboard.BLACK_F407VE=BLACK F407VE (V2.0)
+BLACK_F407XX.menu.subboard.BLACK_F407VE.upload.maximum_size=524288
+BLACK_F407XX.menu.subboard.BLACK_F407VE.upload.maximum_data_size=131072
+BLACK_F407XX.menu.subboard.BLACK_F407VE.build.variant=BLACK_F407VE
+BLACK_F407XX.menu.subboard.BLACK_F407VE.build.extra_flags=-DSTM32F407VE -DHSE_VALUE=8000000
+
+BLACK_F407XX.menu.subboard.BLACK_F407ZE=BLACK F407ZE (V3.0)
+BLACK_F407XX.menu.subboard.BLACK_F407ZE.upload.maximum_size=1232896
+BLACK_F407XX.menu.subboard.BLACK_F407ZE.upload.maximum_data_size=131072
+BLACK_F407XX.menu.subboard.BLACK_F407ZE.build.variant=BLACK_F407VE
+BLACK_F407XX.menu.subboard.BLACK_F407ZE.build.extra_flags=-DSTM32F407VE -DHSE_VALUE=8000000
+
+BLACK_F407XX.menu.subboard.BLACK_F407ZG=BLACK F407ZG (M4 DEMO)
+BLACK_F407XX.menu.subboard.BLACK_F407ZG.upload.maximum_size=1232896
+BLACK_F407XX.menu.subboard.BLACK_F407ZG.upload.maximum_data_size=131072
+BLACK_F407XX.menu.subboard.BLACK_F407ZG.build.variant=BLACK_F407ZG
+BLACK_F407XX.menu.subboard.BLACK_F407ZG.build.extra_flags=-DSTM32F407VE -DHSE_VALUE=8000000
 
 ################################################################################
 # NUCLEO 64 board
@@ -188,68 +204,68 @@ NUCLEO_64.build.board=NUCLEO_64
 
 NUCLEO_64.build.extra_flags_serial_auto=-DMENU_SERIAL_AUTO=SerialUART2
 
-NUCLEO_64.menu.nucleo_board.Nucleo_F030R8=Nucleo-F030R8
-NUCLEO_64.menu.nucleo_board.Nucleo_F030R8.upload.maximum_size=65536
-NUCLEO_64.menu.nucleo_board.Nucleo_F030R8.upload.maximum_data_size=8192
-NUCLEO_64.menu.nucleo_board.Nucleo_F030R8.build.mcu=cortex-m0
-NUCLEO_64.menu.nucleo_board.Nucleo_F030R8.build.series=STM32F0
-NUCLEO_64.menu.nucleo_board.Nucleo_F030R8.build.variant=NUCLEO_F030R8
-NUCLEO_64.menu.nucleo_board.Nucleo_F030R8.build.extra_flags=-DSTM32F030R8
-NUCLEO_64.menu.nucleo_board.Nucleo_F030R8.massstorage_drive=NODE_F030R8
+NUCLEO_64.menu.subboard.Nucleo_F030R8=Nucleo-F030R8
+NUCLEO_64.menu.subboard.Nucleo_F030R8.upload.maximum_size=65536
+NUCLEO_64.menu.subboard.Nucleo_F030R8.upload.maximum_data_size=8192
+NUCLEO_64.menu.subboard.Nucleo_F030R8.build.mcu=cortex-m0
+NUCLEO_64.menu.subboard.Nucleo_F030R8.build.series=STM32F0
+NUCLEO_64.menu.subboard.Nucleo_F030R8.build.variant=NUCLEO_F030R8
+NUCLEO_64.menu.subboard.Nucleo_F030R8.build.extra_flags=-DSTM32F030R8
+NUCLEO_64.menu.subboard.Nucleo_F030R8.massstorage_drive=NODE_F030R8
 
-NUCLEO_64.menu.nucleo_board.Nucleo_F103RB=Nucleo-F103RB
-NUCLEO_64.menu.nucleo_board.Nucleo_F103RB.upload.maximum_size=131072
-NUCLEO_64.menu.nucleo_board.Nucleo_F103RB.upload.maximum_data_size=20480
-NUCLEO_64.menu.nucleo_board.Nucleo_F103RB.build.mcu=cortex-m3
-NUCLEO_64.menu.nucleo_board.Nucleo_F103RB.build.series=STM32F1
-NUCLEO_64.menu.nucleo_board.Nucleo_F103RB.build.variant=NUCLEO_F103RB
-NUCLEO_64.menu.nucleo_board.Nucleo_F103RB.build.extra_flags=-DSTM32F103RB
-NUCLEO_64.menu.nucleo_board.Nucleo_F103RB.massstorage_drive=NODE_F103RB
+NUCLEO_64.menu.subboard.Nucleo_F103RB=Nucleo-F103RB
+NUCLEO_64.menu.subboard.Nucleo_F103RB.upload.maximum_size=131072
+NUCLEO_64.menu.subboard.Nucleo_F103RB.upload.maximum_data_size=20480
+NUCLEO_64.menu.subboard.Nucleo_F103RB.build.mcu=cortex-m3
+NUCLEO_64.menu.subboard.Nucleo_F103RB.build.series=STM32F1
+NUCLEO_64.menu.subboard.Nucleo_F103RB.build.variant=NUCLEO_F103RB
+NUCLEO_64.menu.subboard.Nucleo_F103RB.build.extra_flags=-DSTM32F103RB
+NUCLEO_64.menu.subboard.Nucleo_F103RB.massstorage_drive=NODE_F103RB
 
-NUCLEO_64.menu.nucleo_board.Nucleo_F303RE=Nucleo-F303RE
-NUCLEO_64.menu.nucleo_board.Nucleo_F303RE.upload.maximum_size=524288
-NUCLEO_64.menu.nucleo_board.Nucleo_F303RE.upload.maximum_data_size=81920
-NUCLEO_64.menu.nucleo_board.Nucleo_F303RE.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
-NUCLEO_64.menu.nucleo_board.Nucleo_F303RE.build.series=STM32F3
-NUCLEO_64.menu.nucleo_board.Nucleo_F303RE.build.variant=NUCLEO_F303RE
-NUCLEO_64.menu.nucleo_board.Nucleo_F303RE.build.extra_flags=-DSTM32F303RE
-NUCLEO_64.menu.nucleo_board.Nucleo_F303RE.massstorage_drive=NODE_F303RE
+NUCLEO_64.menu.subboard.Nucleo_F303RE=Nucleo-F303RE
+NUCLEO_64.menu.subboard.Nucleo_F303RE.upload.maximum_size=524288
+NUCLEO_64.menu.subboard.Nucleo_F303RE.upload.maximum_data_size=81920
+NUCLEO_64.menu.subboard.Nucleo_F303RE.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
+NUCLEO_64.menu.subboard.Nucleo_F303RE.build.series=STM32F3
+NUCLEO_64.menu.subboard.Nucleo_F303RE.build.variant=NUCLEO_F303RE
+NUCLEO_64.menu.subboard.Nucleo_F303RE.build.extra_flags=-DSTM32F303RE
+NUCLEO_64.menu.subboard.Nucleo_F303RE.massstorage_drive=NODE_F303RE
 
-NUCLEO_64.menu.nucleo_board.Nucleo_F411RE=Nucleo-F411RE
-NUCLEO_64.menu.nucleo_board.Nucleo_F411RE.upload.maximum_size=524288
-NUCLEO_64.menu.nucleo_board.Nucleo_F411RE.upload.maximum_data_size=131072
-NUCLEO_64.menu.nucleo_board.Nucleo_F411RE.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
-NUCLEO_64.menu.nucleo_board.Nucleo_F411RE.build.series=STM32F4
-NUCLEO_64.menu.nucleo_board.Nucleo_F411RE.build.variant=NUCLEO_F411RE
-NUCLEO_64.menu.nucleo_board.Nucleo_F411RE.build.extra_flags=-DSTM32F411RE
-NUCLEO_64.menu.nucleo_board.Nucleo_F411RE.massstorage_drive=NODE_F411RE
+NUCLEO_64.menu.subboard.Nucleo_F411RE=Nucleo-F411RE
+NUCLEO_64.menu.subboard.Nucleo_F411RE.upload.maximum_size=524288
+NUCLEO_64.menu.subboard.Nucleo_F411RE.upload.maximum_data_size=131072
+NUCLEO_64.menu.subboard.Nucleo_F411RE.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
+NUCLEO_64.menu.subboard.Nucleo_F411RE.build.series=STM32F4
+NUCLEO_64.menu.subboard.Nucleo_F411RE.build.variant=NUCLEO_F411RE
+NUCLEO_64.menu.subboard.Nucleo_F411RE.build.extra_flags=-DSTM32F411RE
+NUCLEO_64.menu.subboard.Nucleo_F411RE.massstorage_drive=NODE_F411RE
 
-NUCLEO_64.menu.nucleo_board.Nucleo_L053R8=Nucleo-L053R8
-NUCLEO_64.menu.nucleo_board.Nucleo_L053R8.upload.maximum_size=65536
-NUCLEO_64.menu.nucleo_board.Nucleo_L053R8.upload.maximum_data_size=8192
-NUCLEO_64.menu.nucleo_board.Nucleo_L053R8.build.mcu=cortex-m0
-NUCLEO_64.menu.nucleo_board.Nucleo_L053R8.build.series=STM32L0
-NUCLEO_64.menu.nucleo_board.Nucleo_L053R8.build.variant=NUCLEO_L053R8
-NUCLEO_64.menu.nucleo_board.Nucleo_L053R8.build.extra_flags=-DSTM32L053R8
-NUCLEO_64.menu.nucleo_board.Nucleo_L053R8.massstorage_drive=NODE_L053R8
+NUCLEO_64.menu.subboard.Nucleo_L053R8=Nucleo-L053R8
+NUCLEO_64.menu.subboard.Nucleo_L053R8.upload.maximum_size=65536
+NUCLEO_64.menu.subboard.Nucleo_L053R8.upload.maximum_data_size=8192
+NUCLEO_64.menu.subboard.Nucleo_L053R8.build.mcu=cortex-m0
+NUCLEO_64.menu.subboard.Nucleo_L053R8.build.series=STM32L0
+NUCLEO_64.menu.subboard.Nucleo_L053R8.build.variant=NUCLEO_L053R8
+NUCLEO_64.menu.subboard.Nucleo_L053R8.build.extra_flags=-DSTM32L053R8
+NUCLEO_64.menu.subboard.Nucleo_L053R8.massstorage_drive=NODE_L053R8
 
-NUCLEO_64.menu.nucleo_board.Nucleo_L152RE=Nucleo-L152RE
-NUCLEO_64.menu.nucleo_board.Nucleo_L152RE.upload.maximum_size=524288
-NUCLEO_64.menu.nucleo_board.Nucleo_L152RE.upload.maximum_data_size=81920
-NUCLEO_64.menu.nucleo_board.Nucleo_L152RE.build.mcu=cortex-m3
-NUCLEO_64.menu.nucleo_board.Nucleo_L152RE.build.series=STM32L1
-NUCLEO_64.menu.nucleo_board.Nucleo_L152RE.build.variant=NUCLEO_L152RE
-NUCLEO_64.menu.nucleo_board.Nucleo_L152RE.build.extra_flags=-DSTM32L152RE
-NUCLEO_64.menu.nucleo_board.Nucleo_L152RE.massstorage_drive=NODE_L152RE
+NUCLEO_64.menu.subboard.Nucleo_L152RE=Nucleo-L152RE
+NUCLEO_64.menu.subboard.Nucleo_L152RE.upload.maximum_size=524288
+NUCLEO_64.menu.subboard.Nucleo_L152RE.upload.maximum_data_size=81920
+NUCLEO_64.menu.subboard.Nucleo_L152RE.build.mcu=cortex-m3
+NUCLEO_64.menu.subboard.Nucleo_L152RE.build.series=STM32L1
+NUCLEO_64.menu.subboard.Nucleo_L152RE.build.variant=NUCLEO_L152RE
+NUCLEO_64.menu.subboard.Nucleo_L152RE.build.extra_flags=-DSTM32L152RE
+NUCLEO_64.menu.subboard.Nucleo_L152RE.massstorage_drive=NODE_L152RE
 
-NUCLEO_64.menu.nucleo_board.Nucleo_L476RG=Nucleo-L476RG
-NUCLEO_64.menu.nucleo_board.Nucleo_L476RG.upload.maximum_size=1024
-NUCLEO_64.menu.nucleo_board.Nucleo_L476RG.upload.maximum_data_size=131072
-NUCLEO_64.menu.nucleo_board.Nucleo_L476RG.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
-NUCLEO_64.menu.nucleo_board.Nucleo_L476RG.build.series=STM32L4
-NUCLEO_64.menu.nucleo_board.Nucleo_L476RG.build.variant=NUCLEO_L476RG
-NUCLEO_64.menu.nucleo_board.Nucleo_L476RG.build.extra_flags=-DSTM32L476RG
-NUCLEO_64.menu.nucleo_board.Nucleo_L476RG.massstorage_drive=NODE_L476RG
+NUCLEO_64.menu.subboard.Nucleo_L476RG=Nucleo-L476RG
+NUCLEO_64.menu.subboard.Nucleo_L476RG.upload.maximum_size=1024
+NUCLEO_64.menu.subboard.Nucleo_L476RG.upload.maximum_data_size=131072
+NUCLEO_64.menu.subboard.Nucleo_L476RG.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
+NUCLEO_64.menu.subboard.Nucleo_L476RG.build.series=STM32L4
+NUCLEO_64.menu.subboard.Nucleo_L476RG.build.variant=NUCLEO_L476RG
+NUCLEO_64.menu.subboard.Nucleo_L476RG.build.extra_flags=-DSTM32L476RG
+NUCLEO_64.menu.subboard.Nucleo_L476RG.massstorage_drive=NODE_L476RG
 
 
 NUCLEO_64.menu.upload_method.MassStorageMethod=Mass Storage
diff --git a/STM32/variants/BLACK_F407ZE/ldscript.ld b/STM32/variants/BLACK_F407ZE/ldscript.ld
new file mode 100644
index 0000000..944a26c
--- /dev/null
+++ b/STM32/variants/BLACK_F407ZE/ldscript.ld
@@ -0,0 +1,121 @@
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20000000 + 131072;    /* end of RAM */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata ALIGN(4) :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( _end = . );
+  
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/STM32/variants/BLACK_F407ZE/systemclock_config.c b/STM32/variants/BLACK_F407ZE/systemclock_config.c
new file mode 100644
index 0000000..89663f0
--- /dev/null
+++ b/STM32/variants/BLACK_F407ZE/systemclock_config.c
@@ -0,0 +1,51 @@
+#include "stm32_build_defines.h"
+#include "stm32_def.h"
+
+void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 4;
+  RCC_OscInitStruct.PLL.PLLN = 168;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S;
+  PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+  PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+  Error_Handler();
+  }
+  
+  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+
+  HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+
+  /* SysTick_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
+}
diff --git a/STM32/variants/BLACK_F407ZE/variant.cpp b/STM32/variants/BLACK_F407ZE/variant.cpp
new file mode 100644
index 0000000..c0cdc43
--- /dev/null
+++ b/STM32/variants/BLACK_F407ZE/variant.cpp
@@ -0,0 +1,121 @@
+#include <Arduino.h>
+
+#include "stm32_gpio.h"
+
+const stm32_port_pin_type variant_pin_list[] = {
+  { GPIOA, GPIO_PIN_0 },
+  { GPIOA, GPIO_PIN_1 },
+  { GPIOA, GPIO_PIN_2 },
+  { GPIOA, GPIO_PIN_3 },
+  { GPIOA, GPIO_PIN_4 },
+  { GPIOA, GPIO_PIN_5 },
+  { GPIOA, GPIO_PIN_6 },
+  { GPIOA, GPIO_PIN_7 },
+  { GPIOA, GPIO_PIN_8 },
+  { GPIOA, GPIO_PIN_9 },
+  { GPIOA, GPIO_PIN_10},
+  { GPIOA, GPIO_PIN_11},
+  { GPIOA, GPIO_PIN_12},
+  { GPIOA, GPIO_PIN_13},
+  { GPIOA, GPIO_PIN_14},
+  { GPIOA, GPIO_PIN_15},
+  { GPIOB, GPIO_PIN_0 },
+  { GPIOB, GPIO_PIN_1 },
+  { GPIOB, GPIO_PIN_2 },
+  { GPIOB, GPIO_PIN_3 },
+  { GPIOB, GPIO_PIN_4 },
+  { GPIOB, GPIO_PIN_5 },
+  { GPIOB, GPIO_PIN_6 },
+  { GPIOB, GPIO_PIN_7 },
+  { GPIOB, GPIO_PIN_8 },
+  { GPIOB, GPIO_PIN_9 },
+  { GPIOB, GPIO_PIN_10},
+  { GPIOB, GPIO_PIN_11},
+  { GPIOB, GPIO_PIN_12},
+  { GPIOB, GPIO_PIN_13},
+  { GPIOB, GPIO_PIN_14},
+  { GPIOB, GPIO_PIN_15},
+  { GPIOC, GPIO_PIN_0 },
+  { GPIOC, GPIO_PIN_1 },
+  { GPIOC, GPIO_PIN_2 },
+  { GPIOC, GPIO_PIN_3 },
+  { GPIOC, GPIO_PIN_4 },
+  { GPIOC, GPIO_PIN_5 },
+  { GPIOC, GPIO_PIN_6 },
+  { GPIOC, GPIO_PIN_7 },
+  { GPIOC, GPIO_PIN_8 },
+  { GPIOC, GPIO_PIN_9 },
+  { GPIOC, GPIO_PIN_10},
+  { GPIOC, GPIO_PIN_11},
+  { GPIOC, GPIO_PIN_12},
+  { GPIOC, GPIO_PIN_13},
+  { GPIOC, GPIO_PIN_14},
+  { GPIOC, GPIO_PIN_15},
+  { GPIOD, GPIO_PIN_0 },
+  { GPIOD, GPIO_PIN_1 },
+  { GPIOD, GPIO_PIN_2 },
+  { GPIOD, GPIO_PIN_3 },
+  { GPIOD, GPIO_PIN_4 },
+  { GPIOD, GPIO_PIN_5 },
+  { GPIOD, GPIO_PIN_6 },
+  { GPIOD, GPIO_PIN_7 },
+  { GPIOD, GPIO_PIN_8 },
+  { GPIOD, GPIO_PIN_9 },
+  { GPIOD, GPIO_PIN_10},
+  { GPIOD, GPIO_PIN_11},
+  { GPIOD, GPIO_PIN_12},
+  { GPIOD, GPIO_PIN_13},
+  { GPIOD, GPIO_PIN_14},
+  { GPIOD, GPIO_PIN_15},
+  { GPIOE, GPIO_PIN_0 },
+  { GPIOE, GPIO_PIN_1 },
+  { GPIOE, GPIO_PIN_2 },
+  { GPIOE, GPIO_PIN_3 },
+  { GPIOE, GPIO_PIN_4 },
+  { GPIOE, GPIO_PIN_5 },
+  { GPIOE, GPIO_PIN_6 },
+  { GPIOE, GPIO_PIN_7 },
+  { GPIOE, GPIO_PIN_8 },
+  { GPIOE, GPIO_PIN_9 },
+  { GPIOE, GPIO_PIN_10},
+  { GPIOE, GPIO_PIN_11},
+  { GPIOE, GPIO_PIN_12},
+  { GPIOE, GPIO_PIN_13},
+  { GPIOE, GPIO_PIN_14},
+  { GPIOE, GPIO_PIN_15},
+  { GPIOH, GPIO_PIN_0 },
+  { GPIOH, GPIO_PIN_1 },
+  { GPIOF, GPIO_PIN_0 },
+  { GPIOF, GPIO_PIN_1 },
+  { GPIOF, GPIO_PIN_2 },
+  { GPIOF, GPIO_PIN_3 },
+  { GPIOF, GPIO_PIN_4 },
+  { GPIOF, GPIO_PIN_5 },
+  { GPIOF, GPIO_PIN_6 },
+  { GPIOF, GPIO_PIN_7 },
+  { GPIOF, GPIO_PIN_8 },
+  { GPIOF, GPIO_PIN_9 },
+  { GPIOF, GPIO_PIN_10},
+  { GPIOF, GPIO_PIN_11},
+  { GPIOF, GPIO_PIN_12},
+  { GPIOF, GPIO_PIN_13},
+  { GPIOF, GPIO_PIN_14},
+  { GPIOF, GPIO_PIN_15},
+  { GPIOG, GPIO_PIN_0 },
+  { GPIOG, GPIO_PIN_1 },
+  { GPIOG, GPIO_PIN_2 },
+  { GPIOG, GPIO_PIN_3 },
+  { GPIOG, GPIO_PIN_4 },
+  { GPIOG, GPIO_PIN_5 },
+  { GPIOG, GPIO_PIN_6 },
+  { GPIOG, GPIO_PIN_7 },
+  { GPIOG, GPIO_PIN_8 },
+  { GPIOG, GPIO_PIN_9 },
+  { GPIOG, GPIO_PIN_10},
+  { GPIOG, GPIO_PIN_11},
+  { GPIOG, GPIO_PIN_12},
+  { GPIOG, GPIO_PIN_13},
+  { GPIOG, GPIO_PIN_14},
+  { GPIOG, GPIO_PIN_15}
+};
+
diff --git a/STM32/variants/BLACK_F407ZE/variant.h b/STM32/variants/BLACK_F407ZE/variant.h
new file mode 100644
index 0000000..576e9cc
--- /dev/null
+++ b/STM32/variants/BLACK_F407ZE/variant.h
@@ -0,0 +1,135 @@
+#ifndef VARIANT_H
+#define VARIANT_H
+
+#define LED_BUILTIN PF9
+#define LED_BUILTIN2 PF10
+
+#define STM32_LED_BUILTIN_ACTIVE_LOW
+
+#define MOSI PB5
+#define MISO PB4
+#define SCK PB3
+#define SS PA4
+
+#define SDA PB7
+#define SCL PB6
+
+enum {
+   PA0 ,
+   PA1 ,
+   PA2 ,
+   PA3 ,
+   PA4 ,
+   PA5 ,
+   PA6 ,
+   PA7 ,
+   PA8 ,
+   PA9 ,
+   PA10,
+   PA11,
+   PA12,
+   PA13,
+   PA14,
+   PA15,
+   PB0 ,
+   PB1 ,
+   PB2 ,
+   PB3 ,
+   PB4 ,
+   PB5 ,
+   PB6 ,
+   PB7 ,
+   PB8 ,
+   PB9 ,
+   PB10,
+   PB11,
+   PB12,
+   PB13,
+   PB14,
+   PB15,
+   PC0 ,
+   PC1 ,
+   PC2 ,
+   PC3 ,
+   PC4 ,
+   PC5 ,
+   PC6 ,
+   PC7 ,
+   PC8 ,
+   PC9 ,
+   PC10,
+   PC11,
+   PC12,
+   PC13,
+   PC14,
+   PC15,
+   PD0 ,
+   PD1 ,
+   PD2 ,
+   PD3 ,
+   PD4 ,
+   PD5 ,
+   PD6 ,
+   PD7 ,
+   PD8 ,
+   PD9 ,
+   PD10,
+   PD11,
+   PD12,
+   PD13,
+   PD14,
+   PD15,
+   PE0 ,
+   PE1 ,
+   PE2 ,
+   PE3 ,
+   PE4 ,
+   PE5 ,
+   PE6 ,
+   PE7 ,
+   PE8 ,
+   PE9 ,
+   PE10,
+   PE11,
+   PE12,
+   PE13,
+   PE14,
+   PE15,
+   PH0 ,
+   PH1 ,
+   PF0 ,
+   PF1 ,
+   PF2 ,
+   PF3 ,
+   PF4 ,
+   PF5 ,
+   PF6 ,
+   PF7 ,
+   PF8 ,
+   PF9 ,
+   PF10,
+   PF11,
+   PF12,
+   PF13,
+   PF14,
+   PF15,
+   PG0 ,
+   PG1 ,
+   PG2 ,
+   PG3 ,
+   PG4 ,
+   PG5 ,
+   PG6 ,
+   PG7 ,
+   PG8 ,
+   PG9 ,
+   PG10,
+   PG11,
+   PG12,
+   PG13,
+   PG14,
+   PG15,
+NUM_PINS
+};
+
+#endif
diff --git a/STM32/variants/BLACK_F407ZG/ldscript.ld b/STM32/variants/BLACK_F407ZG/ldscript.ld
new file mode 100644
index 0000000..944a26c
--- /dev/null
+++ b/STM32/variants/BLACK_F407ZG/ldscript.ld
@@ -0,0 +1,121 @@
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20000000 + 131072;    /* end of RAM */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata ALIGN(4) :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( _end = . );
+  
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/STM32/variants/BLACK_F407ZG/systemclock_config.c b/STM32/variants/BLACK_F407ZG/systemclock_config.c
new file mode 100644
index 0000000..89663f0
--- /dev/null
+++ b/STM32/variants/BLACK_F407ZG/systemclock_config.c
@@ -0,0 +1,51 @@
+#include "stm32_build_defines.h"
+#include "stm32_def.h"
+
+void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 4;
+  RCC_OscInitStruct.PLL.PLLN = 168;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S;
+  PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+  PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+  Error_Handler();
+  }
+  
+  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+
+  HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+
+  /* SysTick_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
+}
diff --git a/STM32/variants/BLACK_F407ZG/variant.cpp b/STM32/variants/BLACK_F407ZG/variant.cpp
new file mode 100644
index 0000000..017bcc6
--- /dev/null
+++ b/STM32/variants/BLACK_F407ZG/variant.cpp
@@ -0,0 +1,120 @@
+#include <Arduino.h>
+
+#include "stm32_gpio.h"
+
+const stm32_port_pin_type variant_pin_list[] = {
+  { GPIOA, GPIO_PIN_0 },
+  { GPIOA, GPIO_PIN_1 },
+  { GPIOA, GPIO_PIN_2 },
+  { GPIOA, GPIO_PIN_3 },
+  { GPIOA, GPIO_PIN_4 },
+  { GPIOA, GPIO_PIN_5 },
+  { GPIOA, GPIO_PIN_6 },
+  { GPIOA, GPIO_PIN_7 },
+  { GPIOA, GPIO_PIN_8 },
+  { GPIOA, GPIO_PIN_9 },
+  { GPIOA, GPIO_PIN_10},
+  { GPIOA, GPIO_PIN_11},
+  { GPIOA, GPIO_PIN_12},
+  { GPIOA, GPIO_PIN_13},
+  { GPIOA, GPIO_PIN_14},
+  { GPIOA, GPIO_PIN_15},
+  { GPIOB, GPIO_PIN_0 },
+  { GPIOB, GPIO_PIN_1 },
+  { GPIOB, GPIO_PIN_2 },
+  { GPIOB, GPIO_PIN_3 },
+  { GPIOB, GPIO_PIN_4 },
+  { GPIOB, GPIO_PIN_5 },
+  { GPIOB, GPIO_PIN_6 },
+  { GPIOB, GPIO_PIN_7 },
+  { GPIOB, GPIO_PIN_8 },
+  { GPIOB, GPIO_PIN_9 },
+  { GPIOB, GPIO_PIN_10},
+  { GPIOB, GPIO_PIN_11},
+  { GPIOB, GPIO_PIN_12},
+  { GPIOB, GPIO_PIN_13},
+  { GPIOB, GPIO_PIN_14},
+  { GPIOB, GPIO_PIN_15},
+  { GPIOC, GPIO_PIN_0 },
+  { GPIOC, GPIO_PIN_1 },
+  { GPIOC, GPIO_PIN_2 },
+  { GPIOC, GPIO_PIN_3 },
+  { GPIOC, GPIO_PIN_4 },
+  { GPIOC, GPIO_PIN_5 },
+  { GPIOC, GPIO_PIN_6 },
+  { GPIOC, GPIO_PIN_7 },
+  { GPIOC, GPIO_PIN_8 },
+  { GPIOC, GPIO_PIN_9 },
+  { GPIOC, GPIO_PIN_10},
+  { GPIOC, GPIO_PIN_11},
+  { GPIOC, GPIO_PIN_12},
+  { GPIOC, GPIO_PIN_13},
+  { GPIOC, GPIO_PIN_14},
+  { GPIOC, GPIO_PIN_15},
+  { GPIOD, GPIO_PIN_0 },
+  { GPIOD, GPIO_PIN_1 },
+  { GPIOD, GPIO_PIN_2 },
+  { GPIOD, GPIO_PIN_3 },
+  { GPIOD, GPIO_PIN_4 },
+  { GPIOD, GPIO_PIN_5 },
+  { GPIOD, GPIO_PIN_6 },
+  { GPIOD, GPIO_PIN_7 },
+  { GPIOD, GPIO_PIN_8 },
+  { GPIOD, GPIO_PIN_9 },
+  { GPIOD, GPIO_PIN_10},
+  { GPIOD, GPIO_PIN_11},
+  { GPIOD, GPIO_PIN_12},
+  { GPIOD, GPIO_PIN_13},
+  { GPIOD, GPIO_PIN_14},
+  { GPIOD, GPIO_PIN_15},
+  { GPIOE, GPIO_PIN_0 },
+  { GPIOE, GPIO_PIN_1 },
+  { GPIOE, GPIO_PIN_2 },
+  { GPIOE, GPIO_PIN_3 },
+  { GPIOE, GPIO_PIN_4 },
+  { GPIOE, GPIO_PIN_5 },
+  { GPIOE, GPIO_PIN_6 },
+  { GPIOE, GPIO_PIN_7 },
+  { GPIOE, GPIO_PIN_8 },
+  { GPIOE, GPIO_PIN_9 },
+  { GPIOE, GPIO_PIN_10},
+  { GPIOE, GPIO_PIN_11},
+  { GPIOE, GPIO_PIN_12},
+  { GPIOE, GPIO_PIN_13},
+  { GPIOE, GPIO_PIN_14},
+  { GPIOE, GPIO_PIN_15},
+  { GPIOF, GPIO_PIN_0 },
+  { GPIOF, GPIO_PIN_1 },
+  { GPIOF, GPIO_PIN_2 },
+  { GPIOF, GPIO_PIN_3 },
+  { GPIOF, GPIO_PIN_4 },
+  { GPIOF, GPIO_PIN_5 },
+  { GPIOF, GPIO_PIN_6 },
+  { GPIOF, GPIO_PIN_7 },
+  { GPIOF, GPIO_PIN_8 },
+  { GPIOF, GPIO_PIN_9 },
+  { GPIOF, GPIO_PIN_10},
+  { GPIOF, GPIO_PIN_11},
+  { GPIOF, GPIO_PIN_12},
+  { GPIOF, GPIO_PIN_13},
+  { GPIOF, GPIO_PIN_14},
+  { GPIOF, GPIO_PIN_15},
+  { GPIOG, GPIO_PIN_0 },
+  { GPIOG, GPIO_PIN_1 },
+  { GPIOG, GPIO_PIN_2 },
+  { GPIOG, GPIO_PIN_3 },
+  { GPIOG, GPIO_PIN_4 },
+  { GPIOG, GPIO_PIN_5 },
+  { GPIOG, GPIO_PIN_6 },
+  { GPIOG, GPIO_PIN_7 },
+  { GPIOG, GPIO_PIN_8 },
+  { GPIOG, GPIO_PIN_9 },
+  { GPIOG, GPIO_PIN_10},
+  { GPIOG, GPIO_PIN_11},
+  { GPIOG, GPIO_PIN_12},
+  { GPIOG, GPIO_PIN_13},
+  { GPIOG, GPIO_PIN_14},
+  { GPIOG, GPIO_PIN_15},
+  { GPIOH, GPIO_PIN_0 },
+  { GPIOH, GPIO_PIN_1 },
+};
diff --git a/STM32/variants/BLACK_F407ZG/variant.h b/STM32/variants/BLACK_F407ZG/variant.h
new file mode 100644
index 0000000..c3ff233
--- /dev/null
+++ b/STM32/variants/BLACK_F407ZG/variant.h
@@ -0,0 +1,135 @@
+#ifndef VARIANT_H
+#define VARIANT_H
+
+#define LED_BUILTIN PC0
+#define LED_BUILTIN2 PD3
+
+#define STM32_LED_BUILTIN_ACTIVE_LOW
+
+#define MOSI PB5
+#define MISO PB4
+#define SCK PB3
+#define SS PA4
+
+#define SDA PB7
+#define SCL PB6
+
+enum {
+   PA0 ,
+   PA1 ,
+   PA2 ,
+   PA3 ,
+   PA4 ,
+   PA5 ,
+   PA6 ,
+   PA7 ,
+   PA8 ,
+   PA9 ,
+   PA10,
+   PA11,
+   PA12,
+   PA13,
+   PA14,
+   PA15,
+   PB0 ,
+   PB1 ,
+   PB2 ,
+   PB3 ,
+   PB4 ,
+   PB5 ,
+   PB6 ,
+   PB7 ,
+   PB8 ,
+   PB9 ,
+   PB10,
+   PB11,
+   PB12,
+   PB13,
+   PB14,
+   PB15,
+   PC0 ,
+   PC1 ,
+   PC2 ,
+   PC3 ,
+   PC4 ,
+   PC5 ,
+   PC6 ,
+   PC7 ,
+   PC8 ,
+   PC9 ,
+   PC10,
+   PC11,
+   PC12,
+   PC13,
+   PC14,
+   PC15,
+   PD0 ,
+   PD1 ,
+   PD2 ,
+   PD3 ,
+   PD4 ,
+   PD5 ,
+   PD6 ,
+   PD7 ,
+   PD8 ,
+   PD9 ,
+   PD10,
+   PD11,
+   PD12,
+   PD13,
+   PD14,
+   PD15,
+   PE0 ,
+   PE1 ,
+   PE2 ,
+   PE3 ,
+   PE4 ,
+   PE5 ,
+   PE6 ,
+   PE7 ,
+   PE8 ,
+   PE9 ,
+   PE10,
+   PE11,
+   PE12,
+   PE13,
+   PE14,
+   PE15,
+   PF0 ,
+   PF1 ,
+   PF2 ,
+   PF3 ,
+   PF4 ,
+   PF5 ,
+   PF6 ,
+   PF7 ,
+   PF8 ,
+   PF9 ,
+   PF10,
+   PF11,
+   PF12,
+   PF13,
+   PF14,
+   PF15,
+   PG0 ,
+   PG1 ,
+   PG2 ,
+   PG3 ,
+   PG4 ,
+   PG5 ,
+   PG6 ,
+   PG7 ,
+   PG8 ,
+   PG9 ,
+   PG10,
+   PG11,
+   PG12,
+   PG13,
+   PG14,
+   PG15,
+   PH0 ,
+   PH1 ,
+NUM_PINS,
+};
+
+#endif