LL: Add F1 low level headers
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@ -82,6 +82,7 @@
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#include "stm32f1xx_ll_fsmc.c"
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#include "stm32f1xx_ll_sdmmc.c"
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#include "stm32f1xx_ll_usb.c"
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#include "stm32f1xx_ll_utils.c"
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#endif
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#ifdef STM32F2
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#include "stm32f2xx_hal.c"
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@ -0,0 +1,658 @@
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/**
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******************************************************************************
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* @file stm32f1xx_ll_cortex.h
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* @author MCD Application Team
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* @version V1.1.0
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* @date 14-April-2017
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* @brief Header file of CORTEX LL module.
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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The LL CORTEX driver contains a set of generic APIs that can be
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used by user:
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(+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
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functions
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(+) Low power mode configuration (SCB register of Cortex-MCU)
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(+) MPU API to configure and enable regions
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(MPU services provided only on some devices)
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(+) API to access to MCU info (CPUID register)
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(+) API to enable fault handler (SHCSR accesses)
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F1xx_LL_CORTEX_H
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#define __STM32F1xx_LL_CORTEX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx.h"
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/** @addtogroup STM32F1xx_LL_Driver
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* @{
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*/
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/** @defgroup CORTEX_LL CORTEX
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
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* @{
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*/
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/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
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* @{
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*/
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#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
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#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
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* @{
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*/
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#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
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#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
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#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
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/**
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* @}
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*/
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#if __MPU_PRESENT
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/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
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* @{
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*/
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#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
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#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
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#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
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#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
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* @{
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*/
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#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
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#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
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#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
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#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
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#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
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#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
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#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
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#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
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* @{
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*/
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#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
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* @{
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*/
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#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
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#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
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#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
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#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
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#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
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#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
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* @{
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*/
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#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
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#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
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#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
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#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
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* @{
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*/
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#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
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#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
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* @{
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*/
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#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
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#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
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* @{
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*/
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#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
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#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
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* @{
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*/
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#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
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#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
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/**
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* @}
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*/
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#endif /* __MPU_PRESENT */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
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* @{
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*/
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/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
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* @{
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*/
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/**
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* @brief This function checks if the Systick counter flag is active or not.
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* @note It can be used in timeout function on application side.
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* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
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{
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return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
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}
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/**
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* @brief Configures the SysTick clock source
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* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
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* @param Source This parameter can be one of the following values:
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* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
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* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
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* @retval None
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*/
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__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
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{
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if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
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{
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SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
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}
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else
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{
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CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
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}
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}
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/**
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* @brief Get the SysTick clock source
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* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
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* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
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*/
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__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
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{
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return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
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}
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/**
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* @brief Enable SysTick exception request
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* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
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* @retval None
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*/
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__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
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{
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SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
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}
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/**
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* @brief Disable SysTick exception request
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* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
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* @retval None
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*/
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__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
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{
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CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
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}
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/**
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* @brief Checks if the SYSTICK interrupt is enabled or disabled.
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* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
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{
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return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
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}
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
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* @{
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*/
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/**
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* @brief Processor uses sleep as its low power mode
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* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
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* @retval None
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*/
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__STATIC_INLINE void LL_LPM_EnableSleep(void)
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{
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/* Clear SLEEPDEEP bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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}
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/**
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* @brief Processor uses deep sleep as its low power mode
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* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
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* @retval None
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*/
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__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
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{
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/* Set SLEEPDEEP bit of Cortex System Control Register */
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SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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}
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/**
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* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
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* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
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* empty main application.
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* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
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* @retval None
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*/
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__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
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{
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/* Set SLEEPONEXIT bit of Cortex System Control Register */
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SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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}
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/**
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* @brief Do not sleep when returning to Thread mode.
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* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
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* @retval None
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*/
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__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
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{
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/* Clear SLEEPONEXIT bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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}
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/**
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* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
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* processor.
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* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
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* @retval None
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*/
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__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
|
||||
{
|
||||
/* Set SEVEONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
|
||||
* excluded
|
||||
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
|
||||
{
|
||||
/* Clear SEVEONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable a fault in System handler control register (SHCSR)
|
||||
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
|
||||
* @param Fault This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_HANDLER_FAULT_USG
|
||||
* @arg @ref LL_HANDLER_FAULT_BUS
|
||||
* @arg @ref LL_HANDLER_FAULT_MEM
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
|
||||
{
|
||||
/* Enable the system handler fault */
|
||||
SET_BIT(SCB->SHCSR, Fault);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a fault in System handler control register (SHCSR)
|
||||
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
|
||||
* @param Fault This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_HANDLER_FAULT_USG
|
||||
* @arg @ref LL_HANDLER_FAULT_BUS
|
||||
* @arg @ref LL_HANDLER_FAULT_MEM
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
|
||||
{
|
||||
/* Disable the system handler fault */
|
||||
CLEAR_BIT(SCB->SHCSR, Fault);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Implementer code
|
||||
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
|
||||
* @retval Value should be equal to 0x41 for ARM
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Variant number (The r value in the rnpn product revision identifier)
|
||||
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
|
||||
* @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Constant number
|
||||
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
|
||||
* @retval Value should be equal to 0xF for Cortex-M3 devices
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Part number
|
||||
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
|
||||
* @retval Value should be equal to 0xC23 for Cortex-M3
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
|
||||
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
|
||||
* @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if __MPU_PRESENT
|
||||
/** @defgroup CORTEX_LL_EF_MPU MPU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable MPU with input options
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
|
||||
* @param Options This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
|
||||
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
|
||||
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
|
||||
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
|
||||
{
|
||||
/* Enable the MPU*/
|
||||
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
|
||||
/* Ensure MPU settings take effects */
|
||||
__DSB();
|
||||
/* Sequence instruction fetches using update settings */
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable MPU
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_Disable(void)
|
||||
{
|
||||
/* Make sure outstanding transfers are done */
|
||||
__DMB();
|
||||
/* Disable MPU*/
|
||||
WRITE_REG(MPU->CTRL, 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if MPU is enabled or not
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
|
||||
{
|
||||
return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable a MPU region
|
||||
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Enable the MPU region */
|
||||
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure and enable a region
|
||||
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
|
||||
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
|
||||
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR XN LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR AP LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR S LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR C LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR B LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR SIZE LL_MPU_ConfigRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @param Address Value of region base address
|
||||
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
|
||||
* @param Attributes This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
|
||||
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
|
||||
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
|
||||
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
|
||||
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
|
||||
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
|
||||
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
|
||||
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
|
||||
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
|
||||
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
|
||||
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
|
||||
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
|
||||
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Set base address */
|
||||
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
|
||||
/* Configure MPU */
|
||||
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a region
|
||||
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
|
||||
* MPU_RASR ENABLE LL_MPU_DisableRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Disable the MPU region */
|
||||
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __MPU_PRESENT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_LL_CORTEX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,592 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_ll_system.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of SYSTEM LL module.
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The LL SYSTEM driver contains a set of generic APIs that can be
|
||||
used by user:
|
||||
(+) Some of the FLASH features need to be handled in the SYSTEM file.
|
||||
(+) Access to DBGCMU registers
|
||||
(+) Access to SYSCFG registers
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_LL_SYSTEM_H
|
||||
#define __STM32F1xx_LL_SYSTEM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (FLASH) || defined (DBGMCU)
|
||||
|
||||
/** @defgroup SYSTEM_LL SYSTEM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
|
||||
* @{
|
||||
*/
|
||||
#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
|
||||
#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
|
||||
#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
|
||||
#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
|
||||
#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
|
||||
* @{
|
||||
*/
|
||||
#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
|
||||
#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
|
||||
#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
|
||||
#if defined(DBGMCU_CR_DBG_TIM5_STOP)
|
||||
#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_TIM5_STOP */
|
||||
#if defined(DBGMCU_CR_DBG_TIM6_STOP)
|
||||
#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_TIM6_STOP */
|
||||
#if defined(DBGMCU_CR_DBG_TIM7_STOP)
|
||||
#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_TIM7_STOP */
|
||||
#if defined(DBGMCU_CR_DBG_TIM12_STOP)
|
||||
#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_TIM12_STOP */
|
||||
#if defined(DBGMCU_CR_DBG_TIM13_STOP)
|
||||
#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_TIM13_STOP */
|
||||
#if defined(DBGMCU_CR_DBG_TIM14_STOP)
|
||||
#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_TIM14_STOP */
|
||||
#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_CR_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
|
||||
#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
|
||||
#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
|
||||
#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_STOP /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
|
||||
#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_STOP /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
|
||||
#if defined(DBGMCU_CR_DBG_CAN1_STOP)
|
||||
#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_CAN1_STOP */
|
||||
#if defined(DBGMCU_CR_DBG_CAN2_STOP)
|
||||
#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_CAN2_STOP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
|
||||
* @{
|
||||
*/
|
||||
#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
|
||||
#if defined(DBGMCU_CR_DBG_TIM8_STOP)
|
||||
#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_CAN1_STOP */
|
||||
#if defined(DBGMCU_CR_DBG_TIM9_STOP)
|
||||
#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_TIM9_STOP */
|
||||
#if defined(DBGMCU_CR_DBG_TIM10_STOP)
|
||||
#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_TIM10_STOP */
|
||||
#if defined(DBGMCU_CR_DBG_TIM11_STOP)
|
||||
#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_TIM11_STOP */
|
||||
#if defined(DBGMCU_CR_DBG_TIM15_STOP)
|
||||
#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_TIM15_STOP */
|
||||
#if defined(DBGMCU_CR_DBG_TIM16_STOP)
|
||||
#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_TIM16_STOP */
|
||||
#if defined(DBGMCU_CR_DBG_TIM17_STOP)
|
||||
#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
|
||||
#endif /* DBGMCU_CR_DBG_TIM17_STOP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
|
||||
* @{
|
||||
*/
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
|
||||
#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
|
||||
#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
|
||||
#else
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the device identifier
|
||||
* @note For Low Density devices, the device ID is 0x412
|
||||
* @note For Medium Density devices, the device ID is 0x410
|
||||
* @note For High Density devices, the device ID is 0x414
|
||||
* @note For XL Density devices, the device ID is 0x430
|
||||
* @note For Connectivity Line devices, the device ID is 0x418
|
||||
* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
|
||||
* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the device revision identifier
|
||||
* @note This field indicates the revision of the device.
|
||||
For example, it is read as revA -> 0x1000,for Low Density devices
|
||||
For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
|
||||
For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
|
||||
For example, it is read as revA or 1 -> 0x1003,for XL Density devices
|
||||
For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
|
||||
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
|
||||
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during SLEEP mode
|
||||
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during SLEEP mode
|
||||
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STOP mode
|
||||
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STOP mode
|
||||
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STANDBY mode
|
||||
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STANDBY mode
|
||||
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Trace pin assignment control
|
||||
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
|
||||
* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
|
||||
* @param PinAssignment This parameter can be one of the following values:
|
||||
* @arg @ref LL_DBGMCU_TRACE_NONE
|
||||
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
|
||||
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
|
||||
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
|
||||
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
|
||||
{
|
||||
MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Trace pin assignment control
|
||||
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
|
||||
* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_DBGMCU_TRACE_NONE
|
||||
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
|
||||
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
|
||||
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
|
||||
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Freeze APB1 peripherals (group1 peripherals)
|
||||
* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unfreeze APB1 peripherals (group1 peripherals)
|
||||
* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||
* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Freeze APB2 peripherals
|
||||
* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unfreeze APB2 peripherals
|
||||
* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||
* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
|
||||
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, Periphs);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
/** @defgroup SYSTEM_LL_EF_FLASH FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set FLASH Latency
|
||||
* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
|
||||
* @param Latency This parameter can be one of the following values:
|
||||
* @arg @ref LL_FLASH_LATENCY_0
|
||||
* @arg @ref LL_FLASH_LATENCY_1
|
||||
* @arg @ref LL_FLASH_LATENCY_2
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
|
||||
{
|
||||
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get FLASH Latency
|
||||
* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_FLASH_LATENCY_0
|
||||
* @arg @ref LL_FLASH_LATENCY_1
|
||||
* @arg @ref LL_FLASH_LATENCY_2
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Prefetch
|
||||
* @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
|
||||
{
|
||||
SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Prefetch
|
||||
* @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
|
||||
{
|
||||
CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Prefetch buffer is enabled
|
||||
* @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
|
||||
{
|
||||
return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
|
||||
}
|
||||
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
/**
|
||||
* @brief Enable Flash Half Cycle Access
|
||||
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
|
||||
{
|
||||
SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Flash Half Cycle Access
|
||||
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
|
||||
{
|
||||
CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Flash Half Cycle Access is enabled or not
|
||||
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
|
||||
{
|
||||
return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (FLASH) || defined (DBGMCU) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_LL_SYSTEM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -0,0 +1,623 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_ll_utils.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 14-April-2017
|
||||
* @brief UTILS LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx_ll_rcc.h"
|
||||
#include "stm32f1xx_ll_utils.h"
|
||||
#include "stm32f1xx_ll_system.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F1xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UTILS_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @addtogroup UTILS_LL_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Defines used for PLL range */
|
||||
#define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY /*!< Frequency max for PLL output, in Hz */
|
||||
|
||||
/* Defines used for HSE range */
|
||||
#define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN /*!< Frequency min for HSE frequency, in Hz */
|
||||
#define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX /*!< Frequency max for HSE frequency, in Hz */
|
||||
|
||||
/* Defines used for FLASH latency according to HCLK Frequency */
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
|
||||
#define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */
|
||||
#else
|
||||
/*!< No Latency Configuration in this device */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup UTILS_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
|
||||
|
||||
#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
|
||||
|| ((__VALUE__) == LL_RCC_APB1_DIV_2) \
|
||||
|| ((__VALUE__) == LL_RCC_APB1_DIV_4) \
|
||||
|| ((__VALUE__) == LL_RCC_APB1_DIV_8) \
|
||||
|| ((__VALUE__) == LL_RCC_APB1_DIV_16))
|
||||
|
||||
#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
|
||||
|| ((__VALUE__) == LL_RCC_APB2_DIV_2) \
|
||||
|| ((__VALUE__) == LL_RCC_APB2_DIV_4) \
|
||||
|| ((__VALUE__) == LL_RCC_APB2_DIV_8) \
|
||||
|| ((__VALUE__) == LL_RCC_APB2_DIV_16))
|
||||
|
||||
#if defined(RCC_CFGR_PLLMULL6_5)
|
||||
#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_5) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_6) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_7) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_8) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_9) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_6_5))
|
||||
#else
|
||||
#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_3) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_4) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_5) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_6) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_7) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_8) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_9) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_10) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_11) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_12) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_13) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_14) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_15) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_16))
|
||||
#endif /* RCC_CFGR_PLLMULL6_5 */
|
||||
|
||||
#if defined(RCC_CFGR2_PREDIV1)
|
||||
#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
|
||||
#else
|
||||
#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
|
||||
#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/
|
||||
|
||||
#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
|
||||
|
||||
|
||||
#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
|
||||
|| ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
|
||||
|
||||
#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
|
||||
* @{
|
||||
*/
|
||||
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
static ErrorStatus UTILS_PLL_IsBusy(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup UTILS_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UTILS_LL_EF_DELAY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Cortex-M SysTick source to have 1ms time base.
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the Systick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param HCLKFrequency HCLK frequency in Hz
|
||||
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
|
||||
* @retval None
|
||||
*/
|
||||
void LL_Init1msTick(uint32_t HCLKFrequency)
|
||||
{
|
||||
/* Use frequency provided in argument */
|
||||
LL_InitTick(HCLKFrequency, 1000U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides accurate delay (in milliseconds) based
|
||||
* on SysTick counter flag
|
||||
* @note When a RTOS is used, it is recommended to avoid using blocking delay
|
||||
* and use rather osDelay service.
|
||||
* @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
|
||||
* will configure Systick to 1ms
|
||||
* @param Delay specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_mDelay(uint32_t Delay)
|
||||
{
|
||||
__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
|
||||
/* Add this code to indicate that local variable is not used */
|
||||
((void)tmp);
|
||||
|
||||
/* Add a period to guaranty minimum wait */
|
||||
if (Delay < LL_MAX_DELAY)
|
||||
{
|
||||
Delay++;
|
||||
}
|
||||
|
||||
while (Delay)
|
||||
{
|
||||
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
|
||||
{
|
||||
Delay--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UTILS_EF_SYSTEM
|
||||
* @brief System Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### System Configuration functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
System, AHB and APB buses clocks configuration
|
||||
|
||||
(+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.
|
||||
@endverbatim
|
||||
@internal
|
||||
Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
|
||||
(++) +-----------------------------------------------+
|
||||
(++) | Latency | SYSCLK clock frequency (MHz) |
|
||||
(++) |---------------|-------------------------------|
|
||||
(++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
|
||||
(++) |---------------|-------------------------------|
|
||||
(++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
|
||||
(++) |---------------|-------------------------------|
|
||||
(++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
|
||||
(++) +-----------------------------------------------+
|
||||
@endinternal
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function sets directly SystemCoreClock CMSIS variable.
|
||||
* @note Variable can be calculated also through SystemCoreClockUpdate function.
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @retval None
|
||||
*/
|
||||
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
|
||||
{
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock = HCLKFrequency;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures system clock with HSI as clock source of the PLL
|
||||
* @note The application need to ensure that PLL is disabled.
|
||||
* @note Function is based on the following formula:
|
||||
* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
|
||||
* - PREDIV: Set to 2 for few devices
|
||||
* - PLLMUL: The application software must set correctly the PLL multiplication factor to
|
||||
* not exceed 72MHz
|
||||
* @note FLASH latency can be modified through this function.
|
||||
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
|
||||
* the configuration information for the PLL.
|
||||
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
|
||||
* the configuration information for the BUS prescalers.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Max frequency configuration done
|
||||
* - ERROR: Max frequency configuration not done
|
||||
*/
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t pllfreq = 0U;
|
||||
|
||||
/* Check if one of the PLL is enabled */
|
||||
if (UTILS_PLL_IsBusy() == SUCCESS)
|
||||
{
|
||||
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
||||
/* Check PREDIV value */
|
||||
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
|
||||
#else
|
||||
/* Force PREDIV value to 2 */
|
||||
UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
|
||||
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
|
||||
/* Calculate the new PLL output frequency */
|
||||
pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
|
||||
|
||||
/* Enable HSI if not enabled */
|
||||
if (LL_RCC_HSI_IsReady() != 1U)
|
||||
{
|
||||
LL_RCC_HSI_Enable();
|
||||
while (LL_RCC_HSI_IsReady() != 1U)
|
||||
{
|
||||
/* Wait for HSI ready */
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure PLL */
|
||||
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
|
||||
|
||||
/* Enable PLL and switch system clock to PLL */
|
||||
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Current PLL configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures system clock with HSE as clock source of the PLL
|
||||
* @note The application need to ensure that PLL is disabled.
|
||||
* @note Function is based on the following formula:
|
||||
* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
|
||||
* - PREDIV: Set to 2 for few devices
|
||||
* - PLLMUL: The application software must set correctly the PLL multiplication factor to
|
||||
* not exceed @ref UTILS_PLL_OUTPUT_MAX
|
||||
* @note FLASH latency can be modified through this function.
|
||||
* @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
|
||||
* @param HSEBypass This parameter can be one of the following values:
|
||||
* @arg @ref LL_UTILS_HSEBYPASS_ON
|
||||
* @arg @ref LL_UTILS_HSEBYPASS_OFF
|
||||
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
|
||||
* the configuration information for the PLL.
|
||||
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
|
||||
* the configuration information for the BUS prescalers.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Max frequency configuration done
|
||||
* - ERROR: Max frequency configuration not done
|
||||
*/
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t pllfreq = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
|
||||
assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
|
||||
|
||||
/* Check if one of the PLL is enabled */
|
||||
if (UTILS_PLL_IsBusy() == SUCCESS)
|
||||
{
|
||||
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
|
||||
|
||||
/* Calculate the new PLL output frequency */
|
||||
pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
|
||||
|
||||
/* Enable HSE if not enabled */
|
||||
if (LL_RCC_HSE_IsReady() != 1U)
|
||||
{
|
||||
/* Check if need to enable HSE bypass feature or not */
|
||||
if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
|
||||
{
|
||||
LL_RCC_HSE_EnableBypass();
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_RCC_HSE_DisableBypass();
|
||||
}
|
||||
|
||||
/* Enable HSE */
|
||||
LL_RCC_HSE_Enable();
|
||||
while (LL_RCC_HSE_IsReady() != 1U)
|
||||
{
|
||||
/* Wait for HSE ready */
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure PLL */
|
||||
LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
|
||||
|
||||
/* Enable PLL and switch system clock to PLL */
|
||||
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Current PLL configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UTILS_LL_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Update number of Flash wait states in line with new frequency and current
|
||||
voltage range.
|
||||
* @param Frequency SYSCLK frequency
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Latency has been modified
|
||||
* - ERROR: Latency cannot be modified
|
||||
*/
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
|
||||
|
||||
/* Frequency cannot be equal to 0 */
|
||||
if (Frequency == 0U)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (Frequency > UTILS_LATENCY2_FREQ)
|
||||
{
|
||||
/* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
|
||||
latency = LL_FLASH_LATENCY_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (Frequency > UTILS_LATENCY1_FREQ)
|
||||
{
|
||||
/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
|
||||
latency = LL_FLASH_LATENCY_1;
|
||||
}
|
||||
/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
|
||||
}
|
||||
|
||||
LL_FLASH_SetLatency(latency);
|
||||
|
||||
/* Check that the new number of wait states is taken into account to access the Flash
|
||||
memory by reading the FLASH_ACR register */
|
||||
if (LL_FLASH_GetLatency() != latency)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
|
||||
/**
|
||||
* @brief Function to check that PLL can be modified
|
||||
* @param PLL_InputFrequency PLL input frequency (in Hz)
|
||||
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
|
||||
* the configuration information for the PLL.
|
||||
* @retval PLL output frequency (in Hz)
|
||||
*/
|
||||
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
|
||||
{
|
||||
uint32_t pllfreq = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
|
||||
|
||||
/* Check different PLL parameters according to RM */
|
||||
#if defined (RCC_CFGR2_PREDIV1)
|
||||
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
|
||||
#elif defined(RCC_CFGR2_PREDIV1SRC)
|
||||
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
|
||||
#else
|
||||
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
|
||||
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
||||
assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
|
||||
|
||||
return pllfreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to check that PLL can be modified
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: PLL modification can be done
|
||||
* - ERROR: PLL is busy
|
||||
*/
|
||||
static ErrorStatus UTILS_PLL_IsBusy(void)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check if PLL is busy*/
|
||||
if (LL_RCC_PLL_IsReady() != 0U)
|
||||
{
|
||||
/* PLL configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
#if defined(RCC_PLL2_SUPPORT)
|
||||
/* Check if PLL2 is busy*/
|
||||
if (LL_RCC_PLL2_IsReady() != 0U)
|
||||
{
|
||||
/* PLL2 configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
#endif /* RCC_PLL2_SUPPORT */
|
||||
|
||||
#if defined(RCC_PLLI2S_SUPPORT)
|
||||
/* Check if PLLI2S is busy*/
|
||||
if (LL_RCC_PLLI2S_IsReady() != 0U)
|
||||
{
|
||||
/* PLLI2S configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
#endif /* RCC_PLLI2S_SUPPORT */
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to enable PLL and switch system clock to PLL
|
||||
* @param SYSCLK_Frequency SYSCLK frequency
|
||||
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
|
||||
* the configuration information for the BUS prescalers.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: No problem to switch system to PLL
|
||||
* - ERROR: Problem to switch system to PLL
|
||||
*/
|
||||
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
uint32_t sysclk_frequency_current = 0U;
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
|
||||
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
|
||||
assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
|
||||
assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
|
||||
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
/* Calculate current SYSCLK frequency */
|
||||
sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]);
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
|
||||
/* Increasing the number of wait states because of higher CPU frequency */
|
||||
#if defined (FLASH_ACR_LATENCY)
|
||||
if (sysclk_frequency_current < SYSCLK_Frequency)
|
||||
{
|
||||
/* Set FLASH latency to highest latency */
|
||||
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
|
||||
}
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
|
||||
/* Update system clock configuration */
|
||||
if (status == SUCCESS)
|
||||
{
|
||||
#if defined(RCC_PLL2_SUPPORT)
|
||||
/* Enable PLL2 */
|
||||
LL_RCC_PLL2_Enable();
|
||||
while (LL_RCC_PLL2_IsReady() != 1U)
|
||||
{
|
||||
/* Wait for PLL2 ready */
|
||||
}
|
||||
|
||||
#endif /* RCC_PLL2_SUPPORT */
|
||||
/* Enable PLL */
|
||||
LL_RCC_PLL_Enable();
|
||||
while (LL_RCC_PLL_IsReady() != 1U)
|
||||
{
|
||||
/* Wait for PLL ready */
|
||||
}
|
||||
|
||||
/* Sysclk activation on the main PLL */
|
||||
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
||||
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
|
||||
{
|
||||
/* Wait for system clock switch to PLL */
|
||||
}
|
||||
|
||||
/* Set APB1 & APB2 prescaler*/
|
||||
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
|
||||
LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
|
||||
}
|
||||
|
||||
/* Decreasing the number of wait states because of lower CPU frequency */
|
||||
#if defined (FLASH_ACR_LATENCY)
|
||||
if (sysclk_frequency_current > SYSCLK_Frequency)
|
||||
{
|
||||
/* Set FLASH latency to lowest latency */
|
||||
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
|
||||
}
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
|
||||
/* Update SystemCoreClock variable */
|
||||
if (status == SUCCESS)
|
||||
{
|
||||
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -0,0 +1,284 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_ll_utils.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of UTILS LL module.
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The LL UTILS driver contains a set of generic APIs that can be
|
||||
used by user:
|
||||
(+) Device electronic signature
|
||||
(+) Timing functions
|
||||
(+) PLL configuration functions
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_LL_UTILS_H
|
||||
#define __STM32F1xx_LL_UTILS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f1xx.h"
|
||||
|
||||
/** @addtogroup STM32F1xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL UTILS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Max delay can be used in LL_mDelay */
|
||||
#define LL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* @brief Unique device ID register base address
|
||||
*/
|
||||
#define UID_BASE_ADDRESS UID_BASE
|
||||
|
||||
/**
|
||||
* @brief Flash size data register base address
|
||||
*/
|
||||
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief UTILS PLL structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
|
||||
uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
} LL_UTILS_PLLInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief UTILS System, AHB and APB buses clock configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAHBPrescaler(). */
|
||||
|
||||
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB1Prescaler(). */
|
||||
|
||||
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB2Prescaler(). */
|
||||
|
||||
} LL_UTILS_ClkInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
|
||||
* @{
|
||||
*/
|
||||
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
|
||||
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[31:0]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[63:32]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[95:64]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Flash memory size
|
||||
* @note This bitfield indicates the size of the device Flash memory expressed in
|
||||
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
|
||||
* @retval FLASH_SIZE[15:0]: Flash memory size
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
||||
{
|
||||
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL_EF_DELAY DELAY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Cortex-M SysTick source of the time base.
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param Ticks Number of ticks
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||
{
|
||||
/* Configure the SysTick to have interrupt in 1ms time base */
|
||||
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
|
||||
}
|
||||
|
||||
void LL_Init1msTick(uint32_t HCLKFrequency);
|
||||
void LL_mDelay(uint32_t Delay);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_SYSTEM SYSTEM
|
||||
* @{
|
||||
*/
|
||||
|
||||
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_LL_UTILS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
Loading…
Reference in New Issue