1557 lines
28 KiB
HTML
1557 lines
28 KiB
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<li class="main active"><a href="#black-f407zg-m4-demo">BLACK F407ZG (M4 DEMO)</a></li>
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<li><a href="#spi">SPI</a></li>
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<li><a href="#i2c">I2C</a></li>
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<li><a href="#usart">USART</a></li>
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<li><a href="#tim">TIM</a></li>
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<li><a href="#adc">ADC</a></li>
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<li><a href="#gpio">GPIO</a></li>
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</div></div>
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<div class="col-md-9" role="main">
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<h1 id="black-f407zg-m4-demo">BLACK F407ZG (M4 DEMO)</h1>
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<p>Below are the pins usable for the peripherals. Pins in <strong>bold</strong> are the default.</p>
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<h2 id="spi">SPI</h2>
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<table>
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<thead>
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<tr>
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<th>Instance</th>
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<th>MOSI</th>
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<th>MISO</th>
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<th>SCK</th>
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<th></th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td>SPI1</td>
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<td><strong>PA7</strong>, PB5</td>
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<td><strong>PA6</strong>, PB4</td>
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<td><strong>PA5</strong>, PB3</td>
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<td></td>
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</tr>
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<tr>
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<td>SPI2</td>
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<td><strong>PB15</strong>, PC3</td>
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<td><strong>PB14</strong>, PC2</td>
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<td><strong>PB10</strong>, PB13</td>
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<td></td>
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</tr>
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<tr>
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<td>SPI3</td>
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<td><strong>PB5</strong>, PC12</td>
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<td><strong>PB4</strong>, PC11</td>
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<td><strong>PB3</strong>, PC10</td>
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<td></td>
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</tr>
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</tbody>
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</table>
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<h2 id="i2c">I2C</h2>
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<table>
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<thead>
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<tr>
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<th>Instance</th>
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<th>SDA</th>
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<th>SCL</th>
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<th></th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td>I2C1</td>
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<td><strong>PB7</strong>, PB9</td>
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<td><strong>PB6</strong>, PB8</td>
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<td></td>
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</tr>
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<tr>
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<td>I2C2</td>
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<td><strong>PB11</strong>, PF0</td>
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<td><strong>PB10</strong>, PF1</td>
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<td></td>
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</tr>
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<tr>
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<td>I2C3</td>
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<td><strong>PC9</strong></td>
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<td><strong>PA8</strong></td>
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<td></td>
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</tr>
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</tbody>
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</table>
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<h2 id="usart">USART</h2>
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<table>
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<thead>
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<tr>
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<th>Instance</th>
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<th>RX</th>
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<th>TX</th>
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<th></th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td>UART4</td>
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<td><strong>PA1</strong>, PC11</td>
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<td><strong>PA0</strong>, PC10</td>
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<td></td>
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</tr>
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<tr>
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<td>UART5</td>
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<td><strong>PD2</strong></td>
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<td><strong>PC12</strong></td>
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<td></td>
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</tr>
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<tr>
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<td>USART1</td>
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<td><strong>PA10</strong>, PB7</td>
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<td><strong>PA9</strong>, PB6</td>
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<td></td>
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</tr>
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<tr>
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<td>USART2</td>
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<td><strong>PA3</strong>, PD6</td>
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<td><strong>PA2</strong>, PD5</td>
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<td></td>
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</tr>
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<tr>
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<td>USART3</td>
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<td><strong>PB11</strong>, PC11, PD9</td>
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<td><strong>PB10</strong>, PC10, PD8</td>
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<td></td>
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</tr>
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<tr>
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<td>USART6</td>
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<td><strong>PC7</strong>, PG9</td>
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<td><strong>PC6</strong>, PG14</td>
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<td></td>
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</tr>
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</tbody>
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</table>
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<h2 id="i2s">I2S</h2>
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<table>
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<thead>
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<tr>
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<th>Instance</th>
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<th>CK</th>
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<th>SD</th>
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<th>WS</th>
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<th>MCK</th>
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<th></th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td>I2S2</td>
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<td><strong>PB10</strong>, PB13</td>
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<td><strong>PB15</strong>, PC3</td>
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<td><strong>PB9</strong>, PB12</td>
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<td><strong>PC6</strong></td>
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<td></td>
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</tr>
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<tr>
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<td>I2S3</td>
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<td><strong>PB3</strong>, PC10</td>
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<td><strong>PB5</strong>, PC12</td>
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<td><strong>PA4</strong>, PA15</td>
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<td><strong>PC7</strong></td>
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<td></td>
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</tr>
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</tbody>
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</table>
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<h2 id="tim">TIM</h2>
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<table>
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<thead>
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<tr>
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<th>Instance</th>
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<th>CH1</th>
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<th>CH2</th>
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<th>CH3</th>
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<th>CH4</th>
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<th></th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td>TIM1</td>
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<td><strong>PA8</strong>, PE9, <span style="text-decoration: overline">PA7</span>, <span style="text-decoration: overline">PB13</span>, <span style="text-decoration: overline">PE8</span></td>
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<td><strong>PA9</strong>, PE11, <span style="text-decoration: overline">PB0</span>, <span style="text-decoration: overline">PB14</span>, <span style="text-decoration: overline">PE10</span></td>
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<td><strong>PA10</strong>, PE13, <span style="text-decoration: overline">PB1</span>, <span style="text-decoration: overline">PB15</span>, <span style="text-decoration: overline">PE12</span></td>
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<td><strong>PA11</strong>, PE14</td>
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<td></td>
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</tr>
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<tr>
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<td>TIM2</td>
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<td><strong>PA0</strong>, PA5, PA15</td>
|
|
<td><strong>PA1</strong>, PB3</td>
|
|
<td><strong>PA2</strong>, PB10</td>
|
|
<td><strong>PA3</strong>, PB11</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>TIM3</td>
|
|
<td><strong>PA6</strong>, PB4, PC6</td>
|
|
<td><strong>PA7</strong>, PB5, PC7</td>
|
|
<td><strong>PB0</strong>, PC8</td>
|
|
<td><strong>PB1</strong>, PC9</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>TIM4</td>
|
|
<td><strong>PB6</strong>, PD12</td>
|
|
<td><strong>PB7</strong>, PD13</td>
|
|
<td><strong>PB8</strong>, PD14</td>
|
|
<td><strong>PB9</strong>, PD15</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>TIM5</td>
|
|
<td><strong>PA0</strong></td>
|
|
<td><strong>PA1</strong></td>
|
|
<td><strong>PA2</strong></td>
|
|
<td><strong>PA3</strong></td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>TIM8</td>
|
|
<td><strong>PC6</strong>, <span style="text-decoration: overline">PA5</span>, <span style="text-decoration: overline">PA7</span></td>
|
|
<td><strong>PC7</strong>, <span style="text-decoration: overline">PB0</span>, <span style="text-decoration: overline">PB14</span></td>
|
|
<td><strong>PC8</strong>, <span style="text-decoration: overline">PB1</span>, <span style="text-decoration: overline">PB15</span></td>
|
|
<td><strong>PC9</strong></td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>TIM9</td>
|
|
<td><strong>PA2</strong>, PE5</td>
|
|
<td><strong>PA3</strong>, PE6</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>TIM10</td>
|
|
<td><strong>PB8</strong>, PF6</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>TIM11</td>
|
|
<td><strong>PB9</strong>, PF7</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>TIM12</td>
|
|
<td><strong>PB14</strong></td>
|
|
<td><strong>PB15</strong></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>TIM13</td>
|
|
<td><strong>PA6</strong>, PF8</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>TIM14</td>
|
|
<td><strong>PA7</strong>, PF9</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<h2 id="adc">ADC</h2>
|
|
<table>
|
|
<thead>
|
|
<tr>
|
|
<th>Instance</th>
|
|
<th>Channel</th>
|
|
<th>Pin</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN0</td>
|
|
<td>PA0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN1</td>
|
|
<td>PA1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN2</td>
|
|
<td>PA2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN3</td>
|
|
<td>PA3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN4</td>
|
|
<td>PA4</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN5</td>
|
|
<td>PA5</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN6</td>
|
|
<td>PA6</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN7</td>
|
|
<td>PA7</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN8</td>
|
|
<td>PB0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN9</td>
|
|
<td>PB1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN10</td>
|
|
<td>PC0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN11</td>
|
|
<td>PC1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN12</td>
|
|
<td>PC2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN13</td>
|
|
<td>PC3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN14</td>
|
|
<td>PC4</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC1</td>
|
|
<td>IN15</td>
|
|
<td>PC5</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN0</td>
|
|
<td>PA0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN1</td>
|
|
<td>PA1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN2</td>
|
|
<td>PA2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN3</td>
|
|
<td>PA3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN4</td>
|
|
<td>PA4</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN5</td>
|
|
<td>PA5</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN6</td>
|
|
<td>PA6</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN7</td>
|
|
<td>PA7</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN8</td>
|
|
<td>PB0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN9</td>
|
|
<td>PB1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN10</td>
|
|
<td>PC0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN11</td>
|
|
<td>PC1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN12</td>
|
|
<td>PC2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN13</td>
|
|
<td>PC3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN14</td>
|
|
<td>PC4</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC2</td>
|
|
<td>IN15</td>
|
|
<td>PC5</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN0</td>
|
|
<td>PA0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN1</td>
|
|
<td>PA1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN2</td>
|
|
<td>PA2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN3</td>
|
|
<td>PA3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN4</td>
|
|
<td>PF6</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN5</td>
|
|
<td>PF7</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN6</td>
|
|
<td>PF8</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN7</td>
|
|
<td>PF9</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN8</td>
|
|
<td>PF10</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN9</td>
|
|
<td>PF3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN10</td>
|
|
<td>PC0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN11</td>
|
|
<td>PC1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN12</td>
|
|
<td>PC2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN13</td>
|
|
<td>PC3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN14</td>
|
|
<td>PF4</td>
|
|
</tr>
|
|
<tr>
|
|
<td>ADC3</td>
|
|
<td>IN15</td>
|
|
<td>PF5</td>
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<h2 id="gpio">GPIO</h2>
|
|
<table>
|
|
<thead>
|
|
<tr>
|
|
<th>Pin</th>
|
|
<th>Peripheral signal available on the pin</th>
|
|
<th>Board macro</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>PA0</td>
|
|
<td>ADC1_IN0, ADC2_IN0, ADC3_IN0, ETH_CRS, SYS_WKUP, TIM2_CH1, TIM2_ETR, TIM5_CH1, TIM8_ETR, UART4_TX, USART2_CTS</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA1</td>
|
|
<td>ADC1_IN1, ADC2_IN1, ADC3_IN1, ETH_REF_CLK, ETH_RX_CLK, TIM2_CH2, TIM5_CH2, UART4_RX, USART2_RTS</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA2</td>
|
|
<td>ADC1_IN2, ADC2_IN2, ADC3_IN2, ETH_MDIO, TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA3</td>
|
|
<td>ADC1_IN3, ADC2_IN3, ADC3_IN3, ETH_COL, TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX, USB_OTG_HS_ULPI_D0</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA4</td>
|
|
<td>ADC1_IN4, ADC2_IN4, DAC_OUT1, DCMI_HSYNC, I2S3_WS, SPI1_NSS, SPI3_NSS, USART2_CK, USB_OTG_HS_SOF</td>
|
|
<td><strong>SS</strong></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA5</td>
|
|
<td>ADC1_IN5, ADC2_IN5, DAC_OUT2, SPI1_SCK, TIM2_CH1, TIM2_ETR, TIM8_CH1N, USB_OTG_HS_ULPI_CK</td>
|
|
<td><strong>SCK</strong></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA6</td>
|
|
<td>ADC1_IN6, ADC2_IN6, DCMI_PIXCK, SPI1_MISO, TIM1_BKIN, TIM3_CH1, TIM8_BKIN, TIM13_CH1</td>
|
|
<td><strong>MISO</strong></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA7</td>
|
|
<td>ADC1_IN7, ADC2_IN7, ETH_CRS_DV, ETH_RX_DV, SPI1_MOSI, TIM1_CH1N, TIM3_CH2, TIM8_CH1N, TIM14_CH1</td>
|
|
<td><strong>MOSI</strong></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA8</td>
|
|
<td>I2C3_SCL, RCC_MCO_1, TIM1_CH1, USART1_CK, USB_OTG_FS_SOF</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA9</td>
|
|
<td>DCMI_D0, I2C3_SMBA, TIM1_CH2, USART1_TX, USB_OTG_FS_VBUS</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA10</td>
|
|
<td>DCMI_D1, TIM1_CH3, USART1_RX, USB_OTG_FS_ID</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA11</td>
|
|
<td>CAN1_RX, TIM1_CH4, USART1_CTS, USB_OTG_FS_DM</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA12</td>
|
|
<td>CAN1_TX, TIM1_ETR, USART1_RTS, USB_OTG_FS_DP</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA13</td>
|
|
<td>SYS_JTMS-SWDIO</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA14</td>
|
|
<td>SYS_JTCK-SWCLK</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PA15</td>
|
|
<td>I2S3_WS, SPI1_NSS, SPI3_NSS, SYS_JTDI, TIM2_CH1, TIM2_ETR</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB0</td>
|
|
<td>ADC1_IN8, ADC2_IN8, ETH_RXD2, TIM1_CH2N, TIM3_CH3, TIM8_CH2N, USB_OTG_HS_ULPI_D1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB1</td>
|
|
<td>ADC1_IN9, ADC2_IN9, ETH_RXD3, TIM1_CH3N, TIM3_CH4, TIM8_CH3N, USB_OTG_HS_ULPI_D2</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB2</td>
|
|
<td></td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB3</td>
|
|
<td>I2S3_CK, SPI1_SCK, SPI3_SCK, SYS_JTDO-SWO, TIM2_CH2</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB4</td>
|
|
<td>I2S3_ext_SD, SPI1_MISO, SPI3_MISO, SYS_JTRST, TIM3_CH1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB5</td>
|
|
<td>CAN2_RX, DCMI_D10, ETH_PPS_OUT, I2C1_SMBA, I2S3_SD, SPI1_MOSI, SPI3_MOSI, TIM3_CH2, USB_OTG_HS_ULPI_D7</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB6</td>
|
|
<td>CAN2_TX, DCMI_D5, I2C1_SCL, TIM4_CH1, USART1_TX</td>
|
|
<td><strong>SCL</strong></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB7</td>
|
|
<td>DCMI_VSYNC, FSMC_NL, I2C1_SDA, TIM4_CH2, USART1_RX</td>
|
|
<td><strong>SDA</strong></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB8</td>
|
|
<td>CAN1_RX, DCMI_D6, ETH_TXD3, I2C1_SCL, SDIO_D4, TIM4_CH3, TIM10_CH1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB9</td>
|
|
<td>CAN1_TX, DCMI_D7, I2C1_SDA, I2S2_WS, SDIO_D5, SPI2_NSS, TIM4_CH4, TIM11_CH1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB10</td>
|
|
<td>ETH_RX_ER, I2C2_SCL, I2S2_CK, SPI2_SCK, TIM2_CH3, USART3_TX, USB_OTG_HS_ULPI_D3</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB11</td>
|
|
<td>ETH_TX_EN, I2C2_SDA, TIM2_CH4, USART3_RX, USB_OTG_HS_ULPI_D4</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB12</td>
|
|
<td>CAN2_RX, ETH_TXD0, I2C2_SMBA, I2S2_WS, SPI2_NSS, TIM1_BKIN, USART3_CK, USB_OTG_HS_ID, USB_OTG_HS_ULPI_D5</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB13</td>
|
|
<td>CAN2_TX, ETH_TXD1, I2S2_CK, SPI2_SCK, TIM1_CH1N, USART3_CTS, USB_OTG_HS_ULPI_D6, USB_OTG_HS_VBUS</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB14</td>
|
|
<td>I2S2_ext_SD, SPI2_MISO, TIM1_CH2N, TIM8_CH2N, TIM12_CH1, USART3_RTS, USB_OTG_HS_DM</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PB15</td>
|
|
<td>I2S2_SD, RTC_REFIN, SPI2_MOSI, TIM1_CH3N, TIM8_CH3N, TIM12_CH2, USB_OTG_HS_DP</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC0</td>
|
|
<td>ADC1_IN10, ADC2_IN10, ADC3_IN10, USB_OTG_HS_ULPI_STP</td>
|
|
<td><strong>LED_BUILTIN</strong></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC1</td>
|
|
<td>ADC1_IN11, ADC2_IN11, ADC3_IN11, ETH_MDC</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC2</td>
|
|
<td>ADC1_IN12, ADC2_IN12, ADC3_IN12, ETH_TXD2, I2S2_ext_SD, SPI2_MISO, USB_OTG_HS_ULPI_DIR</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC3</td>
|
|
<td>ADC1_IN13, ADC2_IN13, ADC3_IN13, ETH_TX_CLK, I2S2_SD, SPI2_MOSI, USB_OTG_HS_ULPI_NXT</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC4</td>
|
|
<td>ADC1_IN14, ADC2_IN14, ETH_RXD0</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC5</td>
|
|
<td>ADC1_IN15, ADC2_IN15, ETH_RXD1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC6</td>
|
|
<td>DCMI_D0, I2S2_MCK, SDIO_D6, TIM3_CH1, TIM8_CH1, USART6_TX</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC7</td>
|
|
<td>DCMI_D1, I2S3_MCK, SDIO_D7, TIM3_CH2, TIM8_CH2, USART6_RX</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC8</td>
|
|
<td>DCMI_D2, SDIO_D0, TIM3_CH3, TIM8_CH3, USART6_CK</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC9</td>
|
|
<td>DCMI_D3, I2C3_SDA, I2S_CKIN, RCC_MCO_2, SDIO_D1, TIM3_CH4, TIM8_CH4</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC10</td>
|
|
<td>DCMI_D8, I2S3_CK, SDIO_D2, SPI3_SCK, UART4_TX, USART3_TX</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC11</td>
|
|
<td>DCMI_D4, I2S3_ext_SD, SDIO_D3, SPI3_MISO, UART4_RX, USART3_RX</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC12</td>
|
|
<td>DCMI_D9, I2S3_SD, SDIO_CK, SPI3_MOSI, UART5_TX, USART3_CK</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC13</td>
|
|
<td>RTC_AF1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC14</td>
|
|
<td>RCC_OSC32_IN</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PC15</td>
|
|
<td>ADC1_EXTI15, ADC2_EXTI15, ADC3_EXTI15, RCC_OSC32_OUT</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD0</td>
|
|
<td>CAN1_RX, FSMC_D2, FSMC_DA2</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD1</td>
|
|
<td>CAN1_TX, FSMC_D3, FSMC_DA3</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD2</td>
|
|
<td>DCMI_D11, SDIO_CMD, TIM3_ETR, UART5_RX</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD3</td>
|
|
<td>FSMC_CLK, USART2_CTS</td>
|
|
<td><strong>LED_BUILTIN2</strong></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD4</td>
|
|
<td>FSMC_NOE, USART2_RTS</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD5</td>
|
|
<td>FSMC_NWE, USART2_TX</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD6</td>
|
|
<td>FSMC_NWAIT, USART2_RX</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD7</td>
|
|
<td>FSMC_NCE2, FSMC_NE1, USART2_CK</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD8</td>
|
|
<td>FSMC_D13, FSMC_DA13, USART3_TX</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD9</td>
|
|
<td>FSMC_D14, FSMC_DA14, USART3_RX</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD10</td>
|
|
<td>FSMC_D15, FSMC_DA15, USART3_CK</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD11</td>
|
|
<td>FSMC_A16, FSMC_CLE, USART3_CTS</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD12</td>
|
|
<td>FSMC_A17, FSMC_ALE, TIM4_CH1, USART3_RTS</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD13</td>
|
|
<td>FSMC_A18, TIM4_CH2</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD14</td>
|
|
<td>FSMC_D0, FSMC_DA0, TIM4_CH3</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PD15</td>
|
|
<td>FSMC_D1, FSMC_DA1, TIM4_CH4</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PDR_ON</td>
|
|
<td></td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE0</td>
|
|
<td>DCMI_D2, FSMC_NBL0, TIM4_ETR</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE1</td>
|
|
<td>DCMI_D3, FSMC_NBL1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE2</td>
|
|
<td>ETH_TXD3, FSMC_A23, SYS_TRACECLK</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE3</td>
|
|
<td>FSMC_A19, SYS_TRACED0</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE4</td>
|
|
<td>DCMI_D4, FSMC_A20, SYS_TRACED1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE5</td>
|
|
<td>DCMI_D6, FSMC_A21, SYS_TRACED2, TIM9_CH1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE6</td>
|
|
<td>DCMI_D7, FSMC_A22, SYS_TRACED3, TIM9_CH2</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE7</td>
|
|
<td>FSMC_D4, FSMC_DA4, TIM1_ETR</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE8</td>
|
|
<td>FSMC_D5, FSMC_DA5, TIM1_CH1N</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE9</td>
|
|
<td>FSMC_D6, FSMC_DA6, TIM1_CH1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE10</td>
|
|
<td>FSMC_D7, FSMC_DA7, TIM1_CH2N</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE11</td>
|
|
<td>FSMC_D8, FSMC_DA8, TIM1_CH2</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE12</td>
|
|
<td>FSMC_D9, FSMC_DA9, TIM1_CH3N</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE13</td>
|
|
<td>FSMC_D10, FSMC_DA10, TIM1_CH3</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE14</td>
|
|
<td>FSMC_D11, FSMC_DA11, TIM1_CH4</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PE15</td>
|
|
<td>FSMC_D12, FSMC_DA12, TIM1_BKIN</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF0</td>
|
|
<td>FSMC_A0, I2C2_SDA</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF1</td>
|
|
<td>FSMC_A1, I2C2_SCL</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF2</td>
|
|
<td>FSMC_A2, I2C2_SMBA</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF3</td>
|
|
<td>ADC3_IN9, FSMC_A3</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF4</td>
|
|
<td>ADC3_IN14, FSMC_A4</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF5</td>
|
|
<td>ADC3_IN15, FSMC_A5</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF6</td>
|
|
<td>ADC3_IN4, FSMC_NIORD, TIM10_CH1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF7</td>
|
|
<td>ADC3_IN5, FSMC_NREG, TIM11_CH1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF8</td>
|
|
<td>ADC3_IN6, FSMC_NIOWR, TIM13_CH1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF9</td>
|
|
<td>ADC3_IN7, DAC_EXTI9, FSMC_CD, TIM14_CH1</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF10</td>
|
|
<td>ADC3_IN8, FSMC_INTR</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF11</td>
|
|
<td>ADC1_EXTI11, ADC2_EXTI11, ADC3_EXTI11, DCMI_D12</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF12</td>
|
|
<td>FSMC_A6</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF13</td>
|
|
<td>FSMC_A7</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF14</td>
|
|
<td>FSMC_A8</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PF15</td>
|
|
<td>FSMC_A9</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG0</td>
|
|
<td>FSMC_A10</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG1</td>
|
|
<td>FSMC_A11</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG2</td>
|
|
<td>FSMC_A12</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG3</td>
|
|
<td>FSMC_A13</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG4</td>
|
|
<td>FSMC_A14</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG5</td>
|
|
<td>FSMC_A15</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG6</td>
|
|
<td>FSMC_INT2</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG7</td>
|
|
<td>FSMC_INT3, USART6_CK</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG8</td>
|
|
<td>ETH_PPS_OUT, USART6_RTS</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG9</td>
|
|
<td>FSMC_NCE3, FSMC_NE2, USART6_RX</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG10</td>
|
|
<td>FSMC_NCE4_1, FSMC_NE3</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG11</td>
|
|
<td>ETH_TX_EN, FSMC_NCE4_2</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG12</td>
|
|
<td>FSMC_NE4, USART6_RTS</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG13</td>
|
|
<td>ETH_TXD0, FSMC_A24, USART6_CTS</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG14</td>
|
|
<td>ETH_TXD1, FSMC_A25, USART6_TX</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PG15</td>
|
|
<td>DCMI_D13, USART6_CTS</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PH0</td>
|
|
<td>RCC_OSC_IN</td>
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td>PH1</td>
|
|
<td>RCC_OSC_OUT</td>
|
|
<td></td>
|
|
</tr>
|
|
</tbody>
|
|
</table></div>
|
|
</div>
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