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Cleanedup sram backup as EEPROM

This commit is contained in:
hoogendijkta 2019-02-20 17:29:35 +01:00
parent 7863cc1eef
commit 1ee21e7555
1 changed files with 17 additions and 17 deletions
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34
speeduino/src/BackupSram/BackupSramAsEEPROM.cpp
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@ -1,7 +1,22 @@
#if defined(ARDUINO_BLACK_F407VE)
#include "BackupSramAsEEPROM.h"
BackupSramAsEEPROM::BackupSramAsEEPROM(){}
BackupSramAsEEPROM::BackupSramAsEEPROM(){
//Enable the power interface clock
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
//Enable the backup SRAM clock by setting BKPSRAMEN bit i
RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
/** enable the backup regulator (used to maintain the backup SRAM content in
* standby and Vbat modes). NOTE : this bit is not reset when the device
* wakes up from standby, system reset or power reset. You can check that
* the backup regulator is ready on PWR->CSR.brr, see rm p144 */
//enable backup power regulator this makes sram backup posible. bit is not reset by software!
PWR->CSR |= PWR_CSR_BRE;
}
int8_t BackupSramAsEEPROM::write_byte( uint8_t *data, uint16_t bytes, uint16_t offset ) {
uint8_t* base_addr = (uint8_t *) BKPSRAM_BASE;
uint16_t i;
@ -10,23 +25,10 @@
return -1;
}
//Enable the power interface clock
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
//Enable the backup SRAM clock by setting BKPSRAMEN bit i
RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
/* disable backup domain write protection */
//Set the Disable Backup Domain write protection (DBP) bit in PWR power control register
PWR->CR |= PWR_CR_DBP;
/** enable the backup regulator (used to maintain the backup SRAM content in
* standby and Vbat modes). NOTE : this bit is not reset when the device
* wakes up from standby, system reset or power reset. You can check that
* the backup regulator is ready on PWR->CSR.brr, see rm p144 */
//enable backup power regulator this makes sram backup posible. bit is not reset by software!
PWR->CSR |= PWR_CSR_BRE;
for( i = 0; i < bytes; i++ ) {
*(base_addr + offset + i) = *(data + i);
}
@ -43,8 +45,6 @@
/* ERROR : the last byte is outside the backup SRAM region */
return -1;
}
//Enable the backup SRAM clock by setting BKPSRAMEN bit i
RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
for( i = 0; i < bytes; i++ ) {
*(data + i) = *(base_addr + offset + i);