Fix 2.0.0 STM32 core and F1 support (#587)
This commit is contained in:
Pasi Kemppainen
GitHub
parent
74656300ca
commit
1f8b8eb486
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@ -348,15 +348,29 @@ void STM32_CAN::setBaudRate(uint32_t baud)
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{
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CAN1->BTR &= ~(((0x03) << 24) | ((0x07) << 20) | ((0x0F) << 16) | (0x1FF));
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CAN1->BTR |= (((can_configs[bitrate].TS2-1) & 0x07) << 20) | (((can_configs[bitrate].TS1-1) & 0x0F) << 16) | ((can_configs[bitrate].BRP-1) & 0x1FF);
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}
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#if defined(CAN2)
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else if (_channel == _CAN2)
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{
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CAN2->BTR &= ~(((0x03) << 24) | ((0x07) << 20) | ((0x0F) << 16) | (0x1FF));
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CAN2->BTR |= (((can_configs[bitrate].TS2-1) & 0x07) << 20) | (((can_configs[bitrate].TS1-1) & 0x0F) << 16) | ((can_configs[bitrate].BRP-1) & 0x1FF);
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}
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#endif
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// Configure Filters to default values
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CAN1->FMR |= 0x1UL; // Set to filter initialization mode
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CAN1->FMR &= 0xFFFFC0FF; // Clear CAN2 start bank
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// bxCAN has 28 filters.
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// These filters are used for both CAN1 and CAN2.
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// STM32F405 has CAN1 and CAN2, so CAN2 filters are offset by 14
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#if defined(STM32F1xx)
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// STM32F1xx has only CAN1, so all 28 are used for CAN1
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CAN1->FMR |= 0x1C << 8; // Assign all filters to CAN1
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#elif defined(STM32F4xx)
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// STM32F4xx has CAN1 and CAN2, so CAN2 filters are offset by 14
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CAN1->FMR |= 0xE00; // Start bank for the CAN2 interface
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#endif
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// Set filter 0
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// Single 32-bit scale configuration
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@ -371,36 +385,6 @@ void STM32_CAN::setBaudRate(uint32_t baud)
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// Filter assigned to FIFO 0
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// Filter bank register to all 0
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CANSetFilter(14, 1, 0, 0, 0x0UL, 0x0UL);
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}
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#if defined(CAN2)
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else if (_channel == _CAN2)
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{
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CAN2->BTR &= ~(((0x03) << 24) | ((0x07) << 20) | ((0x0F) << 16) | (0x1FF));
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CAN2->BTR |= (((can_configs[bitrate].TS2-1) & 0x07) << 20) | (((can_configs[bitrate].TS1-1) & 0x0F) << 16) | ((can_configs[bitrate].BRP-1) & 0x1FF);
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// Configure Filters to default values
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CAN2->FMR |= 0x1UL; // Set to filter initialization mode
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CAN2->FMR &= 0xFFFFC0FF; // Clear CAN2 start bank
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// bxCAN has 28 filters.
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// These filters are used for both CAN1 and CAN2.
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// STM32F405 has CAN1 and CAN2, so CAN2 filters are offset by 14
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CAN2->FMR |= 0xE00; // Start bank for the CAN2 interface
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// Set filter 0
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// Single 32-bit scale configuration
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// Two 32-bit registers of filter bank x are in Identifier Mask mode
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// Filter assigned to FIFO 0
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// Filter bank register to all 0
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CANSetFilter(0, 1, 0, 0, 0x0UL, 0x0UL);
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// Set filter 14
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// Single 32-bit scale configuration
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// Two 32-bit registers of filter bank x are in Identifier Mask mode
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// Filter assigned to FIFO 0
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// Filter bank register to all 0
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CANSetFilter(14, 1, 0, 0, 0x0UL, 0x0UL);
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}
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#endif
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if (_channel == _CAN1)
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{
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@ -439,14 +423,17 @@ void STM32_CAN::SetTXRX()
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CANSetGpio(GPIOB, 8); // Set PB8
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}
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//PA11/PA12 are second alternative pins, but it can't be used if native USB connection is in use.
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if (_pins == ALT2) {
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if (_pins == ALT_2) {
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RCC->AHB1ENR |= 0x1; // Enable GPIOA clock
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CANSetGpio(GPIOA, 12); // Set PA12
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CANSetGpio(GPIOA, 11); // Set PA11
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}
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#elif defined(STM32F1xx)
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RCC->APB2ENR |= 0x1UL;
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AFIO->MAPR &= 0xFFFF9FFF; // reset CAN remap
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//PA11/PA12 as default, because those are only ones available on all F1 models.
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if (_pins == DEF) {
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RCC->APB2ENR |= 0x4UL; // Enable GPIOA clock
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AFIO->MAPR &= 0xFFFF9FFF; // reset CAN remap
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// CAN_RX mapped to PA11, CAN_TX mapped to PA12
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GPIOA->CRH &= ~(0xFF000UL); // Configure PA12(0b0000) and PA11(0b0000)
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@ -485,6 +472,26 @@ void STM32_CAN::SetTXRX()
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GPIOB->ODR |= 0x1UL << 8; // PB8 Upll-up
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}
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if (_pins == ALT_2) {
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AFIO->MAPR |= 0x00005000; // set CAN remap
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// CAN_RX mapped to PD0, CAN_TX mapped to PD1 (available on 100-pin and 144-pin package)
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RCC->APB2ENR |= 0x20UL; // Enable GPIOD clock
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GPIOD->CRL &= ~(0xFFUL); // Configure PD1(0b0000) and PD0(0b0000)
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// 0b0000
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// MODE=00(Input mode)
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// CNF=00(Analog mode)
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GPIOD->CRH |= 0xB8UL; // Configure PD1(0b1011) and PD0(0b1000)
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// 0b1000
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// MODE=00(Input mode)
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// CNF=10(Input with pull-up / pull-down)
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// 0b1011
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// MODE=11(Output mode, max speed 50 MHz)
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// CNF=10(Alternate function output Push-pull
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GPIOD->ODR |= 0x1UL << 0; // PD0 Upll-up
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}
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#endif
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}
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#if defined(CAN2)
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@ -9,7 +9,7 @@ https://github.com/nopnop2002/Arduino-STM32-CAN
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#ifndef STM32_CAN_H
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#define STM32_CAN_H
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#if defined(STM32F407xx) || defined(STM32F103xB) || defined(STM32F405xx)
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#if defined(STM32F407xx) || defined(STM32F1xx) || defined(STM32F405xx)
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#include <Arduino.h>
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#define STM32_CAN_TIR_TXRQ (1U << 0U) // Bit 0: Transmit Mailbox Request
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@ -48,7 +48,7 @@ typedef const struct
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uint8_t BRP;
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} CAN_bit_timing_config_t;
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typedef enum CAN_PINS {DEF, ALT, ALT2,} CAN_PINS;
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typedef enum CAN_PINS {DEF, ALT, ALT_2,} CAN_PINS;
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//STM32 has only 3 TX mailboxes
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typedef enum CAN_MAILBOX {
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