Clean compile on Teensy 4
This commit is contained in:
Josh Stewart
parent
bc60059445
commit
4357b1b4cf
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@ -385,7 +385,7 @@ void boostDisable()
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}
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}
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#if defined(CORE_TEENSY)
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#if defined(CORE_TEENSY35)
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void ftm1_isr(void)
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{
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//FTM1 only has 2 compare channels
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@ -397,4 +397,6 @@ void ftm1_isr(void)
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else if(interrupt2) { FTM1_C1SC &= ~FTM_CSC_CHF; vvtInterrupt(); }
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}
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#elif defined(CORE_TEENSY40)
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//DO STUFF HERE
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#endif
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@ -11,6 +11,8 @@
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*/
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#define PORT_TYPE uint8_t //Size of the port variables (Eg inj1_pin_port).
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#define PINMASK_TYPE uint8_t
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#define COMPARE_TYPE uint16_t
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#define COUNTER_TYPE uint16_t
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#define EEPROM_LIB_H <EEPROM.h>
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void initBoard();
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uint16_t freeRam();
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@ -8,6 +8,8 @@
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*/
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#define PORT_TYPE uint32_t
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#define PINMASK_TYPE uint32_t
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#define COMPARE_TYPE uint16_t
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#define COUNTER_TYPE uint16_t
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#define micros_safe() micros() //timer5 method is not used on anything but AVR, the micros_safe() macro is simply an alias for the normal micros()
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#ifndef USE_SERIAL3
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#define USE_SERIAL3
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@ -10,6 +10,8 @@
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*/
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#define PORT_TYPE uint32_t
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#define PINMASK_TYPE uint32_t
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#define COMPARE_TYPE uint16_t
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#define COUNTER_TYPE uint16_t
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#define micros_safe() micros() //timer5 method is not used on anything but AVR, the micros_safe() macro is simply an alias for the normal micros()
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#if defined(SRAM_AS_EEPROM)
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#define EEPROM_LIB_H "src/BackupSram/BackupSramAsEEPROM.h"
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@ -10,6 +10,8 @@
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uint16_t freeRam();
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#define PORT_TYPE uint8_t //Size of the port variables
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#define PINMASK_TYPE uint8_t
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#define COMPARE_TYPE uint16_t
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#define COUNTER_TYPE uint16_t
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#define BOARD_DIGITAL_GPIO_PINS 34
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#define BOARD_NR_GPIO_PINS 34
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#define USE_SERIAL3
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@ -0,0 +1,142 @@
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#ifndef TEENSY40_H
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#define TEENSY40_H
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#if defined(CORE_TEENSY)&& defined(__IMXRT1062__)
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/*
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***********************************************************************************************************
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* General
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*/
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void initBoard();
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uint16_t freeRam();
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#define PORT_TYPE uint32_t //Size of the port variables
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#define PINMASK_TYPE uint32_t
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#define COMPARE_TYPE uint32_t
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#define COUNTER_TYPE uint32_t
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#define BOARD_DIGITAL_GPIO_PINS 34
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#define BOARD_NR_GPIO_PINS 34
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#define USE_SERIAL3
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#define EEPROM_LIB_H <EEPROM.h>
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#define micros_safe() micros() //timer5 method is not used on anything but AVR, the micros_safe() macro is simply an alias for the normal micros()
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/*
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***********************************************************************************************************
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* Schedules
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*/
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//http://shawnhymel.com/661/learning-the-teensy-lc-interrupt-service-routines/
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#define FUEL1_COUNTER TMR1_CNTR0
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#define FUEL2_COUNTER TMR1_CNTR0
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#define FUEL3_COUNTER TMR1_CNTR1
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#define FUEL4_COUNTER TMR1_CNTR1
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#define FUEL5_COUNTER TMR1_CNTR2
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#define FUEL6_COUNTER TMR1_CNTR2
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#define FUEL7_COUNTER TMR1_CNTR3
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#define FUEL8_COUNTER TMR1_CNTR3
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#define IGN1_COUNTER TMR2_CNTR0
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#define IGN2_COUNTER TMR2_CNTR0
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#define IGN3_COUNTER TMR2_CNTR1
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#define IGN4_COUNTER TMR2_CNTR1
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#define IGN5_COUNTER TMR2_CNTR2
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#define IGN6_COUNTER TMR2_CNTR2
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#define IGN7_COUNTER TMR2_CNTR3
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#define IGN8_COUNTER TMR2_CNTR3
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#define FUEL1_COMPARE TMR1_COMP10
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#define FUEL2_COMPARE TMR1_COMP20
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#define FUEL3_COMPARE TMR1_COMP11
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#define FUEL4_COMPARE TMR1_COMP21
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#define FUEL5_COMPARE TMR1_COMP12
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#define FUEL6_COMPARE TMR1_COMP22
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#define FUEL7_COMPARE TMR1_COMP13
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#define FUEL8_COMPARE TMR1_COMP23
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#define IGN1_COMPARE TMR2_COMP10
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#define IGN2_COMPARE TMR2_COMP20
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#define IGN3_COMPARE TMR2_COMP11
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#define IGN4_COMPARE TMR2_COMP21
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#define IGN5_COMPARE TMR2_COMP12
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#define IGN6_COMPARE TMR2_COMP22
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#define IGN7_COMPARE TMR2_COMP13
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#define IGN8_COMPARE TMR2_COMP23
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#define FUEL1_TIMER_ENABLE() TMR1_CSCTRL0 |= TMR_CSCTRL_TCF1EN //Write 1 to the TCFIE (Channel Interrupt Enable) bit of channel 0 Status/Control
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#define FUEL2_TIMER_ENABLE() TMR1_CSCTRL0 |= TMR_CSCTRL_TCF2EN
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#define FUEL3_TIMER_ENABLE() TMR1_CSCTRL1 |= TMR_CSCTRL_TCF1EN
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#define FUEL4_TIMER_ENABLE() TMR1_CSCTRL1 |= TMR_CSCTRL_TCF2EN
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#define FUEL5_TIMER_ENABLE() TMR1_CSCTRL2 |= TMR_CSCTRL_TCF1EN
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#define FUEL6_TIMER_ENABLE() TMR1_CSCTRL2 |= TMR_CSCTRL_TCF2EN
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#define FUEL7_TIMER_ENABLE() TMR1_CSCTRL3 |= TMR_CSCTRL_TCF1EN
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#define FUEL8_TIMER_ENABLE() TMR1_CSCTRL3 |= TMR_CSCTRL_TCF2EN
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#define FUEL1_TIMER_DISABLE() TMR1_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN //Write 0 to the CHIE (Channel Interrupt Enable) bit of channel 0 Status/Control
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#define FUEL2_TIMER_DISABLE() TMR1_CSCTRL0 &= ~TMR_CSCTRL_TCF2EN
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#define FUEL3_TIMER_DISABLE() TMR1_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN
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#define FUEL4_TIMER_DISABLE() TMR1_CSCTRL1 &= ~TMR_CSCTRL_TCF2EN
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#define FUEL5_TIMER_DISABLE() TMR1_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN
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#define FUEL6_TIMER_DISABLE() TMR1_CSCTRL2 &= ~TMR_CSCTRL_TCF2EN
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#define FUEL7_TIMER_DISABLE() TMR1_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN
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#define FUEL8_TIMER_DISABLE() TMR1_CSCTRL3 &= ~TMR_CSCTRL_TCF2EN
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#define IGN1_TIMER_ENABLE() TMR2_CSCTRL0 |= TMR_CSCTRL_TCF1EN //Write 1 to the TCFIE (Channel Interrupt Enable) bit of channel 0 Status/Control
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#define IGN2_TIMER_ENABLE() TMR2_CSCTRL0 |= TMR_CSCTRL_TCF2EN
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#define IGN3_TIMER_ENABLE() TMR2_CSCTRL1 |= TMR_CSCTRL_TCF1EN
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#define IGN4_TIMER_ENABLE() TMR2_CSCTRL1 |= TMR_CSCTRL_TCF2EN
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#define IGN5_TIMER_ENABLE() TMR2_CSCTRL2 |= TMR_CSCTRL_TCF1EN
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#define IGN6_TIMER_ENABLE() TMR2_CSCTRL2 |= TMR_CSCTRL_TCF2EN
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#define IGN7_TIMER_ENABLE() TMR2_CSCTRL3 |= TMR_CSCTRL_TCF1EN
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#define IGN8_TIMER_ENABLE() TMR2_CSCTRL3 |= TMR_CSCTRL_TCF2EN
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#define IGN1_TIMER_DISABLE() TMR2_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN //Write 0 to the CHIE (Channel Interrupt Enable) bit of channel 0 Status/Control
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#define IGN2_TIMER_DISABLE() TMR2_CSCTRL0 &= ~TMR_CSCTRL_TCF2EN
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#define IGN3_TIMER_DISABLE() TMR2_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN
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#define IGN4_TIMER_DISABLE() TMR2_CSCTRL1 &= ~TMR_CSCTRL_TCF2EN
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#define IGN5_TIMER_DISABLE() TMR2_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN
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#define IGN6_TIMER_DISABLE() TMR2_CSCTRL2 &= ~TMR_CSCTRL_TCF2EN
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#define IGN7_TIMER_DISABLE() TMR2_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN
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#define IGN8_TIMER_DISABLE() TMR2_CSCTRL3 &= ~TMR_CSCTRL_TCF2EN
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#define MAX_TIMER_PERIOD 139808 // 2.13333333uS * 65535
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#define MAX_TIMER_PERIOD_SLOW 139808
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#define uS_TO_TIMER_COMPARE(uS) ((uS * 15) >> 5) //Converts a given number of uS into the required number of timer ticks until that time has passed.
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//Hack compatibility with AVR timers that run at different speeds
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#define uS_TO_TIMER_COMPARE_SLOW(uS) ((uS * 15) >> 5)
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/*
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***********************************************************************************************************
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* Auxilliaries
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*/
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#define ENABLE_BOOST_TIMER() TMR3_CSCTRL0 |= TMR_CSCTRL_TCF1EN
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#define DISABLE_BOOST_TIMER() TMR3_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN
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#define ENABLE_VVT_TIMER() TMR3_CSCTRL0 |= TMR_CSCTRL_TCF2EN
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#define DISABLE_VVT_TIMER() TMR3_CSCTRL0 &= ~TMR_CSCTRL_TCF2EN
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#define BOOST_TIMER_COMPARE TMR3_COMP10
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#define BOOST_TIMER_COUNTER TMR3_CNTR0
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#define VVT_TIMER_COMPARE TMR3_COMP20
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#define VVT_TIMER_COUNTER TMR3_CNTR0
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static inline void boostInterrupt();
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static inline void vvtInterrupt();
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/*
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***********************************************************************************************************
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* Idle
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*/
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#define IDLE_COUNTER TMR3_CNTR1
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#define IDLE_COMPARE TMR3_COMP21
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#define IDLE_TIMER_ENABLE() TMR3_CSCTRL1 |= TMR_CSCTRL_TCF1EN
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#define IDLE_TIMER_DISABLE() TMR3_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN
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static inline void idleInterrupt();
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/*
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***********************************************************************************************************
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* CAN / Second serial
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*/
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//Uart CANSerial (&sercom3, 0, 1, SERCOM_RX_PAD_1, UART_TX_PAD_0);
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#endif //CORE_TEENSY
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#endif //TEENSY40_H
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@ -0,0 +1,269 @@
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#if defined(CORE_TEENSY) && defined(__IMXRT1062__)
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#include "board_teensy40.h"
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#include "globals.h"
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#include "auxiliaries.h"
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#include "idle.h"
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#include "scheduler.h"
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void initBoard()
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{
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/*
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***********************************************************************************************************
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* General
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*/
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/*
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***********************************************************************************************************
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* Idle
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*/
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if( (configPage6.iacAlgorithm == IAC_ALGORITHM_PWM_OL) || (configPage6.iacAlgorithm == IAC_ALGORITHM_PWM_CL) )
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{
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//FlexTimer 2, compare channel 0 is used for idle
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/*
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FTM2_MODE |= FTM_MODE_WPDIS; // Write Protection Disable
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FTM2_MODE |= FTM_MODE_FTMEN; //Flex Timer module enable
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FTM2_MODE |= FTM_MODE_INIT;
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FTM2_SC = 0x00; // Set this to zero before changing the modulus
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FTM2_CNTIN = 0x0000; //Shouldn't be needed, but just in case
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FTM2_CNT = 0x0000; // Reset the count to zero
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FTM2_MOD = 0xFFFF; // max modulus = 65535*/
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/*
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* Enable the clock for FTM0/1
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* 00 No clock selected. Disables the FTM counter.
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* 01 System clock
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* 10 Fixed frequency clock (32kHz)
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* 11 External clock
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*/
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//FTM2_SC |= FTM_SC_CLKS(0b10);
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/*
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* Trim the slow clock from 32kHz down to 31.25kHz (The slowest it will go)
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* This is somewhat imprecise and documentation is not good.
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* I poked the chip until I figured out the values associated with 31.25kHz
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*/
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//MCG_C3 = 0x9B;
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/*
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* Set Prescaler
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* This is the slowest that the timer can be clocked (Without used the slow timer, which is too slow). It results in ticks of 2.13333uS on the teensy 3.5:
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* 32000 Hz = F_BUS
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* 128 * 1000000uS / F_BUS = 2.133uS
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*
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* 000 = Divide by 1
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* 001 Divide by 2
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* 010 Divide by 4
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* 011 Divide by 8
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* 100 Divide by 16
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* 101 Divide by 32
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* 110 Divide by 64
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* 111 Divide by 128
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*/
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/*
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FTM2_SC |= FTM_SC_PS(0b0); //No prescaler
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//Setup the channels (See Pg 1014 of K64 DS).
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FTM2_C0SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM2_C0SC |= FTM_CSC_MSA; //Enable Compare mode
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//The below enables channel compare interrupt, but this is done in idleControl()
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//FTM2_C0SC |= FTM_CSC_CHIE;
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FTM2_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM2_C1SC |= FTM_CSC_MSA; //Enable Compare mode
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//Enable channel compare interrupt (This is currently disabled as not in use)
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//FTM2_C1SC |= FTM_CSC_CHIE;
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FTM2_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM2_C1SC |= FTM_CSC_MSA; //Enable Compare mode
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//Enable channel compare interrupt (This is currently disabled as not in use)
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//FTM2_C1SC |= FTM_CSC_CHIE;
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//Enable IRQ Interrupt
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NVIC_ENABLE_IRQ(IRQ_FTM2);
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*/
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}
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/*
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***********************************************************************************************************
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* Timers
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*/
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//Uses the PIT timer on Teensy.
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lowResTimer.begin(oneMSInterval, 1000);
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/*
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***********************************************************************************************************
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* Auxilliaries
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*/
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/*
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//FlexTimer 1 is used for boost and VVT. There are 8 channels on this module
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FTM1_MODE |= FTM_MODE_WPDIS; // Write Protection Disable
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FTM1_MODE |= FTM_MODE_FTMEN; //Flex Timer module enable
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FTM1_MODE |= FTM_MODE_INIT;
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FTM1_SC |= FTM_SC_CLKS(0b1); // Set internal clocked
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FTM1_SC |= FTM_SC_PS(0b111); //Set prescaler to 128 (2.1333uS tick time)
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//Enable each compare channel individually
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FTM1_C0SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM1_C0SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM1_C0SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM1_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM1_C1SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM1_C1SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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//NVIC_ENABLE_IRQ(IRQ_FTM1);
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*/
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//2uS resolution Min 8Hz, Max 5KHz
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boost_pwm_max_count = 1000000L / (2 * configPage6.boostFreq * 2); //Converts the frequency in Hz to the number of ticks (at 2uS) it takes to complete 1 cycle. The x2 is there because the frequency is stored at half value (in a byte) to allow freqneucies up to 511Hz
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vvt_pwm_max_count = 1000000L / (2 * configPage6.vvtFreq * 2); //Converts the frequency in Hz to the number of ticks (at 2uS) it takes to complete 1 cycle
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/*
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***********************************************************************************************************
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* Schedules
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*/
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/*
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//FlexTimer 0 is used for 4 ignition and 4 injection schedules. There are 8 channels on this module, so no other timers are needed
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FTM0_MODE |= FTM_MODE_WPDIS; //Write Protection Disable
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FTM0_MODE |= FTM_MODE_FTMEN; //Flex Timer module enable
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FTM0_MODE |= FTM_MODE_INIT;
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FTM0_SC = 0x00; // Set this to zero before changing the modulus
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FTM0_CNTIN = 0x0000; //Shouldn't be needed, but just in case
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FTM0_CNT = 0x0000; //Reset the count to zero
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FTM0_MOD = 0xFFFF; //max modulus = 65535
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//FlexTimer 3 is used for schedules on channel 5+. Currently only channel 5 is used, but will likely be expanded later
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FTM3_MODE |= FTM_MODE_WPDIS; //Write Protection Disable
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FTM3_MODE |= FTM_MODE_FTMEN; //Flex Timer module enable
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FTM3_MODE |= FTM_MODE_INIT;
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FTM3_SC = 0x00; // Set this to zero before changing the modulus
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FTM3_CNTIN = 0x0000; //Shouldn't be needed, but just in case
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FTM3_CNT = 0x0000; //Reset the count to zero
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FTM3_MOD = 0xFFFF; //max modulus = 65535
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*/
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/*
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* Enable the clock for FTM0/1
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* 00 No clock selected. Disables the FTM counter.
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* 01 System clock
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* 10 Fixed frequency clock
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* 11 External clock
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*/
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//FTM0_SC |= FTM_SC_CLKS(0b1);
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//FTM3_SC |= FTM_SC_CLKS(0b1);
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/*
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* Set Prescaler
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* This is the slowest that the timer can be clocked (Without used the slow timer, which is too slow). It results in ticks of 2.13333uS on the teensy 3.5:
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* 60000000 Hz = F_BUS
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* 128 * 1000000uS / F_BUS = 2.133uS
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*
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* 000 = Divide by 1
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* 001 Divide by 2
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* 010 Divide by 4
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* 011 Divide by 8
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* 100 Divide by 16
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* 101 Divide by 32
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* 110 Divide by 64
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* 111 Divide by 128
|
||||
*/
|
||||
//FTM0_SC |= FTM_SC_PS(0b111);
|
||||
//FTM3_SC |= FTM_SC_PS(0b111);
|
||||
|
||||
//Setup the channels (See Pg 1014 of K64 DS).
|
||||
//The are probably not needed as power on state should be 0
|
||||
/*
|
||||
FTM0_C0SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM0_C0SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM0_C0SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM0_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM0_C1SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM0_C1SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM0_C2SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM0_C2SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM0_C2SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM0_C3SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM0_C3SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM0_C3SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM0_C4SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM0_C4SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM0_C4SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM0_C5SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM0_C5SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM0_C5SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM0_C6SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM0_C6SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM0_C6SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM0_C7SC &= ~FTM_CSC_MSB; //According to Pg 965 of the datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM0_C7SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM0_C7SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
//Do the same, but on flex timer 3 (Used for channels 5-8)
|
||||
FTM3_C0SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM3_C0SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM3_C0SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM3_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM3_C1SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM3_C1SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM3_C2SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM3_C2SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM3_C2SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM3_C3SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM3_C3SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM3_C3SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM3_C4SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM3_C4SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM3_C4SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM3_C5SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM3_C5SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM3_C5SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM3_C6SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM3_C6SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM3_C6SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
FTM3_C7SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
|
||||
FTM3_C7SC |= FTM_CSC_MSA; //Enable Compare mode
|
||||
FTM3_C7SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
|
||||
|
||||
// enable IRQ Interrupt
|
||||
NVIC_ENABLE_IRQ(IRQ_FTM0);
|
||||
NVIC_ENABLE_IRQ(IRQ_FTM1);
|
||||
*/
|
||||
}
|
||||
|
||||
uint16_t freeRam()
|
||||
{
|
||||
uint32_t stackTop;
|
||||
uint32_t heapTop;
|
||||
|
||||
// current position of the stack.
|
||||
stackTop = (uint32_t) &stackTop;
|
||||
|
||||
// current position of heap.
|
||||
void* hTop = malloc(1);
|
||||
heapTop = (uint32_t) hTop;
|
||||
free(hTop);
|
||||
|
||||
// The difference is the free, available ram.
|
||||
return (uint16_t)stackTop - heapTop;
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -505,7 +505,7 @@ static inline void idleInterrupt() //Most ARM chips can simply call a function
|
|||
}
|
||||
}
|
||||
|
||||
#if defined(CORE_TEENSY)
|
||||
#if defined(CORE_TEENSY35)
|
||||
void ftm2_isr(void)
|
||||
{
|
||||
//FTM2 only has 2 compare channels
|
||||
|
|
@ -516,4 +516,6 @@ void ftm2_isr(void)
|
|||
if(interrupt1) { FTM2_C0SC &= ~FTM_CSC_CHF; idleInterrupt(); }
|
||||
else if(interrupt2) { FTM2_C1SC &= ~FTM_CSC_CHF; } //Add a callback function here if this is ever used
|
||||
}
|
||||
#elif defined(CORE_TEENSY40)
|
||||
//DO STUFF HERE
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -949,7 +949,7 @@ void setPinMapping(byte boardID)
|
|||
pinFlex = 2; // Flex sensor (Must be external interrupt enabled)
|
||||
pinResetControl = 50; //Reset control output
|
||||
|
||||
#if defined(CORE_TEENSY)
|
||||
#if defined(CORE_TEENSY35)
|
||||
pinTrigger = 23;
|
||||
pinStepperDir = 33;
|
||||
pinStepperStep = 34;
|
||||
|
|
@ -999,7 +999,7 @@ void setPinMapping(byte boardID)
|
|||
pinFlex = 2; // Flex sensor (Must be external interrupt enabled)
|
||||
pinResetControl = 43; //Reset control output
|
||||
|
||||
#if defined(CORE_TEENSY)
|
||||
#if defined(CORE_TEENSY35)
|
||||
pinInjector6 = 51;
|
||||
|
||||
pinTrigger = 23;
|
||||
|
|
@ -1128,7 +1128,7 @@ void setPinMapping(byte boardID)
|
|||
pinResetControl = 39; //Reset control output
|
||||
|
||||
//This is NOT correct. It has not yet been tested with this board
|
||||
#if defined(CORE_TEENSY)
|
||||
#if defined(CORE_TEENSY35)
|
||||
pinTrigger = 23;
|
||||
pinTrigger2 = 36;
|
||||
pinStepperDir = 34;
|
||||
|
|
@ -1178,7 +1178,7 @@ void setPinMapping(byte boardID)
|
|||
pinResetControl = 44; //Reset control output
|
||||
|
||||
//This is NOT correct. It has not yet been tested with this board
|
||||
#if defined(CORE_TEENSY)
|
||||
#if defined(CORE_TEENSY35)
|
||||
pinTrigger = 23;
|
||||
pinTrigger2 = 36;
|
||||
pinStepperDir = 34;
|
||||
|
|
@ -1226,7 +1226,7 @@ void setPinMapping(byte boardID)
|
|||
pinFlex = 3; // Flex sensor (Must be external interrupt enabled)
|
||||
pinResetControl = 44; //Reset control output
|
||||
|
||||
#if defined(CORE_TEENSY)
|
||||
#if defined(CORE_TEENSY35)
|
||||
pinTrigger = 23;
|
||||
pinTrigger2 = 36;
|
||||
pinStepperDir = 34;
|
||||
|
|
@ -1444,7 +1444,8 @@ void setPinMapping(byte boardID)
|
|||
|
||||
case 45:
|
||||
#ifndef SMALL_FLASH_MODE //No support for bluepill here anyway
|
||||
//Pin mappings for the DIY-EFI CORE4 Module
|
||||
//Pin mappings for the DIY-EFI CORE4 Module. This is an AVR only module
|
||||
#if defined(CORE_AVR)
|
||||
pinInjector1 = 10; //Output pin injector 1 is on
|
||||
pinInjector2 = 11; //Output pin injector 2 is on
|
||||
pinInjector3 = 12; //Output pin injector 3 is on
|
||||
|
|
@ -1484,10 +1485,11 @@ void setPinMapping(byte boardID)
|
|||
pinSpareLOut5 = 33; //low current output spare4
|
||||
pinFan = 40; //Pin for the fan output
|
||||
pinResetControl = 46; //Reset control output PLACEHOLDER value for now
|
||||
#endif
|
||||
#endif
|
||||
break;
|
||||
|
||||
#if defined(CORE_TEENSY)
|
||||
#if defined(CORE_TEENSY35)
|
||||
case 50:
|
||||
//Pin mappings as per the teensy rev A shield
|
||||
pinInjector1 = 2; //Output pin injector 1 is on
|
||||
|
|
@ -1772,8 +1774,8 @@ void setPinMapping(byte boardID)
|
|||
}
|
||||
if(configPage10.fuel2Mode == FUEL2_MODE_INPUT_SWITCH)
|
||||
{
|
||||
if (configPage10.fuel2InputPullup == 1) { pinMode(pinfuel2Input, INPUT_PULLUP); } //Normal setting
|
||||
else { pinMode(pinFuel2Input, INPUT); } //inverted setting
|
||||
if (configPage10.fuel2InputPullup == true) { pinMode(pinFuel2Input, INPUT_PULLUP); } //With pullup
|
||||
else { pinMode(pinFuel2Input, INPUT); } //Normal input
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -102,14 +102,14 @@ struct Schedule {
|
|||
void (*StartCallback)(); //Start Callback function for schedule
|
||||
void (*EndCallback)(); //Start Callback function for schedule
|
||||
volatile unsigned long startTime; /**< The system time (in uS) that the schedule started, used by the overdwell protection in timers.ino */
|
||||
volatile uint16_t startCompare; //The counter value of the timer when this will start
|
||||
volatile uint16_t endCompare;
|
||||
volatile COMPARE_TYPE startCompare; //The counter value of the timer when this will start
|
||||
volatile COMPARE_TYPE endCompare;
|
||||
|
||||
unsigned int nextStartCompare;
|
||||
unsigned int nextEndCompare;
|
||||
volatile bool hasNextSchedule = false;
|
||||
volatile bool endScheduleSetByDecoder = false;
|
||||
#if defined(CORE_AVR)
|
||||
#if defined(CORE_AVR) || defined(CORE_TEENSY40)
|
||||
volatile uint16_t * counter;
|
||||
volatile uint16_t * compare;
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -1242,7 +1242,7 @@ static inline void ignitionSchedule8Interrupt() //Most ARM chips can simply call
|
|||
#endif
|
||||
|
||||
|
||||
#if defined(CORE_TEENSY)
|
||||
#if defined(CORE_TEENSY35)
|
||||
void ftm0_isr(void)
|
||||
{
|
||||
//Use separate variables for each test to ensure conversion to bool
|
||||
|
|
|
|||
|
|
@ -38,9 +38,6 @@ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
|||
#include "crankMaths.h"
|
||||
#include "init.h"
|
||||
#include BOARD_H //Note that this is not a real file, it is defined in globals.h.
|
||||
#if defined (CORE_TEENSY)
|
||||
#include <FlexCAN.h>
|
||||
#endif
|
||||
|
||||
void setup()
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue