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Enable ignition channel 5 on Teensy (Prevent compile error)

This commit is contained in:
Josh Stewart 2017-01-11 17:38:59 +11:00
parent 83114b4c76
commit 49e0ba1f65
2 changed files with 23 additions and 1 deletions
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4
scheduler.h
View File

@ -92,6 +92,7 @@ See page 136 of the processors datasheet: http://www.atmel.com/Images/doc2549.pd
#define IGN2_COUNTER FTM0_CNT #define IGN2_COUNTER FTM0_CNT
#define IGN3_COUNTER FTM0_CNT #define IGN3_COUNTER FTM0_CNT
#define IGN4_COUNTER FTM0_CNT #define IGN4_COUNTER FTM0_CNT
#define IGN5_COUNTER FTM1_CNT
#define FUEL1_COMPARE FTM0_C0V #define FUEL1_COMPARE FTM0_C0V
#define FUEL2_COMPARE FTM0_C1V #define FUEL2_COMPARE FTM0_C1V
@ -102,6 +103,7 @@ See page 136 of the processors datasheet: http://www.atmel.com/Images/doc2549.pd
#define IGN2_COMPARE FTM0_C5V #define IGN2_COMPARE FTM0_C5V
#define IGN3_COMPARE FTM0_C6V #define IGN3_COMPARE FTM0_C6V
#define IGN4_COMPARE FTM0_C7V #define IGN4_COMPARE FTM0_C7V
#define IGN5_COMPARE FTM1_C0V
#define FUEL1_TIMER_ENABLE() FTM0_C0SC |= FTM_CSC_CHIE //Write 1 to the CHIE (Channel Interrupt Enable) bit of channel 0 Status/Control #define FUEL1_TIMER_ENABLE() FTM0_C0SC |= FTM_CSC_CHIE //Write 1 to the CHIE (Channel Interrupt Enable) bit of channel 0 Status/Control
#define FUEL2_TIMER_ENABLE() FTM0_C1SC |= FTM_CSC_CHIE #define FUEL2_TIMER_ENABLE() FTM0_C1SC |= FTM_CSC_CHIE
@ -117,11 +119,13 @@ See page 136 of the processors datasheet: http://www.atmel.com/Images/doc2549.pd
#define IGN2_TIMER_ENABLE() FTM0_C5SC |= FTM_CSC_CHIE #define IGN2_TIMER_ENABLE() FTM0_C5SC |= FTM_CSC_CHIE
#define IGN3_TIMER_ENABLE() FTM0_C6SC |= FTM_CSC_CHIE #define IGN3_TIMER_ENABLE() FTM0_C6SC |= FTM_CSC_CHIE
#define IGN4_TIMER_ENABLE() FTM0_C7SC |= FTM_CSC_CHIE #define IGN4_TIMER_ENABLE() FTM0_C7SC |= FTM_CSC_CHIE
#define IGN5_TIMER_ENABLE() FTM1_C0SC |= FTM_CSC_CHIE
#define IGN1_TIMER_DISABLE() FTM0_C4SC &= ~FTM_CSC_CHIE #define IGN1_TIMER_DISABLE() FTM0_C4SC &= ~FTM_CSC_CHIE
#define IGN2_TIMER_DISABLE() FTM0_C5SC &= ~FTM_CSC_CHIE #define IGN2_TIMER_DISABLE() FTM0_C5SC &= ~FTM_CSC_CHIE
#define IGN3_TIMER_DISABLE() FTM0_C6SC &= ~FTM_CSC_CHIE #define IGN3_TIMER_DISABLE() FTM0_C6SC &= ~FTM_CSC_CHIE
#define IGN4_TIMER_DISABLE() FTM0_C7SC &= ~FTM_CSC_CHIE #define IGN4_TIMER_DISABLE() FTM0_C7SC &= ~FTM_CSC_CHIE
#define IGN5_TIMER_DISABLE() FTM1_C0SC &= ~FTM_CSC_CHIE
#define MAX_TIMER_PERIOD 139808 // 2.13333333uS * 65535 #define MAX_TIMER_PERIOD 139808 // 2.13333333uS * 65535
#define uS_TO_TIMER_COMPARE(uS) ((uS * 15) >> 5) //Converts a given number of uS into the required number of timer ticks until that time has passed. #define uS_TO_TIMER_COMPARE(uS) ((uS * 15) >> 5) //Converts a given number of uS into the required number of timer ticks until that time has passed.

20
scheduler.ino
View File

@ -48,14 +48,25 @@ void initialiseSchedulers()
FTM0_CNT = 0x0000; // Reset the count to zero FTM0_CNT = 0x0000; // Reset the count to zero
FTM0_MOD = 0xFFFF; // max modulus = 65535 FTM0_MOD = 0xFFFF; // max modulus = 65535
//FlexTimer 1 is used for schedules on channel 5+. Currently only channel 5 is used, but will likely be expanded later
FTM1_MODE |= FTM_MODE_WPDIS; // Write Protection Disable
FTM1_MODE |= FTM_MODE_FTMEN; //Flex Timer module enable
FTM1_MODE |= FTM_MODE_INIT;
FTM1_SC = 0x00; // Set this to zero before changing the modulus
FTM1_CNTIN = 0x0000; //Shouldn't be needed, but just in case
FTM1_CNT = 0x0000; // Reset the count to zero
FTM1_MOD = 0xFFFF; // max modulus = 65535
/* /*
* Enable the clock for FTM0 * Enable the clock for FTM0/1
* 00 No clock selected. Disables the FTM counter. * 00 No clock selected. Disables the FTM counter.
* 01 System clock * 01 System clock
* 10 Fixed frequency clock * 10 Fixed frequency clock
* 11 External clock * 11 External clock
*/ */
FTM0_SC |= FTM_SC_CLKS(0b1); FTM0_SC |= FTM_SC_CLKS(0b1);
FTM1_SC |= FTM_SC_CLKS(0b1);
/* /*
* Set Prescaler * Set Prescaler
@ -73,6 +84,7 @@ void initialiseSchedulers()
* 111 Divide by 128 * 111 Divide by 128
*/ */
FTM0_SC |= FTM_SC_PS(0b111); FTM0_SC |= FTM_SC_PS(0b111);
FTM1_SC |= FTM_SC_PS(0b111);
//Setup the channels (See Pg 1014 of K64 DS). //Setup the channels (See Pg 1014 of K64 DS).
//FTM0_C0SC &= ~FTM_CSC_ELSB; //Probably not needed as power on state should be 0 //FTM0_C0SC &= ~FTM_CSC_ELSB; //Probably not needed as power on state should be 0
@ -110,8 +122,14 @@ void initialiseSchedulers()
FTM0_C7SC |= FTM_CSC_MSA; //Enable Compare mode FTM0_C7SC |= FTM_CSC_MSA; //Enable Compare mode
FTM0_C7SC |= FTM_CSC_CHIE; //Enable channel compare interrupt FTM0_C7SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
//Do the same, but on flex timer 1 (Used for channels 5+)
FTM1_C0SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
FTM1_C0SC |= FTM_CSC_MSA; //Enable Compare mode
FTM1_C0SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
// enable IRQ Interrupt // enable IRQ Interrupt
NVIC_ENABLE_IRQ(IRQ_FTM0); NVIC_ENABLE_IRQ(IRQ_FTM0);
NVIC_ENABLE_IRQ(IRQ_FTM1);
#endif #endif