teensy35 FTM1 fixes for Boost and VVT controls (#318)
This commit is contained in:
Benas Brazdziunas
GitHub
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89e19d1432
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@ -5,7 +5,6 @@
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#include "idle.h"
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#include "idle.h"
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#include "scheduler.h"
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#include "scheduler.h"
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void initBoard()
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void initBoard()
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{
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{
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/*
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/*
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@ -73,15 +72,83 @@ void initBoard()
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//Enable channel compare interrupt (This is currently disabled as not in use)
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//Enable channel compare interrupt (This is currently disabled as not in use)
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//FTM2_C1SC |= FTM_CSC_CHIE;
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//FTM2_C1SC |= FTM_CSC_CHIE;
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FTM2_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM2_C1SC |= FTM_CSC_MSA; //Enable Compare mode
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//Enable channel compare interrupt (This is currently disabled as not in use)
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//FTM2_C1SC |= FTM_CSC_CHIE;
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//Enable IRQ Interrupt
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//Enable IRQ Interrupt
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NVIC_ENABLE_IRQ(IRQ_FTM2);
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NVIC_ENABLE_IRQ(IRQ_FTM2);
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}
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}
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/*
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***********************************************************************************************************
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* Auxilliaries
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*/
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/*
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***********************************************************************************************************
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* BOOST and VVT
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*/
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if (configPage6.boostEnabled == 1 || configPage6.vvtEnabled == 1)
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{
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//FlexTimer 2, compare channel 0 is used for idle
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FTM1_MODE |= FTM_MODE_WPDIS; // Write Protection Disable
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FTM1_MODE |= FTM_MODE_FTMEN; //Flex Timer module enable
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FTM1_MODE |= FTM_MODE_INIT;
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FTM1_SC = 0x00; // Set this to zero before changing the modulus
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FTM1_CNTIN = 0x0000; //Shouldn't be needed, but just in case
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FTM1_CNT = 0x0000; // Reset the count to zero
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FTM1_MOD = 0xFFFF; // max modulus = 65535
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/*
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* Enable the clock for FTM0/1
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* 00 No clock selected. Disables the FTM counter.
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* 01 System clock
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* 10 Fixed frequency clock (32kHz)
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* 11 External clock
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*/
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FTM1_SC |= FTM_SC_CLKS(0b10);
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/*
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* Trim the slow clock from 32kHz down to 31.25kHz (The slowest it will go)
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* This is somewhat imprecise and documentation is not good.
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* I poked the chip until I figured out the values associated with 31.25kHz
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*/
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MCG_C3 = 0x9B;
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/*
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* Set Prescaler
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* This is the slowest that the timer can be clocked (Without used the slow timer, which is too slow). It results in ticks of 2.13333uS on the teensy 3.5:
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* 32000 Hz = F_BUS
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* 128 * 1000000uS / F_BUS = 2.133uS
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*
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* 000 = Divide by 1
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* 001 Divide by 2
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* 010 Divide by 4
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* 011 Divide by 8
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* 100 Divide by 16
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* 101 Divide by 32
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* 110 Divide by 64
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* 111 Divide by 128
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*/
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FTM2_SC |= FTM_SC_PS(0b0); //No prescaler
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//Setup the channels (See Pg 1014 of K64 DS).
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FTM1_C0SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM1_C0SC |= FTM_CSC_MSA; //Enable Compare mode
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//The below enables channel compare interrupt, but this is done in idleControl()
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//FTM1_C0SC |= FTM_CSC_CHIE;
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FTM1_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM1_C1SC |= FTM_CSC_MSA; //Enable Compare mode
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//Enable channel compare interrupt (This is currently disabled as not in use)
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//FTM1_C1SC |= FTM_CSC_CHIE;
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//Enable IRQ Interrupt
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NVIC_ENABLE_IRQ(IRQ_FTM1);
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boost_pwm_max_count = 1000000L / (32 * configPage6.boostFreq * 2); //Converts the frequency in Hz to the number of ticks (at 16uS) it takes to complete 1 cycle. Note that the frequency is divided by 2 coming from TS to allow for up to 512hz
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vvt_pwm_max_count = 1000000L / (32 * configPage6.vvtFreq * 2); //Converts the frequency in Hz to the number of ticks (at 16uS) it takes to complete 1 cycle. Note that the frequency is divided by 2 coming from TS to allow for up to 512hz
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}
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/*
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/*
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***********************************************************************************************************
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***********************************************************************************************************
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* Timers
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* Timers
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@ -89,31 +156,6 @@ void initBoard()
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//Uses the PIT timer on Teensy.
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//Uses the PIT timer on Teensy.
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lowResTimer.begin(oneMSInterval, 1000);
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lowResTimer.begin(oneMSInterval, 1000);
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/*
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***********************************************************************************************************
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* Auxilliaries
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*/
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//FlexTimer 1 is used for boost and VVT. There are 8 channels on this module
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FTM1_MODE |= FTM_MODE_WPDIS; // Write Protection Disable
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FTM1_MODE |= FTM_MODE_FTMEN; //Flex Timer module enable
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FTM1_MODE |= FTM_MODE_INIT;
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FTM1_SC |= FTM_SC_CLKS(0b1); // Set internal clocked
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FTM1_SC |= FTM_SC_PS(0b111); //Set prescaler to 128 (2.1333uS tick time)
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//Enable each compare channel individually
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FTM1_C0SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM1_C0SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM1_C0SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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FTM1_C1SC &= ~FTM_CSC_MSB; //According to Pg 965 of the K64 datasheet, this should not be needed as MSB is reset to 0 upon reset, but the channel interrupt fails to fire without it
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FTM1_C1SC |= FTM_CSC_MSA; //Enable Compare mode
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FTM1_C1SC |= FTM_CSC_CHIE; //Enable channel compare interrupt
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//NVIC_ENABLE_IRQ(IRQ_FTM1);
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//2uS resolution Min 8Hz, Max 5KHz
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boost_pwm_max_count = 1000000L / (2 * configPage6.boostFreq * 2); //Converts the frequency in Hz to the number of ticks (at 2uS) it takes to complete 1 cycle. The x2 is there because the frequency is stored at half value (in a byte) to allow freqneucies up to 511Hz
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vvt_pwm_max_count = 1000000L / (2 * configPage6.vvtFreq * 2); //Converts the frequency in Hz to the number of ticks (at 2uS) it takes to complete 1 cycle
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/*
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/*
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***********************************************************************************************************
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***********************************************************************************************************
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* Schedules
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* Schedules
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@ -239,8 +281,7 @@ void initBoard()
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// enable IRQ Interrupt
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// enable IRQ Interrupt
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NVIC_ENABLE_IRQ(IRQ_FTM0);
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NVIC_ENABLE_IRQ(IRQ_FTM0);
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NVIC_ENABLE_IRQ(IRQ_FTM1);
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NVIC_ENABLE_IRQ(IRQ_FTM3);
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}
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}
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uint16_t freeRam()
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uint16_t freeRam()
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@ -260,5 +301,4 @@ uint16_t freeRam()
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return (uint16_t)stackTop - heapTop;
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return (uint16_t)stackTop - heapTop;
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}
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}
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#endif
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#endif
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