186 lines
9.0 KiB
C
186 lines
9.0 KiB
C
#ifndef TEENSY41_H
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#define TEENSY41_H
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#if defined(CORE_TEENSY) && defined(__IMXRT1062__)
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/*
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***********************************************************************************************************
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* General
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*/
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void initBoard();
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uint16_t freeRam();
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void doSystemReset();
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void jumpToBootloader();
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void setTriggerHysteresis();
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time_t getTeensy3Time();
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#define PORT_TYPE uint32_t //Size of the port variables
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#define PINMASK_TYPE uint32_t
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#define COMPARE_TYPE uint16_t
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#define COUNTER_TYPE uint16_t
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#define SERIAL_BUFFER_SIZE 517 //Size of the serial buffer used by new comms protocol. For SD transfers this must be at least 512 + 1 (flag) + 4 (sector)
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#define FPU_MAX_SIZE 32 //Size of the FPU buffer. 0 means no FPU.
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#define BOARD_MAX_DIGITAL_PINS 54
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#define BOARD_MAX_IO_PINS 54
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#define BOARD_MAX_ADC_PINS 17 //Number of analog pins
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#define EEPROM_LIB_H <EEPROM.h>
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typedef int eeprom_address_t;
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#define RTC_ENABLED
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#define SD_LOGGING //SD logging enabled by default for Teensy 4.1 as it has the slot built in
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#define RTC_LIB_H "TimeLib.h"
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#define SD_CONFIG SdioConfig(FIFO_SDIO) //Set Teensy to use SDIO in FIFO mode. This is the fastest SD mode on Teensy as it offloads most of the writes
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#define micros_safe() micros() //timer5 method is not used on anything but AVR, the micros_safe() macro is simply an alias for the normal micros()
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//#define PWM_FAN_AVAILABLE
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#define pinIsReserved(pin) ( ((pin) == 0) || ((pin) == 42) || ((pin) == 43) || ((pin) == 44) || ((pin) == 45) || ((pin) == 46) || ((pin) == 47) ) //Forbidden pins like USB
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/*
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***********************************************************************************************************
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* Schedules
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*/
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/*
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https://github.com/luni64/TeensyTimerTool/wiki/Supported-Timers#pit---periodic-timer
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https://github.com/luni64/TeensyTimerTool/wiki/Configuration#clock-setting-for-the-gpt-and-pit-timers
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The Quad timer (TMR) provides 4 timers each with 4 usable compare channels. The down compare and alternating compares are not usable
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FUEL 1-4: TMR1
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IGN 1-4 : TMR2
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FUEL 5-8: TMR3
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IGN 5-8 : TMR4
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*/
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#define FUEL1_COUNTER TMR1_CNTR0
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#define FUEL2_COUNTER TMR1_CNTR1
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#define FUEL3_COUNTER TMR1_CNTR2
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#define FUEL4_COUNTER TMR1_CNTR3
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#define FUEL5_COUNTER TMR3_CNTR0
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#define FUEL6_COUNTER TMR3_CNTR1
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#define FUEL7_COUNTER TMR3_CNTR2
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#define FUEL8_COUNTER TMR3_CNTR3
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#define IGN1_COUNTER TMR2_CNTR0
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#define IGN2_COUNTER TMR2_CNTR1
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#define IGN3_COUNTER TMR2_CNTR2
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#define IGN4_COUNTER TMR2_CNTR3
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#define IGN5_COUNTER TMR4_CNTR0
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#define IGN6_COUNTER TMR4_CNTR1
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#define IGN7_COUNTER TMR4_CNTR2
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#define IGN8_COUNTER TMR4_CNTR3
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#define FUEL1_COMPARE TMR1_COMP10
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#define FUEL2_COMPARE TMR1_COMP11
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#define FUEL3_COMPARE TMR1_COMP12
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#define FUEL4_COMPARE TMR1_COMP13
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#define FUEL5_COMPARE TMR3_COMP10
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#define FUEL6_COMPARE TMR3_COMP11
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#define FUEL7_COMPARE TMR3_COMP12
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#define FUEL8_COMPARE TMR3_COMP13
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#define IGN1_COMPARE TMR2_COMP10
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#define IGN2_COMPARE TMR2_COMP11
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#define IGN3_COMPARE TMR2_COMP12
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#define IGN4_COMPARE TMR2_COMP13
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#define IGN5_COMPARE TMR4_COMP10
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#define IGN6_COMPARE TMR4_COMP11
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#define IGN7_COMPARE TMR4_COMP12
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#define IGN8_COMPARE TMR4_COMP13
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static inline void FUEL1_TIMER_ENABLE(void) {TMR1_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL0 |= TMR_CSCTRL_TCF1EN;} //Write 1 to the TCFIEN (Channel Interrupt Enable) bit of channel 0 Status/Control
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static inline void FUEL2_TIMER_ENABLE(void) {TMR1_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
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static inline void FUEL3_TIMER_ENABLE(void) {TMR1_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
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static inline void FUEL4_TIMER_ENABLE(void) {TMR1_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
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static inline void FUEL5_TIMER_ENABLE(void) {TMR3_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
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static inline void FUEL6_TIMER_ENABLE(void) {TMR3_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
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static inline void FUEL7_TIMER_ENABLE(void) {TMR3_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
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static inline void FUEL8_TIMER_ENABLE(void) {TMR3_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
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static inline void FUEL1_TIMER_DISABLE(void) {TMR1_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;} //Write 0 to the TCFIEN (Channel Interrupt Enable) bit of channel 0 Status/Control
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static inline void FUEL2_TIMER_DISABLE(void) {TMR1_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void FUEL3_TIMER_DISABLE(void) {TMR1_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void FUEL4_TIMER_DISABLE(void) {TMR1_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void FUEL5_TIMER_DISABLE(void) {TMR3_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void FUEL6_TIMER_DISABLE(void) {TMR3_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void FUEL7_TIMER_DISABLE(void) {TMR3_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void FUEL8_TIMER_DISABLE(void) {TMR3_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void IGN1_TIMER_ENABLE(void) {TMR2_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
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static inline void IGN2_TIMER_ENABLE(void) {TMR2_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
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static inline void IGN3_TIMER_ENABLE(void) {TMR2_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
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static inline void IGN4_TIMER_ENABLE(void) {TMR2_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
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static inline void IGN5_TIMER_ENABLE(void) {TMR4_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
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static inline void IGN6_TIMER_ENABLE(void) {TMR4_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
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static inline void IGN7_TIMER_ENABLE(void) {TMR4_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
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static inline void IGN8_TIMER_ENABLE(void) {TMR4_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
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static inline void IGN1_TIMER_DISABLE(void) {TMR2_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void IGN2_TIMER_DISABLE(void) {TMR2_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void IGN3_TIMER_DISABLE(void) {TMR2_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void IGN4_TIMER_DISABLE(void) {TMR2_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void IGN5_TIMER_DISABLE(void) {TMR4_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void IGN6_TIMER_DISABLE(void) {TMR4_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void IGN7_TIMER_DISABLE(void) {TMR4_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
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static inline void IGN8_TIMER_DISABLE(void) {TMR4_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
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//Bus Clock is 150Mhz @ 600 Mhz CPU. Need to handle this dynamically in the future for other frequencies
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//#define TMR_PRESCALE 128
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//#define MAX_TIMER_PERIOD ((65535 * 1000000ULL) / (F_BUS_ACTUAL / TMR_PRESCALE)) //55923 @ 600Mhz.
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#define MAX_TIMER_PERIOD 55923UL
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#define uS_TO_TIMER_COMPARE(uS) ((uS * 75UL) >> 6) //Converts a given number of uS into the required number of timer ticks until that time has passed.
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/*
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To calculate the above uS_TO_TIMER_COMPARE
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Choose number of bit of precision. Eg: 6
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Divide 2^6 by the time per tick (0.853333) = 75
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Multiply and bitshift back by the precision: (uS * 75) >> 6
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*/
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/*
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***********************************************************************************************************
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* Auxiliaries
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*/
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#define ENABLE_BOOST_TIMER() PIT_TCTRL1 |= PIT_TCTRL_TEN
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#define DISABLE_BOOST_TIMER() PIT_TCTRL1 &= ~PIT_TCTRL_TEN
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#define ENABLE_VVT_TIMER() PIT_TCTRL2 |= PIT_TCTRL_TEN
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#define DISABLE_VVT_TIMER() PIT_TCTRL2 &= ~PIT_TCTRL_TEN
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//Ran out of timers, this most likely won't work. This should be possible to implement with the GPT timer.
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#define ENABLE_FAN_TIMER() TMR3_CSCTRL1 |= TMR_CSCTRL_TCF2EN
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#define DISABLE_FAN_TIMER() TMR3_CSCTRL1 &= ~TMR_CSCTRL_TCF2EN
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#define BOOST_TIMER_COMPARE PIT_LDVAL1
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#define BOOST_TIMER_COUNTER 0
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#define VVT_TIMER_COMPARE PIT_LDVAL2
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#define VVT_TIMER_COUNTER 0
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//these probaply need to be PIT_LDVAL something???
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#define FAN_TIMER_COMPARE TMR3_COMP22
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#define FAN_TIMER_COUNTER TMR3_CNTR1
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/*
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***********************************************************************************************************
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* Idle
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*/
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#define IDLE_COUNTER 0
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#define IDLE_COMPARE PIT_LDVAL0
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#define IDLE_TIMER_ENABLE() PIT_TCTRL0 |= PIT_TCTRL_TEN
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#define IDLE_TIMER_DISABLE() PIT_TCTRL0 &= ~PIT_TCTRL_TEN
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/*
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***********************************************************************************************************
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* CAN / Second serial
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*/
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#define USE_SERIAL3
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#define secondarySerial_AVAILABLE
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#define SECONDARY_SERIAL_T HardwareSerial
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#include <FlexCAN_T4.h>
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/*
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//These are declared locally in comms_CAN now due to this issue: https://github.com/tonton81/FlexCAN_T4/issues/67
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extern FlexCAN_T4<CAN1, RX_SIZE_256, TX_SIZE_16> Can0;
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extern FlexCAN_T4<CAN2, RX_SIZE_256, TX_SIZE_16> Can1;
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extern FlexCAN_T4<CAN3, RX_SIZE_256, TX_SIZE_16> Can2;
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*/
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#define NATIVE_CAN_AVAILABLE //Disable for now as it causes lockup
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#endif //CORE_TEENSY
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#endif //TEENSY41_H
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