!1 fix a typo: intterrupt -> interrupt

Merge pull request !1 from master
This commit is contained in:
Artery-MCU 2023-02-28 02:53:54 +00:00 committed by Gitee
commit 66089830a3
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GPG Key ID: 173E9B9CA92EEF8F
27 changed files with 36 additions and 36 deletions

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@ -47,10 +47,10 @@ extern "C" {
* @{
*/
#define EDMA_DMERR_INT ((uint32_t)0x00000002) /* edma direct mode error intterrupt */
#define EDMA_DTERR_INT ((uint32_t)0x00000004) /* edma data transfer error intterrupt */
#define EDMA_HDT_INT ((uint32_t)0x00000008) /* edma half data transfer intterrupt */
#define EDMA_FDT_INT ((uint32_t)0x00000010) /* edma full data transfer intterrupt */
#define EDMA_DMERR_INT ((uint32_t)0x00000002) /* edma direct mode error interrupt */
#define EDMA_DTERR_INT ((uint32_t)0x00000004) /* edma data transfer error interrupt */
#define EDMA_HDT_INT ((uint32_t)0x00000008) /* edma half data transfer interrupt */
#define EDMA_FDT_INT ((uint32_t)0x00000010) /* edma full data transfer interrupt */
#define EDMA_FERR_INT ((uint32_t)0x00000080) /* edma fifo error interrupt */
/**

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@ -98,7 +98,7 @@ static void edma_config(void)
edmamux_enable(TRUE);
edmamux_init(EDMAMUX_CHANNEL1, EDMAMUX_DMAREQ_ID_ADC1);
/* enable edma full data transfer intterrupt */
/* enable edma full data transfer interrupt */
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
edma_stream_enable(EDMA_STREAM1, TRUE);
}

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@ -100,7 +100,7 @@ static void edma_config(void)
/* enable the double memory mode */
edma_double_buffer_mode_enable(EDMA_STREAM1, TRUE);
/* enable edma full data transfer intterrupt */
/* enable edma full data transfer interrupt */
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
edma_stream_enable(EDMA_STREAM1, TRUE);
}

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@ -86,7 +86,7 @@ int main(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA2_CHANNEL1, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA2_CHANNEL1, DMA_FDT_INT, TRUE);
/* dma2 channel1 interrupt nvic init */

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@ -116,7 +116,7 @@ int main(void)
dmamux_gen_init_struct.gen_enable = TRUE;
dmamux_generator_config(DMA2MUX_GENERATOR1, &dmamux_gen_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);
/* dma2 channel4 interrupt nvic init */

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@ -118,7 +118,7 @@ int main(void)
dmamux_sync_init_struct.sync_enable = TRUE;
dmamux_sync_config(DMA2MUX_CHANNEL4, &dmamux_sync_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);
/* dma2 channel4 interrupt nvic init */

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@ -102,7 +102,7 @@ int main(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL1, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
/* dma1 channel1 interrupt nvic init */

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@ -136,7 +136,7 @@ int main(void)
dmamux_gen_init_struct.gen_enable = TRUE;
edmamux_generator_config(EDMAMUX_GENERATOR1, &dmamux_gen_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
edma_interrupt_enable(EDMA_STREAM4, EDMA_FDT_INT, TRUE);
/* edma stream4 interrupt nvic init */

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@ -138,7 +138,7 @@ int main(void)
edmamux_sync_init_struct.sync_signal_sel = EDMAMUX_SYNC_ID_EXINT1;
edmamux_sync_config(EDMAMUX_CHANNEL4, &edmamux_sync_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
edma_interrupt_enable(EDMA_STREAM4, EDMA_FDT_INT, TRUE);
/* edma stream4 interrupt nvic init */

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@ -119,7 +119,7 @@ int main(void)
edma_init_struct.loop_mode_enable = FALSE;
edma_init(EDMA_STREAM1, &edma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
/* edma stream1 interrupt nvic init */

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@ -165,7 +165,7 @@ static void i2s_config(void)
edma_double_buffer_mode_init(EDMA_STREAM2, (uint32_t)i2s3_buffer2_tx, EDMA_MEMORY_0);
edma_double_buffer_mode_enable(EDMA_STREAM2, TRUE);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
/* edma stream1 interrupt nvic init */

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@ -112,7 +112,7 @@ int main(void)
edmamux_enable(TRUE);
edmamux_init(EDMAMUX_CHANNEL1, EDMAMUX_DMAREQ_ID_USART1_TX);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
/* edma stream1 interrupt nvic init */

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@ -99,7 +99,7 @@ int main(void)
edma_init_struct.loop_mode_enable = FALSE;
edma_init(EDMA_STREAM1, &edma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
/* edma stream1 interrupt nvic init */

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@ -126,7 +126,7 @@ void dma_configuration(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL1, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
/* dma1 channel1 interrupt nvic init */
@ -151,7 +151,7 @@ void dma_configuration(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL2, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL2, DMA_FDT_INT, TRUE);
/* dma1 channel2 interrupt nvic init */
@ -175,7 +175,7 @@ void dma_configuration(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL3, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL3, DMA_FDT_INT, TRUE);
/* dma1 channel3 interrupt nvic init */
@ -199,7 +199,7 @@ void dma_configuration(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL4, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL4, DMA_FDT_INT, TRUE);
/* dma1 channel4 interrupt nvic init */

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@ -98,7 +98,7 @@ static void edma_config(void)
edmamux_enable(TRUE);
edmamux_init(EDMAMUX_CHANNEL1, EDMAMUX_DMAREQ_ID_ADC1);
/* enable edma full data transfer intterrupt */
/* enable edma full data transfer interrupt */
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
edma_stream_enable(EDMA_STREAM1, TRUE);
}

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@ -100,7 +100,7 @@ static void edma_config(void)
/* enable the double memory mode */
edma_double_buffer_mode_enable(EDMA_STREAM1, TRUE);
/* enable edma full data transfer intterrupt */
/* enable edma full data transfer interrupt */
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
edma_stream_enable(EDMA_STREAM1, TRUE);
}

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@ -86,7 +86,7 @@ int main(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA2_CHANNEL1, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA2_CHANNEL1, DMA_FDT_INT, TRUE);
/* dma2 channel1 interrupt nvic init */

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@ -116,7 +116,7 @@ int main(void)
dmamux_gen_init_struct.gen_enable = TRUE;
dmamux_generator_config(DMA2MUX_GENERATOR1, &dmamux_gen_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);
/* dma2 channel4 interrupt nvic init */

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@ -118,7 +118,7 @@ int main(void)
dmamux_sync_init_struct.sync_enable = TRUE;
dmamux_sync_config(DMA2MUX_CHANNEL4, &dmamux_sync_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);
/* dma2 channel4 interrupt nvic init */

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@ -102,7 +102,7 @@ int main(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL1, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
/* dma1 channel1 interrupt nvic init */

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@ -136,7 +136,7 @@ int main(void)
dmamux_gen_init_struct.gen_enable = TRUE;
edmamux_generator_config(EDMAMUX_GENERATOR1, &dmamux_gen_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
edma_interrupt_enable(EDMA_STREAM4, EDMA_FDT_INT, TRUE);
/* edma stream4 interrupt nvic init */

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@ -138,7 +138,7 @@ int main(void)
edmamux_sync_init_struct.sync_signal_sel = EDMAMUX_SYNC_ID_EXINT1;
edmamux_sync_config(EDMAMUX_CHANNEL4, &edmamux_sync_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
edma_interrupt_enable(EDMA_STREAM4, EDMA_FDT_INT, TRUE);
/* edma stream4 interrupt nvic init */

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@ -119,7 +119,7 @@ int main(void)
edma_init_struct.loop_mode_enable = FALSE;
edma_init(EDMA_STREAM1, &edma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
/* edma stream1 interrupt nvic init */

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@ -165,7 +165,7 @@ static void i2s_config(void)
edma_double_buffer_mode_init(EDMA_STREAM2, (uint32_t)i2s3_buffer2_tx, EDMA_MEMORY_0);
edma_double_buffer_mode_enable(EDMA_STREAM2, TRUE);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
/* edma stream1 interrupt nvic init */

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@ -112,7 +112,7 @@ int main(void)
edmamux_enable(TRUE);
edmamux_init(EDMAMUX_CHANNEL1, EDMAMUX_DMAREQ_ID_USART1_TX);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
/* edma stream1 interrupt nvic init */

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@ -99,7 +99,7 @@ int main(void)
edma_init_struct.loop_mode_enable = FALSE;
edma_init(EDMA_STREAM1, &edma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
/* edma stream1 interrupt nvic init */

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@ -126,7 +126,7 @@ void dma_configuration(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL1, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
/* dma1 channel1 interrupt nvic init */
@ -151,7 +151,7 @@ void dma_configuration(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL2, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL2, DMA_FDT_INT, TRUE);
/* dma1 channel2 interrupt nvic init */
@ -175,7 +175,7 @@ void dma_configuration(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL3, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL3, DMA_FDT_INT, TRUE);
/* dma1 channel3 interrupt nvic init */
@ -199,7 +199,7 @@ void dma_configuration(void)
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL4, &dma_init_struct);
/* enable transfer full data intterrupt */
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL4, DMA_FDT_INT, TRUE);
/* dma1 channel4 interrupt nvic init */