diff --git a/document/AT32F435_437固件库BSP&Pack应用指南.pdf b/document/AT32F435_437固件库BSP&Pack应用指南.pdf index 8f4e2c8f..7ba36b9a 100644 Binary files a/document/AT32F435_437固件库BSP&Pack应用指南.pdf and b/document/AT32F435_437固件库BSP&Pack应用指南.pdf differ diff --git a/document/ReleaseNotes_AT32F435_437_Firmware_Library.pdf b/document/ReleaseNotes_AT32F435_437_Firmware_Library.pdf index 4a4f27fa..3ef87af0 100644 Binary files a/document/ReleaseNotes_AT32F435_437_Firmware_Library.pdf and b/document/ReleaseNotes_AT32F435_437_Firmware_Library.pdf differ diff --git a/libraries/cmsis/cm4/device_support/at32f435_437.h b/libraries/cmsis/cm4/device_support/at32f435_437.h index 5ea331ec..2ee213a3 100644 --- a/libraries/cmsis/cm4/device_support/at32f435_437.h +++ b/libraries/cmsis/cm4/device_support/at32f435_437.h @@ -134,7 +134,7 @@ extern "C" { */ #define __AT32F435_437_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ #define __AT32F435_437_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */ -#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x01) /*!< [15:8] minor version */ +#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x02) /*!< [15:8] minor version */ #define __AT32F435_437_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __AT32F435_437_LIBRARY_VERSION ((__AT32F435_437_LIBRARY_VERSION_MAJOR << 24) | \ (__AT32F435_437_LIBRARY_VERSION_MIDDLE << 16) | \ diff --git a/libraries/cmsis/cm4/device_support/at32f435_437_conf_template.h b/libraries/cmsis/cm4/device_support/at32f435_437_conf_template.h index 6c786918..ef2ff88e 100644 --- a/libraries/cmsis/cm4/device_support/at32f435_437_conf_template.h +++ b/libraries/cmsis/cm4/device_support/at32f435_437_conf_template.h @@ -45,8 +45,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/libraries/cmsis/cm4/device_support/system_at32f435_437.c b/libraries/cmsis/cm4/device_support/system_at32f435_437.c index 117dd4c0..0ce0b4ef 100644 --- a/libraries/cmsis/cm4/device_support/system_at32f435_437.c +++ b/libraries/cmsis/cm4/device_support/system_at32f435_437.c @@ -35,7 +35,7 @@ /** @addtogroup AT32F435_437_system_private_defines * @{ */ -#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x400. */ /** * @} */ diff --git a/libraries/drivers/ReleaseNotes_AT32F435_437_Firmware_Library_Drivers.pdf b/libraries/drivers/ReleaseNotes_AT32F435_437_Firmware_Library_Drivers.pdf index f6877051..155d083a 100644 Binary files a/libraries/drivers/ReleaseNotes_AT32F435_437_Firmware_Library_Drivers.pdf and b/libraries/drivers/ReleaseNotes_AT32F435_437_Firmware_Library_Drivers.pdf differ diff --git a/libraries/drivers/inc/at32f435_437_crm.h b/libraries/drivers/inc/at32f435_437_crm.h index 3d0917d6..3501ff3b 100644 --- a/libraries/drivers/inc/at32f435_437_crm.h +++ b/libraries/drivers/inc/at32f435_437_crm.h @@ -402,10 +402,6 @@ typedef enum CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */ CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */ CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */ - CRM_EMAC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 25), /*!< emac sleep mode periph clock */ - CRM_EMACTX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 26), /*!< emac tx sleep mode periph clock */ - CRM_EMACRX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 27), /*!< emac rx sleep mode periph clock */ - CRM_EMACPTP_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 28), /*!< emac ptp sleep mode periph clock */ CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */ /* ahb periph2 */ CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */ @@ -477,6 +473,10 @@ typedef enum CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */ CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */ CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */ + CRM_EMAC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 25), /*!< emac sleep mode periph clock */ + CRM_EMACTX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 26), /*!< emac tx sleep mode periph clock */ + CRM_EMACRX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 27), /*!< emac rx sleep mode periph clock */ + CRM_EMACPTP_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 28), /*!< emac ptp sleep mode periph clock */ CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */ /* ahb periph2 */ CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */ diff --git a/libraries/drivers/inc/at32f435_437_tmr.h b/libraries/drivers/inc/at32f435_437_tmr.h index 7870eb48..3891860c 100644 --- a/libraries/drivers/inc/at32f435_437_tmr.h +++ b/libraries/drivers/inc/at32f435_437_tmr.h @@ -238,7 +238,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** diff --git a/libraries/drivers/src/at32f435_437_ertc.c b/libraries/drivers/src/at32f435_437_ertc.c index 6b175737..24d8d681 100644 --- a/libraries/drivers/src/at32f435_437_ertc.c +++ b/libraries/drivers/src/at32f435_437_ertc.c @@ -320,7 +320,7 @@ error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t we return ERROR; } - /* Set the ertc_DR register */ + /* set the ertc_date register */ ERTC->date = reg.date; /* exit init mode */ @@ -395,8 +395,6 @@ void ertc_calendar_get(ertc_time_type* time) ertc_reg_time_type reg_tm; ertc_reg_date_type reg_dt; - UNUSED(ERTC->sts); - reg_tm.time = ERTC->time; reg_dt.date = ERTC->date; @@ -1516,13 +1514,7 @@ void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data) reg = ERTC_BASE + 0x50 + (dt * 4); - /* disable write protection */ - ertc_write_protect_disable(); - *(__IO uint32_t *)reg = data; - - /* enable write protection */ - ertc_write_protect_enable(); } /** diff --git a/middlewares/3rd_party/lwip_2.1.2/port/arch/cc.h b/middlewares/3rd_party/lwip_2.1.2/port/arch/cc.h index 3a181c61..6faea570 100644 --- a/middlewares/3rd_party/lwip_2.1.2/port/arch/cc.h +++ b/middlewares/3rd_party/lwip_2.1.2/port/arch/cc.h @@ -32,81 +32,44 @@ #ifndef LWIP_ARCH_CC_H #define LWIP_ARCH_CC_H -#ifdef _MSC_VER -#pragma warning (disable: 4127) /* conditional expression is constant */ -#pragma warning (disable: 4996) /* 'strncpy' was declared deprecated */ -#pragma warning (disable: 4103) /* structure packing changed by including file */ -#pragma warning (disable: 4820) /* 'x' bytes padding added after data member 'y' */ -#pragma warning (disable: 4711) /* The compiler performed inlining on the given function, although it was not marked for inlining */ -#endif - -#ifdef _MSC_VER -#if _MSC_VER >= 1910 -#include /* use MSVC errno for >= 2017 */ -#else -#define LWIP_PROVIDE_ERRNO /* provide errno for MSVC pre-2017 */ -#endif -#else /* _MSC_VER */ -#define LWIP_PROVIDE_ERRNO /* provide errno for non-MSVC */ -#endif /* _MSC_VER */ - -/* Define platform endianness (might already be defined) */ -#ifndef BYTE_ORDER -#define BYTE_ORDER LITTLE_ENDIAN -#endif /* BYTE_ORDER */ - typedef int sys_prot_t; -#ifdef _MSC_VER -/* define _INTPTR for Win32 MSVC stdint.h */ -#define _INTPTR 2 +/* Define random number generator function */ +#define LWIP_RAND() ((u32_t)rand()) -/* Do not use lwIP default definitions for format strings - * because these do not work with MSVC 2010 compiler (no inttypes.h) - */ -#define LWIP_NO_INTTYPES_H 1 +/* define compiler specific symbols */ +#if defined (__ICCARM__) -/* Define (sn)printf formatters for these lwIP types */ -#define X8_F "02x" -#define U16_F "hu" -#define U32_F "lu" -#define S32_F "ld" -#define X32_F "lx" - -#define S16_F "hd" -#define X16_F "hx" -#define SZT_F "lu" -#endif /* _MSC_VER */ - -/* Compiler hints for packing structures */ +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_END +#define PACK_STRUCT_FIELD(x) x #define PACK_STRUCT_USE_INCLUDES -#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \ - printf("Assertion \"%s\" failed at line %d in %s\n", message, __LINE__, __FILE__); \ - fflush(NULL);handler;} } while(0) +#elif defined (__GNUC__) + +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_STRUCT __attribute__ ((__packed__)) +#define PACK_STRUCT_END +#define PACK_STRUCT_FIELD(x) x + +#elif defined (__CC_ARM) + +#define PACK_STRUCT_BEGIN __packed +#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_END +#define PACK_STRUCT_FIELD(x) x + +#elif defined (__TASKING__) + +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_END +#define PACK_STRUCT_FIELD(x) x -#ifdef _MSC_VER -/* C runtime functions redefined */ -#if _MSC_VER < 1910 -#define snprintf _snprintf -#endif -#define strdup _strdup #endif -/* Define an example for LWIP_PLATFORM_DIAG: since this uses varargs and the old - * C standard lwIP targets does not support this in macros, we have extra brackets - * around the arguments, which are left out in the following macro definition: - */ -#if !defined(LWIP_TESTMODE) || !LWIP_TESTMODE -void lwip_win32_platform_diag(const char *format, ...); -#define LWIP_PLATFORM_DIAG(x) lwip_win32_platform_diag x -#endif - -//#ifndef LWIP_NORAND -//extern unsigned int sys_win_rand(void); -//#define LWIP_RAND() (sys_win_rand()) -//#endif - -#define PPP_INCLUDE_SETTINGS_HEADER +#define LWIP_PLATFORM_ASSERT(x) do {printf("Assertion \"%s\" failed at line %d in %s\n", \ + x, __LINE__, __FILE__); } while(0) #endif /* LWIP_ARCH_CC_H */ diff --git a/middlewares/3rd_party/lwip_2.1.2/port/ethernetif.c b/middlewares/3rd_party/lwip_2.1.2/port/ethernetif.c index 9e458e55..35ba0324 100644 --- a/middlewares/3rd_party/lwip_2.1.2/port/ethernetif.c +++ b/middlewares/3rd_party/lwip_2.1.2/port/ethernetif.c @@ -94,14 +94,19 @@ extern emac_dma_desc_type *dma_tx_desc_to_set; extern emac_dma_desc_type *dma_rx_desc_to_get; typedef struct{ -u32 length; -u32 buffer; -emac_dma_desc_type *descriptor; + u32 length; + u32 buffer; + emac_dma_desc_type *descriptor; + emac_dma_desc_type *rx_fs_desc; + emac_dma_desc_type *rx_ls_desc; + uint32_t g_seg_count; }FrameTypeDef; -FrameTypeDef emac_rxpkt_chainmode(void); +FrameTypeDef rx_frame; + +error_status emac_rxpkt_chainmode(void); u32 emac_getcurrenttxbuffer(void); -error_status emac_txpkt_chainmode(u16 FrameLength); +error_status emac_txpkt_chainmode(uint32_t FrameLength); /** @@ -133,6 +138,8 @@ void lwip_set_mac_address(uint8_t* macadd) static void low_level_init(struct netif *netif) { + uint32_t index = 0; + /* set MAC hardware address length */ netif->hwaddr_len = ETHARP_HWADDR_LEN; @@ -149,7 +156,7 @@ low_level_init(struct netif *netif) /* device capabilities */ /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ - netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; + netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; /* Initialize Tx Descriptors list: Chain Mode */ emac_dma_descriptor_list_address_set(EMAC_DMA_TRANSMIT, DMATxDscrTab, &Tx_Buff[0][0], EMAC_TXBUFNB); @@ -157,18 +164,19 @@ low_level_init(struct netif *netif) emac_dma_descriptor_list_address_set(EMAC_DMA_RECEIVE, DMARxDscrTab, &Rx_Buff[0][0], EMAC_RXBUFNB); /* Enable Ethernet Rx interrrupt */ - { int i; - for(i=0; i < EMAC_RXBUFNB; i++) - { - emac_dma_rx_desc_interrupt_config(&DMARxDscrTab[i], TRUE); - } -#ifdef CHECKSUM_BY_HARDWARE - for(i=0; i < EMAC_TXBUFNB; i++) - { - DMATxDscrTab[i].status |= EMAC_DMATXDESC_CIC_TUI_FULL; - } -#endif + for(index = 0; index < EMAC_RXBUFNB; index ++) + { + emac_dma_rx_desc_interrupt_config(&DMARxDscrTab[index], TRUE); } + +#ifdef CHECKSUM_BY_HARDWARE + for(index = 0; index < EMAC_TXBUFNB; index ++) + { + DMATxDscrTab[index].status |= EMAC_DMATXDESC_CIC_TUI_FULL; + } +#endif + + rx_frame.g_seg_count = 0; /* Enable MAC and DMA transmission and reception */ emac_start(); @@ -195,21 +203,66 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p) { struct pbuf *q; - int l = 0; - u8 *buffer = (u8 *)emac_getcurrenttxbuffer(); - + err_t errno; + emac_dma_desc_type *dma_tx_desc; + uint8_t *buffer; + uint32_t length = 0; + uint32_t buffer_offset = 0, payload_offset = 0, copy_count = 0; + + dma_tx_desc = dma_tx_desc_to_set; + buffer = (uint8_t *)emac_getcurrenttxbuffer(); + + /* copy data to buffer */ for(q = p; q != NULL; q = q->next) { - memcpy((u8_t*)&buffer[l], q->payload, q->len); - l = l + q->len; + if((dma_tx_desc->status & EMAC_DMATXDESC_OWN) != RESET) + { + errno = ERR_USE; + goto out_error; + } + + copy_count = q->len; + payload_offset = 0; + + while((copy_count + buffer_offset) > EMAC_MAX_PACKET_LENGTH) + { + memcpy(buffer + buffer_offset, (uint8_t *)q->payload + payload_offset, (EMAC_MAX_PACKET_LENGTH - buffer_offset)); + dma_tx_desc = (emac_dma_desc_type*)dma_tx_desc->buf2nextdescaddr; + + if((dma_tx_desc->status & EMAC_DMATXDESC_OWN) != RESET) + { + errno = ERR_USE; + goto out_error; + } + + buffer = (uint8_t *)dma_tx_desc->buf1addr; + + copy_count = copy_count - (EMAC_MAX_PACKET_LENGTH - buffer_offset); + payload_offset = payload_offset + (EMAC_MAX_PACKET_LENGTH - buffer_offset); + length = length + (EMAC_MAX_PACKET_LENGTH - buffer_offset); + buffer_offset = 0; + } + + memcpy(buffer + buffer_offset, (uint8_t *)q->payload + payload_offset, copy_count); + buffer_offset = buffer_offset + copy_count; + length = length + copy_count; } - - if(emac_txpkt_chainmode(l) == ERROR) + + emac_txpkt_chainmode(length); + + errno = ERR_OK; + +out_error: + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if(emac_dma_flag_get(EMAC_DMA_TBU_FLAG)) { - return ERR_MEM; + /* Clear TBUS ETHERNET DMA flag */ + emac_dma_flag_clear(EMAC_DMA_TBU_FLAG); + /* Resume DMA transmission*/ + EMAC_DMA->tpd_bit.tpd = 0; } - - return ERR_OK; + + return errno; } /** @@ -224,35 +277,69 @@ static struct pbuf * low_level_input(struct netif *netif) { struct pbuf *p, *q; - u16_t len; - int l =0; - FrameTypeDef frame; - u8 *buffer; + uint32_t len = 0; + emac_dma_desc_type *dma_rx_desc; + uint8_t *buffer; + uint32_t buffer_offset, payload_offset = 0, copy_count = 0; + uint32_t index = 0; p = NULL; - frame = emac_rxpkt_chainmode(); + + if(emac_rxpkt_chainmode() != SUCCESS) + { + return NULL; + } + /* Obtain the size of the packet and put it into the "len" variable. */ - len = frame.length; - - buffer = (u8 *)frame.buffer; - + len = rx_frame.length; + buffer = (uint8_t *)rx_frame.buffer; + /* We allocate a pbuf chain of pbufs from the pool. */ - p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - - if (p != NULL) + if(len > 0) { + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + } + + if(p != NULL) + { + dma_rx_desc = rx_frame.rx_fs_desc; + buffer_offset = 0; + for (q = p; q != NULL; q = q->next) { - memcpy((u8_t*)q->payload, (u8_t*)&buffer[l], q->len); - l = l + q->len; + copy_count = q->len; + payload_offset = 0; + + while( (copy_count + buffer_offset) > EMAC_MAX_PACKET_LENGTH ) + { + /* copy data to pbuf */ + memcpy((uint8_t*)q->payload + payload_offset, buffer + buffer_offset, (EMAC_MAX_PACKET_LENGTH - buffer_offset)); + + /* point to next descriptor */ + dma_rx_desc = (emac_dma_desc_type *)(dma_rx_desc->buf2nextdescaddr); + buffer = (uint8_t *)(dma_rx_desc->buf1addr); + + copy_count = copy_count - (EMAC_MAX_PACKET_LENGTH - buffer_offset); + payload_offset = payload_offset + (EMAC_MAX_PACKET_LENGTH - buffer_offset); + buffer_offset = 0; + } + + memcpy((uint8_t*)q->payload + payload_offset, (uint8_t*)buffer + buffer_offset, copy_count); + buffer_offset = buffer_offset + copy_count; } + } - - - /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ - frame.descriptor->status |= EMAC_DMARXDESC_OWN; - + + dma_rx_desc = rx_frame.rx_fs_desc; + for(index = 0; index < rx_frame.g_seg_count; index ++) + { + dma_rx_desc->status |= EMAC_DMARXDESC_OWN; + dma_rx_desc = (emac_dma_desc_type*) (dma_rx_desc->buf2nextdescaddr); + } + + rx_frame.g_seg_count = 0; + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ if(emac_dma_flag_get(EMAC_DMA_RBU_FLAG)) { @@ -261,8 +348,7 @@ low_level_input(struct netif *netif) /* Resume DMA reception */ EMAC_DMA->rpd_bit.rpd = FALSE; } - - + return p; } @@ -359,55 +445,47 @@ ethernetif_init(struct netif *netif) * Description : Receives a packet. * Input : None * Output : None -* Return : frame: farme size and location +* Return : ERROR: in case of Tx desc owned by DMA +* SUCCESS: for correct transmission *******************************************************************************/ -FrameTypeDef emac_rxpkt_chainmode(void) +error_status emac_rxpkt_chainmode(void) { - u32 framelength = 0; - FrameTypeDef frame = {0,0}; - /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ if((dma_rx_desc_to_get->status & EMAC_DMARXDESC_OWN) != (u32)RESET) - { - frame.length = FALSE; - - if(emac_dma_flag_get(EMAC_DMA_RBU_FLAG)) - { - /* Clear RBUS ETHERNET DMA flag */ - emac_dma_flag_clear(EMAC_DMA_RBU_FLAG); - /* Resume DMA reception */ - EMAC_DMA->rpd_bit.rpd = FALSE; - } - /* Return error: OWN bit set */ - return frame; + { + /* return error: own bit set */ + return ERROR; } - - if(((dma_rx_desc_to_get->status & EMAC_DMATXDESC_ES) == (u32)RESET) && - ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_LS) != (u32)RESET) && - ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FS) != (u32)RESET)) + if((dma_rx_desc_to_get->status & EMAC_DMARXDESC_LS) != (u32)RESET) { - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FL) >> EMAC_DMARxDesc_FrameLengthShift) - 4; - - /* Get the addrees of the actual buffer */ - frame.buffer = dma_rx_desc_to_get->buf1addr; + rx_frame.g_seg_count ++; + if(rx_frame.g_seg_count == 1) + { + rx_frame.rx_fs_desc = dma_rx_desc_to_get; + } + rx_frame.rx_ls_desc = dma_rx_desc_to_get; + rx_frame.length = ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FL) >> EMAC_DMARxDesc_FrameLengthShift) - 4; + rx_frame.buffer = rx_frame.rx_fs_desc->buf1addr; + + /* Selects the next DMA Rx descriptor list for next buffer to read */ + dma_rx_desc_to_get = (emac_dma_desc_type*) (dma_rx_desc_to_get->buf2nextdescaddr); + + return SUCCESS; + } + else if((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FS) != (u32)RESET) + { + rx_frame.g_seg_count = 1; + rx_frame.rx_fs_desc = dma_rx_desc_to_get; + rx_frame.rx_ls_desc = NULL; + dma_rx_desc_to_get = (emac_dma_desc_type*) (dma_rx_desc_to_get->buf2nextdescaddr); } else { - /* Return ERROR */ - framelength = FALSE; + rx_frame.g_seg_count ++; + dma_rx_desc_to_get = (emac_dma_desc_type*) (dma_rx_desc_to_get->buf2nextdescaddr); } - frame.length = framelength; - - frame.descriptor = dma_rx_desc_to_get; - - /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ - /* Chained Mode */ - /* Selects the next DMA Rx descriptor list for next buffer to read */ - dma_rx_desc_to_get = (emac_dma_desc_type*) (dma_rx_desc_to_get->buf2nextdescaddr); - /* Return Frame */ - return (frame); + return ERROR; } /******************************************************************************* @@ -418,23 +496,81 @@ FrameTypeDef emac_rxpkt_chainmode(void) * Return : ERROR: in case of Tx desc owned by DMA * SUCCESS: for correct transmission *******************************************************************************/ -error_status emac_txpkt_chainmode(u16 FrameLength) +error_status emac_txpkt_chainmode(uint32_t FrameLength) { + uint32_t buf_cnt = 0, index = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ if((dma_tx_desc_to_set->status & EMAC_DMATXDESC_OWN) != (u32)RESET) { /* Return ERROR: OWN bit set */ return ERROR; } - - /* Setting the Frame Length: bits[12:0] */ - dma_tx_desc_to_set->controlsize = (FrameLength & EMAC_DMATXDESC_TBS1); - - /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ - dma_tx_desc_to_set->status |= EMAC_DMATXDESC_LS | EMAC_DMATXDESC_FS; - - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - dma_tx_desc_to_set->status |= EMAC_DMATXDESC_OWN; + + if(FrameLength == 0) + { + return ERROR; + } + + if(FrameLength > EMAC_MAX_PACKET_LENGTH) + { + buf_cnt = FrameLength / EMAC_MAX_PACKET_LENGTH; + if(FrameLength % EMAC_MAX_PACKET_LENGTH) + { + buf_cnt += 1; + } + } + else + { + buf_cnt = 1; + } + + if(buf_cnt == 1) + { + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + dma_tx_desc_to_set->status |= EMAC_DMATXDESC_LS | EMAC_DMATXDESC_FS; + + /* Setting the Frame Length: bits[12:0] */ + dma_tx_desc_to_set->controlsize = (FrameLength & EMAC_DMATXDESC_TBS1); + + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + dma_tx_desc_to_set->status |= EMAC_DMATXDESC_OWN; + + /* Selects the next DMA Tx descriptor list for next buffer to send */ + dma_tx_desc_to_set = (emac_dma_desc_type*) (dma_tx_desc_to_set->buf2nextdescaddr); + } + else + { + for(index = 0; index < buf_cnt; index ++) + { + /* clear first and last segments */ + dma_tx_desc_to_set->status &= ~(EMAC_DMATXDESC_LS | EMAC_DMATXDESC_FS); + + /* set first segments */ + if(index == 0) + { + dma_tx_desc_to_set->status |= EMAC_DMATXDESC_FS; + } + + /* set size */ + dma_tx_desc_to_set->controlsize = (EMAC_MAX_PACKET_LENGTH & EMAC_DMATXDESC_TBS1); + + /* set last segments */ + if(index == (buf_cnt - 1)) + { + dma_tx_desc_to_set->status |= EMAC_DMATXDESC_LS; + dma_tx_desc_to_set->controlsize = ((FrameLength - ((buf_cnt-1) * EMAC_MAX_PACKET_LENGTH)) & EMAC_DMATXDESC_TBS1); + } + + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + dma_tx_desc_to_set->status |= EMAC_DMATXDESC_OWN; + + /* Selects the next DMA Tx descriptor list for next buffer to send */ + dma_tx_desc_to_set = (emac_dma_desc_type*) (dma_tx_desc_to_set->buf2nextdescaddr); + + } + } + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ if(emac_dma_flag_get(EMAC_DMA_TBU_FLAG)) { @@ -443,12 +579,7 @@ error_status emac_txpkt_chainmode(u16 FrameLength) /* Resume DMA transmission*/ EMAC_DMA->tpd_bit.tpd = 0; } - - /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ - /* Chained Mode */ - /* Selects the next DMA Tx descriptor list for next buffer to send */ - dma_tx_desc_to_set = (emac_dma_desc_type*) (dma_tx_desc_to_set->buf2nextdescaddr); - /* Return SUCCESS */ + return SUCCESS; } diff --git a/middlewares/3rd_party/lwip_2.1.2/src/include/lwip/arch.h b/middlewares/3rd_party/lwip_2.1.2/src/include/lwip/arch.h index bbdd0d11..4f741e2e 100644 --- a/middlewares/3rd_party/lwip_2.1.2/src/include/lwip/arch.h +++ b/middlewares/3rd_party/lwip_2.1.2/src/include/lwip/arch.h @@ -45,7 +45,7 @@ #define BIG_ENDIAN 4321 #endif -//#include "arch/cc.h" +#include "arch/cc.h" /** * @defgroup compiler_abstraction Compiler/platform abstraction diff --git a/middlewares/3rd_party/lwip_2.1.2/src/include/lwip/debug.h b/middlewares/3rd_party/lwip_2.1.2/src/include/lwip/debug.h index 809e26ec..e621e4a6 100644 --- a/middlewares/3rd_party/lwip_2.1.2/src/include/lwip/debug.h +++ b/middlewares/3rd_party/lwip_2.1.2/src/include/lwip/debug.h @@ -111,7 +111,6 @@ /** * @} */ -#define LWIP_NOASSERT #ifndef LWIP_NOASSERT #define LWIP_ASSERT(message, assertion) do { if (!(assertion)) { \ diff --git a/middlewares/freertos/source/include/portable.h b/middlewares/freertos/source/include/portable.h index 4f4c1d52..4c16cb9d 100644 --- a/middlewares/freertos/source/include/portable.h +++ b/middlewares/freertos/source/include/portable.h @@ -50,7 +50,6 @@ #ifndef portENTER_CRITICAL #include "portmacro.h" #endif - #if portBYTE_ALIGNMENT == 32 #define portBYTE_ALIGNMENT_MASK ( 0x001f ) #endif diff --git a/middlewares/usb_drivers/src/usbd_sdr.c b/middlewares/usb_drivers/src/usbd_sdr.c index 1f506d5a..2c65a84a 100644 --- a/middlewares/usb_drivers/src/usbd_sdr.c +++ b/middlewares/usb_drivers/src/usbd_sdr.c @@ -156,6 +156,7 @@ static usb_sts_type usbd_set_address(usbd_core_type *udev) else { udev->device_addr = dev_addr; + usbd_set_device_addr(udev, udev->device_addr); if(dev_addr != 0) { diff --git a/middlewares/usb_drivers/src/usbh_ctrl.c b/middlewares/usb_drivers/src/usbh_ctrl.c index 78ad15ae..238cc92b 100644 --- a/middlewares/usb_drivers/src/usbh_ctrl.c +++ b/middlewares/usb_drivers/src/usbh_ctrl.c @@ -159,6 +159,7 @@ usb_sts_type usbh_ctrl_setup_wait_handler(usbh_core_type *uhost, uint32_t *timeo uhost->ctrl.state = CONTROL_STATUS_IN; } } + uhost->ctrl.timer = uhost->timer; status = USB_OK; } else if(urb_state == URB_ERROR || urb_state == URB_NOTREADY) @@ -279,15 +280,13 @@ usb_sts_type usbh_ctrl_data_out_wait_handler(usbh_core_type *uhost, uint32_t tim { uhost->ctrl.state = CONTROL_DATA_OUT; } - else + + /* wait nak timeout 5s*/ + if((uhost->timer - uhost->ctrl.timer > CTRL_TIMEOUT) && (urb_state == URB_NOTREADY)) { - /* wait nak timeout 5s*/ - if(uhost->timer - uhost->ctrl.timer > CTRL_TIMEOUT) - { - uhost->ctrl.state = CONTROL_ERROR; - uhost->ctrl.sts = CTRL_XACTERR; - status = USB_ERROR; - } + uhost->ctrl.state = CONTROL_ERROR; + uhost->ctrl.sts = CTRL_XACTERR; + status = USB_ERROR; } return status; } @@ -388,15 +387,12 @@ usb_sts_type usbh_ctrl_status_out_wait_handler(usbh_core_type *uhost, uint32_t t { uhost->ctrl.state = CONTROL_STATUS_OUT; } - else + /* wait nak timeout 5s*/ + if((uhost->timer - uhost->ctrl.timer > CTRL_TIMEOUT) && (urb_state == URB_NOTREADY)) { - /* wait nak timeout 5s*/ - if(uhost->timer - uhost->ctrl.timer > CTRL_TIMEOUT) - { - uhost->ctrl.state = CONTROL_ERROR; - uhost->ctrl.sts = CTRL_XACTERR; - status = USB_ERROR; - } + uhost->ctrl.state = CONTROL_ERROR; + uhost->ctrl.sts = CTRL_XACTERR; + status = USB_ERROR; } return status; } @@ -468,7 +464,6 @@ usb_sts_type usbh_ctrl_transfer_loop(usbh_core_type *uhost) case CONTROL_DATA_IN: usbh_ctrl_data_in_handler(uhost); - uhost->ctrl.timer = uhost->timer; break; case CONTROL_DATA_IN_WAIT: @@ -477,7 +472,6 @@ usb_sts_type usbh_ctrl_transfer_loop(usbh_core_type *uhost) case CONTROL_DATA_OUT: usbh_ctrl_data_out_handler(uhost); - uhost->ctrl.timer = uhost->timer; break; case CONTROL_DATA_OUT_WAIT: @@ -486,7 +480,6 @@ usb_sts_type usbh_ctrl_transfer_loop(usbh_core_type *uhost) case CONTROL_STATUS_IN: usbh_ctrl_status_in_handler(uhost); - uhost->ctrl.timer = uhost->timer; break; case CONTROL_STATUS_IN_WAIT: @@ -495,7 +488,6 @@ usb_sts_type usbh_ctrl_transfer_loop(usbh_core_type *uhost) case CONTROL_STATUS_OUT: usbh_ctrl_status_out_handler(uhost); - uhost->ctrl.timer = uhost->timer; break; case CONTROL_STATUS_OUT_WAIT: diff --git a/project/at_start_f435/examples/acc/calibration/inc/at32f435_437_conf.h b/project/at_start_f435/examples/acc/calibration/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/acc/calibration/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/acc/calibration/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/acc/calibration/inc/usb_conf.h b/project/at_start_f435/examples/acc/calibration/inc/usb_conf.h index 1c7174a6..5f7a8e09 100644 --- a/project/at_start_f435/examples/acc/calibration/inc/usb_conf.h +++ b/project/at_start_f435/examples/acc/calibration/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/acc/calibration/mdk_v5/calibration.uvoptx b/project/at_start_f435/examples/acc/calibration/mdk_v5/calibration.uvoptx index a2124ae0..31021bc6 100644 --- a/project/at_start_f435/examples/acc/calibration/mdk_v5/calibration.uvoptx +++ b/project/at_start_f435/examples/acc/calibration/mdk_v5/calibration.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/acc/calibration/mdk_v5/calibration.uvprojx b/project/at_start_f435/examples/acc/calibration/mdk_v5/calibration.uvprojx index f5cd377f..5389cc47 100644 --- a/project/at_start_f435/examples/acc/calibration/mdk_v5/calibration.uvprojx +++ b/project/at_start_f435/examples/acc/calibration/mdk_v5/calibration.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -629,4 +629,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/acc/calibration/src/at32f435_437_clock.c b/project/at_start_f435/examples/acc/calibration/src/at32f435_437_clock.c index 4ee4dc65..a194983a 100644 --- a/project/at_start_f435/examples/acc/calibration/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/acc/calibration/src/at32f435_437_clock.c @@ -45,6 +45,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -54,9 +57,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - /* enable hick */ crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); diff --git a/project/at_start_f435/examples/acc/calibration/src/main.c b/project/at_start_f435/examples/acc/calibration/src/main.c index 0b4ff9f2..1ba8b28e 100644 --- a/project/at_start_f435/examples/acc/calibration/src/main.c +++ b/project/at_start_f435/examples/acc/calibration/src/main.c @@ -83,7 +83,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/mdk_v5/combine_mode_ordinary_shift_twoslave_dma3.uvoptx b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/mdk_v5/combine_mode_ordinary_shift_twoslave_dma3.uvoptx index b5cf9be8..0b2ead66 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/mdk_v5/combine_mode_ordinary_shift_twoslave_dma3.uvoptx +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/mdk_v5/combine_mode_ordinary_shift_twoslave_dma3.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/mdk_v5/combine_mode_ordinary_shift_twoslave_dma3.uvprojx b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/mdk_v5/combine_mode_ordinary_shift_twoslave_dma3.uvprojx index e7ccf0b1..1f3313c7 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/mdk_v5/combine_mode_ordinary_shift_twoslave_dma3.uvprojx +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/mdk_v5/combine_mode_ordinary_shift_twoslave_dma3.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/mdk_v5/combine_mode_ordinary_shift_twoslave_dma4.uvoptx b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/mdk_v5/combine_mode_ordinary_shift_twoslave_dma4.uvoptx index 664adc15..3be3c0a6 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/mdk_v5/combine_mode_ordinary_shift_twoslave_dma4.uvoptx +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/mdk_v5/combine_mode_ordinary_shift_twoslave_dma4.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/mdk_v5/combine_mode_ordinary_shift_twoslave_dma4.uvprojx b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/mdk_v5/combine_mode_ordinary_shift_twoslave_dma4.uvprojx index 64ef25f5..fda403d8 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/mdk_v5/combine_mode_ordinary_shift_twoslave_dma4.uvprojx +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/mdk_v5/combine_mode_ordinary_shift_twoslave_dma4.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/mdk_v5/combine_mode_ordinary_smlt_oneslave_dma2.uvoptx b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/mdk_v5/combine_mode_ordinary_smlt_oneslave_dma2.uvoptx index 596cd2ad..9dfe4e80 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/mdk_v5/combine_mode_ordinary_smlt_oneslave_dma2.uvoptx +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/mdk_v5/combine_mode_ordinary_smlt_oneslave_dma2.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/mdk_v5/combine_mode_ordinary_smlt_oneslave_dma2.uvprojx b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/mdk_v5/combine_mode_ordinary_smlt_oneslave_dma2.uvprojx index 052fa2b3..9e75484f 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/mdk_v5/combine_mode_ordinary_smlt_oneslave_dma2.uvprojx +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/mdk_v5/combine_mode_ordinary_smlt_oneslave_dma2.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/mdk_v5/combine_mode_ordinary_smlt_oneslave_edma.uvoptx b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/mdk_v5/combine_mode_ordinary_smlt_oneslave_edma.uvoptx index 67ea9bac..4df7c0d2 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/mdk_v5/combine_mode_ordinary_smlt_oneslave_edma.uvoptx +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/mdk_v5/combine_mode_ordinary_smlt_oneslave_edma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/mdk_v5/combine_mode_ordinary_smlt_oneslave_edma.uvprojx b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/mdk_v5/combine_mode_ordinary_smlt_oneslave_edma.uvprojx index 172af64d..b71aca91 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/mdk_v5/combine_mode_ordinary_smlt_oneslave_edma.uvprojx +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/mdk_v5/combine_mode_ordinary_smlt_oneslave_edma.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma1.uvoptx b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma1.uvoptx index 939e6907..579a1954 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma1.uvoptx +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma1.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma1.uvprojx b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma1.uvprojx index ca9810cd..ce654f16 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma1.uvprojx +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma1.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma5.uvoptx b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma5.uvoptx index 712994e2..4b0c5c24 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma5.uvoptx +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma5.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma5.uvprojx b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma5.uvprojx index c13103aa..ac744f45 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma5.uvprojx +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma5.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/mdk_v5/combine_mode_preempt_interltrig_twoslave.uvoptx b/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/mdk_v5/combine_mode_preempt_interltrig_twoslave.uvoptx index 22e98cb0..27a01b5e 100644 --- a/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/mdk_v5/combine_mode_preempt_interltrig_twoslave.uvoptx +++ b/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/mdk_v5/combine_mode_preempt_interltrig_twoslave.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/mdk_v5/combine_mode_preempt_interltrig_twoslave.uvprojx b/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/mdk_v5/combine_mode_preempt_interltrig_twoslave.uvprojx index 66451148..8d715967 100644 --- a/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/mdk_v5/combine_mode_preempt_interltrig_twoslave.uvprojx +++ b/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/mdk_v5/combine_mode_preempt_interltrig_twoslave.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/conversion_abort/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/conversion_abort/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/conversion_abort/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/conversion_abort/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/conversion_abort/mdk_v5/conversion_abort.uvoptx b/project/at_start_f435/examples/adc/conversion_abort/mdk_v5/conversion_abort.uvoptx index 7b3ea8e6..c143c8ef 100644 --- a/project/at_start_f435/examples/adc/conversion_abort/mdk_v5/conversion_abort.uvoptx +++ b/project/at_start_f435/examples/adc/conversion_abort/mdk_v5/conversion_abort.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/conversion_abort/mdk_v5/conversion_abort.uvprojx b/project/at_start_f435/examples/adc/conversion_abort/mdk_v5/conversion_abort.uvprojx index 129d0a54..346f3b27 100644 --- a/project/at_start_f435/examples/adc/conversion_abort/mdk_v5/conversion_abort.uvprojx +++ b/project/at_start_f435/examples/adc/conversion_abort/mdk_v5/conversion_abort.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/conversion_abort/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/conversion_abort/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/conversion_abort/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/conversion_abort/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/current_vref_value_check/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/current_vref_value_check/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/current_vref_value_check/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/current_vref_value_check/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvoptx b/project/at_start_f435/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvoptx index 15ec8262..5dd45f7b 100644 --- a/project/at_start_f435/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvoptx +++ b/project/at_start_f435/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvprojx b/project/at_start_f435/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvprojx index b755bab9..a0056679 100644 --- a/project/at_start_f435/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvprojx +++ b/project/at_start_f435/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/current_vref_value_check/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/current_vref_value_check/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/current_vref_value_check/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/current_vref_value_check/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/edma_double_buffer/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/edma_double_buffer/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/edma_double_buffer/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/edma_double_buffer/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/edma_double_buffer/mdk_v5/edma_double_buffer.uvoptx b/project/at_start_f435/examples/adc/edma_double_buffer/mdk_v5/edma_double_buffer.uvoptx index fcd9cbfa..beaf9184 100644 --- a/project/at_start_f435/examples/adc/edma_double_buffer/mdk_v5/edma_double_buffer.uvoptx +++ b/project/at_start_f435/examples/adc/edma_double_buffer/mdk_v5/edma_double_buffer.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/edma_double_buffer/mdk_v5/edma_double_buffer.uvprojx b/project/at_start_f435/examples/adc/edma_double_buffer/mdk_v5/edma_double_buffer.uvprojx index eb79736d..6a4b7bab 100644 --- a/project/at_start_f435/examples/adc/edma_double_buffer/mdk_v5/edma_double_buffer.uvprojx +++ b/project/at_start_f435/examples/adc/edma_double_buffer/mdk_v5/edma_double_buffer.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/edma_double_buffer/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/edma_double_buffer/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/edma_double_buffer/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/edma_double_buffer/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/exint_trigger_partitioned/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/exint_trigger_partitioned/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/exint_trigger_partitioned/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/exint_trigger_partitioned/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvoptx b/project/at_start_f435/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvoptx index e6c30734..156030ee 100644 --- a/project/at_start_f435/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvoptx +++ b/project/at_start_f435/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvprojx b/project/at_start_f435/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvprojx index 207509c7..a94d44f4 100644 --- a/project/at_start_f435/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvprojx +++ b/project/at_start_f435/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/exint_trigger_partitioned/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/exint_trigger_partitioned/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/exint_trigger_partitioned/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/exint_trigger_partitioned/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/internal_temperature_sensor/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/internal_temperature_sensor/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/internal_temperature_sensor/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/internal_temperature_sensor/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvoptx b/project/at_start_f435/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvoptx index bd5ab64b..1f4dee16 100644 --- a/project/at_start_f435/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvoptx +++ b/project/at_start_f435/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvprojx b/project/at_start_f435/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvprojx index 2e95d399..4cc089b8 100644 --- a/project/at_start_f435/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvprojx +++ b/project/at_start_f435/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/internal_temperature_sensor/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/internal_temperature_sensor/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/internal_temperature_sensor/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/internal_temperature_sensor/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/mdk_v5/ordinary_preempt_oversampling.uvoptx b/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/mdk_v5/ordinary_preempt_oversampling.uvoptx index da28ae85..8ce16131 100644 --- a/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/mdk_v5/ordinary_preempt_oversampling.uvoptx +++ b/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/mdk_v5/ordinary_preempt_oversampling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/mdk_v5/ordinary_preempt_oversampling.uvprojx b/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/mdk_v5/ordinary_preempt_oversampling.uvprojx index 10a0d7db..3fc3f65c 100644 --- a/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/mdk_v5/ordinary_preempt_oversampling.uvprojx +++ b/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/mdk_v5/ordinary_preempt_oversampling.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/ordinary_preempt_oversampling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvoptx b/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvoptx index c352c783..6969c9b9 100644 --- a/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvoptx +++ b/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvprojx b/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvprojx index 359e70ed..9a54c529 100644 --- a/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvprojx +++ b/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/src/at32f435_437_clock.c index aae8677c..cdf22df3 100644 --- a/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/resolution_6bit/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/resolution_6bit/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/resolution_6bit/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/resolution_6bit/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/resolution_6bit/mdk_v5/resolution_6bit.uvoptx b/project/at_start_f435/examples/adc/resolution_6bit/mdk_v5/resolution_6bit.uvoptx index 0ea45ca1..91b2cca1 100644 --- a/project/at_start_f435/examples/adc/resolution_6bit/mdk_v5/resolution_6bit.uvoptx +++ b/project/at_start_f435/examples/adc/resolution_6bit/mdk_v5/resolution_6bit.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/resolution_6bit/mdk_v5/resolution_6bit.uvprojx b/project/at_start_f435/examples/adc/resolution_6bit/mdk_v5/resolution_6bit.uvprojx index 336bebb9..856fe0f2 100644 --- a/project/at_start_f435/examples/adc/resolution_6bit/mdk_v5/resolution_6bit.uvprojx +++ b/project/at_start_f435/examples/adc/resolution_6bit/mdk_v5/resolution_6bit.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/resolution_6bit/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/resolution_6bit/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/resolution_6bit/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/resolution_6bit/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/software_trigger_repeat/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/software_trigger_repeat/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/software_trigger_repeat/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/software_trigger_repeat/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvoptx b/project/at_start_f435/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvoptx index 0ea45ca1..91b2cca1 100644 --- a/project/at_start_f435/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvoptx +++ b/project/at_start_f435/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvprojx b/project/at_start_f435/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvprojx index 0f7b5c2b..79bcb033 100644 --- a/project/at_start_f435/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvprojx +++ b/project/at_start_f435/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/software_trigger_repeat/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/software_trigger_repeat/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/software_trigger_repeat/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/software_trigger_repeat/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvoptx b/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvoptx index 251ef2d8..1ba4aa90 100644 --- a/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvoptx +++ b/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvprojx b/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvprojx index 701d08b6..939e0820 100644 --- a/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvprojx +++ b/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/use_polling_get_conversion_data/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/use_polling_get_conversion_data/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/use_polling_get_conversion_data/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/use_polling_get_conversion_data/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/use_polling_get_conversion_data/mdk_v5/use_polling_get_conversion_data.uvoptx b/project/at_start_f435/examples/adc/use_polling_get_conversion_data/mdk_v5/use_polling_get_conversion_data.uvoptx index baa2768e..8ae49d27 100644 --- a/project/at_start_f435/examples/adc/use_polling_get_conversion_data/mdk_v5/use_polling_get_conversion_data.uvoptx +++ b/project/at_start_f435/examples/adc/use_polling_get_conversion_data/mdk_v5/use_polling_get_conversion_data.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/use_polling_get_conversion_data/mdk_v5/use_polling_get_conversion_data.uvprojx b/project/at_start_f435/examples/adc/use_polling_get_conversion_data/mdk_v5/use_polling_get_conversion_data.uvprojx index 4159d766..966cbd24 100644 --- a/project/at_start_f435/examples/adc/use_polling_get_conversion_data/mdk_v5/use_polling_get_conversion_data.uvprojx +++ b/project/at_start_f435/examples/adc/use_polling_get_conversion_data/mdk_v5/use_polling_get_conversion_data.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/use_polling_get_conversion_data/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/use_polling_get_conversion_data/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/use_polling_get_conversion_data/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/use_polling_get_conversion_data/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/vbat_monitor/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/vbat_monitor/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/vbat_monitor/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/vbat_monitor/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/vbat_monitor/mdk_v5/vbat_monitor.uvoptx b/project/at_start_f435/examples/adc/vbat_monitor/mdk_v5/vbat_monitor.uvoptx index 071b1204..36fa0e18 100644 --- a/project/at_start_f435/examples/adc/vbat_monitor/mdk_v5/vbat_monitor.uvoptx +++ b/project/at_start_f435/examples/adc/vbat_monitor/mdk_v5/vbat_monitor.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/vbat_monitor/mdk_v5/vbat_monitor.uvprojx b/project/at_start_f435/examples/adc/vbat_monitor/mdk_v5/vbat_monitor.uvprojx index 50729f01..56a41ab2 100644 --- a/project/at_start_f435/examples/adc/vbat_monitor/mdk_v5/vbat_monitor.uvprojx +++ b/project/at_start_f435/examples/adc/vbat_monitor/mdk_v5/vbat_monitor.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/vbat_monitor/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/vbat_monitor/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/vbat_monitor/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/vbat_monitor/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/adc/voltage_monitoring/inc/at32f435_437_conf.h b/project/at_start_f435/examples/adc/voltage_monitoring/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/adc/voltage_monitoring/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/adc/voltage_monitoring/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvoptx b/project/at_start_f435/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvoptx index 99fcc3f1..0c95fc16 100644 --- a/project/at_start_f435/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvoptx +++ b/project/at_start_f435/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvprojx b/project/at_start_f435/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvprojx index 8fd285c8..cfc4ace9 100644 --- a/project/at_start_f435/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvprojx +++ b/project/at_start_f435/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/adc/voltage_monitoring/src/at32f435_437_clock.c b/project/at_start_f435/examples/adc/voltage_monitoring/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/adc/voltage_monitoring/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/adc/voltage_monitoring/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/can/communication_mode/inc/at32f435_437_conf.h b/project/at_start_f435/examples/can/communication_mode/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/can/communication_mode/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/can/communication_mode/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/can/communication_mode/mdk_v5/communication_mode.uvoptx b/project/at_start_f435/examples/can/communication_mode/mdk_v5/communication_mode.uvoptx index 77358118..71151ca6 100644 --- a/project/at_start_f435/examples/can/communication_mode/mdk_v5/communication_mode.uvoptx +++ b/project/at_start_f435/examples/can/communication_mode/mdk_v5/communication_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/can/communication_mode/mdk_v5/communication_mode.uvprojx b/project/at_start_f435/examples/can/communication_mode/mdk_v5/communication_mode.uvprojx index d47294fb..b717e6cf 100644 --- a/project/at_start_f435/examples/can/communication_mode/mdk_v5/communication_mode.uvprojx +++ b/project/at_start_f435/examples/can/communication_mode/mdk_v5/communication_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/can/communication_mode/src/at32f435_437_clock.c b/project/at_start_f435/examples/can/communication_mode/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/can/communication_mode/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/can/communication_mode/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/can/filter/inc/at32f435_437_conf.h b/project/at_start_f435/examples/can/filter/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/can/filter/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/can/filter/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/can/filter/mdk_v5/filter.uvoptx b/project/at_start_f435/examples/can/filter/mdk_v5/filter.uvoptx index cd775dbd..1fb00418 100644 --- a/project/at_start_f435/examples/can/filter/mdk_v5/filter.uvoptx +++ b/project/at_start_f435/examples/can/filter/mdk_v5/filter.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/can/filter/mdk_v5/filter.uvprojx b/project/at_start_f435/examples/can/filter/mdk_v5/filter.uvprojx index b32327f9..abda4e93 100644 --- a/project/at_start_f435/examples/can/filter/mdk_v5/filter.uvprojx +++ b/project/at_start_f435/examples/can/filter/mdk_v5/filter.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/can/filter/src/at32f435_437_clock.c b/project/at_start_f435/examples/can/filter/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/can/filter/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/can/filter/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/can/loopback_mode/inc/at32f435_437_conf.h b/project/at_start_f435/examples/can/loopback_mode/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/can/loopback_mode/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/can/loopback_mode/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/can/loopback_mode/mdk_v5/loopback_mode.uvoptx b/project/at_start_f435/examples/can/loopback_mode/mdk_v5/loopback_mode.uvoptx index d9c1dcbd..77af98b0 100644 --- a/project/at_start_f435/examples/can/loopback_mode/mdk_v5/loopback_mode.uvoptx +++ b/project/at_start_f435/examples/can/loopback_mode/mdk_v5/loopback_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/can/loopback_mode/mdk_v5/loopback_mode.uvprojx b/project/at_start_f435/examples/can/loopback_mode/mdk_v5/loopback_mode.uvprojx index 3b626a09..df34c944 100644 --- a/project/at_start_f435/examples/can/loopback_mode/mdk_v5/loopback_mode.uvprojx +++ b/project/at_start_f435/examples/can/loopback_mode/mdk_v5/loopback_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/can/loopback_mode/src/at32f435_437_clock.c b/project/at_start_f435/examples/can/loopback_mode/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/can/loopback_mode/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/can/loopback_mode/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/cortex_m4/bit_band/inc/at32f435_437_conf.h b/project/at_start_f435/examples/cortex_m4/bit_band/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/cortex_m4/bit_band/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/cortex_m4/bit_band/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvoptx b/project/at_start_f435/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvoptx index 464533cb..5d2a393b 100644 --- a/project/at_start_f435/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvoptx +++ b/project/at_start_f435/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvprojx b/project/at_start_f435/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvprojx index 90be13fa..dcea7d6b 100644 --- a/project/at_start_f435/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvprojx +++ b/project/at_start_f435/examples/cortex_m4/bit_band/mdk_v5/bit_band.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/cortex_m4/bit_band/src/at32f435_437_clock.c b/project/at_start_f435/examples/cortex_m4/bit_band/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/cortex_m4/bit_band/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/cortex_m4/bit_band/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/inc/at32f435_437_conf.h b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/inc/at32f435_437_conf.h index 44a46964..9c52a658 100644 --- a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/inc/at32f435_437_conf.h @@ -55,8 +55,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Listings/cmsis_dsp.map b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Listings/cmsis_dsp.map index cb217c49..60c06c63 100644 --- a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Listings/cmsis_dsp.map +++ b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Listings/cmsis_dsp.map @@ -1,4 +1,4 @@ -Component: ARM Compiler 6.16 Tool: armlink [5dfeaa00] +Component: ARM Compiler 6.14 Tool: armlink [5db06800] ============================================================================== @@ -92,8 +92,8 @@ Section Cross References at32f435_437_int.o(.ARM.exidx.text.DebugMon_Handler) refers to at32f435_437_int.o(.text.DebugMon_Handler) for [Anonymous Symbol] at32f435_437_int.o(.ARM.exidx.text.PendSV_Handler) refers to at32f435_437_int.o(.text.PendSV_Handler) for [Anonymous Symbol] at32f435_437_int.o(.ARM.exidx.text.SysTick_Handler) refers to at32f435_437_int.o(.text.SysTick_Handler) for [Anonymous Symbol] - at32f435_437_clock.o(.text.system_clock_config) refers to at32f435_437_crm.o(.text.crm_periph_clock_enable) for crm_periph_clock_enable at32f435_437_clock.o(.text.system_clock_config) refers to at32f435_437_crm.o(.text.crm_reset) for crm_reset + at32f435_437_clock.o(.text.system_clock_config) refers to at32f435_437_crm.o(.text.crm_periph_clock_enable) for crm_periph_clock_enable at32f435_437_clock.o(.text.system_clock_config) refers to at32f435_437_crm.o(.text.crm_clock_source_enable) for crm_clock_source_enable at32f435_437_clock.o(.text.system_clock_config) refers to at32f435_437_crm.o(.text.crm_hext_stable_wait) for crm_hext_stable_wait at32f435_437_clock.o(.text.system_clock_config) refers to at32f435_437_crm.o(.text.crm_pll_config) for crm_pll_config @@ -883,6 +883,7 @@ Section Cross References statisticsfunctions.o(.text.arm_entropy_f64) refers to log.o(i.__hardfp_log) for __hardfp_log statisticsfunctions.o(.text.arm_entropy_f64) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul statisticsfunctions.o(.text.arm_entropy_f64) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + statisticsfunctions.o(.text.arm_entropy_f64) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub statisticsfunctions.o(.ARM.exidx.text.arm_entropy_f64) refers to statisticsfunctions.o(.text.arm_entropy_f64) for [Anonymous Symbol] statisticsfunctions.o(.text.arm_kullback_leibler_f32) refers to logf.o(i.__hardfp_logf) for __hardfp_logf statisticsfunctions.o(.ARM.exidx.text.arm_kullback_leibler_f32) refers to statisticsfunctions.o(.text.arm_kullback_leibler_f32) for [Anonymous Symbol] @@ -890,6 +891,7 @@ Section Cross References statisticsfunctions.o(.text.arm_kullback_leibler_f64) refers to log.o(i.__hardfp_log) for __hardfp_log statisticsfunctions.o(.text.arm_kullback_leibler_f64) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul statisticsfunctions.o(.text.arm_kullback_leibler_f64) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + statisticsfunctions.o(.text.arm_kullback_leibler_f64) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub statisticsfunctions.o(.ARM.exidx.text.arm_kullback_leibler_f64) refers to statisticsfunctions.o(.text.arm_kullback_leibler_f64) for [Anonymous Symbol] statisticsfunctions.o(.text.arm_logsumexp_dot_prod_f32) refers to basicmathfunctions.o(.text.arm_add_f32) for arm_add_f32 statisticsfunctions.o(.text.arm_logsumexp_dot_prod_f32) refers to statisticsfunctions.o(.text.arm_logsumexp_f32) for arm_logsumexp_f32 @@ -1028,6 +1030,7 @@ Section Cross References transformfunctions.o(.text.arm_cfft_radix4by2_f64) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul transformfunctions.o(.text.arm_cfft_radix4by2_f64) refers to transformfunctions.o(.text.arm_radix4_butterfly_f64) for arm_radix4_butterfly_f64 transformfunctions.o(.ARM.exidx.text.arm_cfft_radix4by2_f64) refers to transformfunctions.o(.text.arm_cfft_radix4by2_f64) for [Anonymous Symbol] + transformfunctions.o(.text.arm_cfft_f64) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub transformfunctions.o(.text.arm_cfft_f64) refers to transformfunctions.o(.text.arm_cfft_radix4by2_f64) for arm_cfft_radix4by2_f64 transformfunctions.o(.text.arm_cfft_f64) refers to transformfunctions.o(.text.arm_bitreversal_64) for arm_bitreversal_64 transformfunctions.o(.text.arm_cfft_f64) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d @@ -1409,6 +1412,15 @@ Section Cross References expf.o(i.expf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp expf.o(i.expf) refers to expf.o(i.__hardfp_expf) for __hardfp_expf expf.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + expf_x.o(i.____hardfp_expf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + expf_x.o(i.____hardfp_expf$lsc) refers to _rserrno.o(.text) for __set_errno + expf_x.o(i.____hardfp_expf$lsc) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan + expf_x.o(i.____hardfp_expf$lsc) refers to expf_x.o(.constdata) for .constdata + expf_x.o(i.____softfp_expf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + expf_x.o(i.____softfp_expf$lsc) refers to expf_x.o(i.____hardfp_expf$lsc) for ____hardfp_expf$lsc + expf_x.o(i.__expf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + expf_x.o(i.__expf$lsc) refers to expf_x.o(i.____hardfp_expf$lsc) for ____hardfp_expf$lsc + expf_x.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp log.o(i.__hardfp_log) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp log.o(i.__hardfp_log) refers to dunder.o(i.__mathlib_dbl_infnan) for __mathlib_dbl_infnan log.o(i.__hardfp_log) refers to _rserrno.o(.text) for __set_errno @@ -1430,6 +1442,24 @@ Section Cross References log.o(i.log) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp log.o(i.log) refers to log.o(i.__hardfp_log) for __hardfp_log log.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + log_x.o(i.____hardfp_log$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + log_x.o(i.____hardfp_log$lsc) refers to dunder.o(i.__mathlib_dbl_infnan) for __mathlib_dbl_infnan + log_x.o(i.____hardfp_log$lsc) refers to _rserrno.o(.text) for __set_errno + log_x.o(i.____hardfp_log$lsc) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + log_x.o(i.____hardfp_log$lsc) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub + log_x.o(i.____hardfp_log$lsc) refers to deqf.o(x$fpl$deqf) for __aeabi_cdcmpeq + log_x.o(i.____hardfp_log$lsc) refers to dflt_clz.o(x$fpl$dflt) for __aeabi_i2d + log_x.o(i.____hardfp_log$lsc) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + log_x.o(i.____hardfp_log$lsc) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub + log_x.o(i.____hardfp_log$lsc) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + log_x.o(i.____hardfp_log$lsc) refers to poly.o(i.__kernel_poly) for __kernel_poly + log_x.o(i.____hardfp_log$lsc) refers to qnan.o(.constdata) for __mathlib_zero + log_x.o(i.____hardfp_log$lsc) refers to log_x.o(.constdata) for .constdata + log_x.o(i.____softfp_log$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + log_x.o(i.____softfp_log$lsc) refers to log_x.o(i.____hardfp_log$lsc) for ____hardfp_log$lsc + log_x.o(i.__log$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + log_x.o(i.__log$lsc) refers to log_x.o(i.____hardfp_log$lsc) for ____hardfp_log$lsc + log_x.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp logf.o(i.__hardfp_logf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp logf.o(i.__hardfp_logf) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan logf.o(i.__hardfp_logf) refers to _rserrno.o(.text) for __set_errno @@ -1441,6 +1471,15 @@ Section Cross References logf.o(i.logf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp logf.o(i.logf) refers to logf.o(i.__hardfp_logf) for __hardfp_logf logf.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + logf_x.o(i.____hardfp_logf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + logf_x.o(i.____hardfp_logf$lsc) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan + logf_x.o(i.____hardfp_logf$lsc) refers to _rserrno.o(.text) for __set_errno + logf_x.o(i.____hardfp_logf$lsc) refers to logf_x.o(.constdata) for .constdata + logf_x.o(i.____softfp_logf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + logf_x.o(i.____softfp_logf$lsc) refers to logf_x.o(i.____hardfp_logf$lsc) for ____hardfp_logf$lsc + logf_x.o(i.__logf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + logf_x.o(i.__logf$lsc) refers to logf_x.o(i.____hardfp_logf$lsc) for ____hardfp_logf$lsc + logf_x.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp powf.o(i.__hardfp_powf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp powf.o(i.__hardfp_powf) refers to _rserrno.o(.text) for __set_errno powf.o(i.__hardfp_powf) refers to funder.o(i.__mathlib_flt_overflow) for __mathlib_flt_overflow @@ -1455,12 +1494,27 @@ Section Cross References powf.o(i.powf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp powf.o(i.powf) refers to powf.o(i.__hardfp_powf) for __hardfp_powf powf.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + powf_x.o(i.____hardfp_powf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + powf_x.o(i.____hardfp_powf$lsc) refers to _rserrno.o(.text) for __set_errno + powf_x.o(i.____hardfp_powf$lsc) refers to powf_x.o(.constdata) for .constdata + powf_x.o(i.____hardfp_powf$lsc) refers to funder.o(i.__mathlib_flt_infnan2) for __mathlib_flt_infnan2 + powf_x.o(i.____softfp_powf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + powf_x.o(i.____softfp_powf$lsc) refers to powf_x.o(i.____hardfp_powf$lsc) for ____hardfp_powf$lsc + powf_x.o(i.__powf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + powf_x.o(i.__powf$lsc) refers to powf_x.o(i.____hardfp_powf$lsc) for ____hardfp_powf$lsc + powf_x.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp sqrtf.o(i.__hardfp_sqrtf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp sqrtf.o(i.__hardfp_sqrtf) refers to _rserrno.o(.text) for __set_errno sqrtf.o(i.__softfp_sqrtf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp sqrtf.o(i.__softfp_sqrtf) refers to _rserrno.o(.text) for __set_errno sqrtf.o(i.sqrtf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp sqrtf.o(i.sqrtf) refers to _rserrno.o(.text) for __set_errno + sqrtf_x.o(i.____hardfp_sqrtf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sqrtf_x.o(i.____hardfp_sqrtf$lsc) refers to _rserrno.o(.text) for __set_errno + sqrtf_x.o(i.____softfp_sqrtf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sqrtf_x.o(i.____softfp_sqrtf$lsc) refers to _rserrno.o(.text) for __set_errno + sqrtf_x.o(i.__sqrtf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sqrtf_x.o(i.__sqrtf$lsc) refers to _rserrno.o(.text) for __set_errno tanhf.o(i.__hardfp_tanhf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp tanhf.o(i.__hardfp_tanhf) refers to expf.o(i.__hardfp_expf) for __hardfp_expf tanhf.o(i.__hardfp_tanhf) refers to fpclassifyf.o(i.__ARM_fpclassifyf) for __ARM_fpclassifyf @@ -1470,6 +1524,13 @@ Section Cross References tanhf.o(i.__softfp_tanhf) refers to tanhf.o(i.__hardfp_tanhf) for __hardfp_tanhf tanhf.o(i.tanhf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp tanhf.o(i.tanhf) refers to tanhf.o(i.__hardfp_tanhf) for __hardfp_tanhf + tanhf_x.o(i.____hardfp_tanhf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + tanhf_x.o(i.____hardfp_tanhf$lsc) refers to expf.o(i.__hardfp_expf) for __hardfp_expf + tanhf_x.o(i.____hardfp_tanhf$lsc) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan + tanhf_x.o(i.____softfp_tanhf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + tanhf_x.o(i.____softfp_tanhf$lsc) refers to tanhf_x.o(i.____hardfp_tanhf$lsc) for ____hardfp_tanhf$lsc + tanhf_x.o(i.__tanhf$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + tanhf_x.o(i.__tanhf$lsc) refers to tanhf_x.o(i.____hardfp_tanhf$lsc) for ____hardfp_tanhf$lsc __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 @@ -1833,7 +1894,7 @@ Removing Unused input sections from the image. Removing at32f435_437_misc.o(.ARM.exidx.text.nvic_vector_table_set), (8 bytes). Removing at32f435_437_misc.o(.text.nvic_lowpower_mode_config), (24 bytes). Removing at32f435_437_misc.o(.ARM.exidx.text.nvic_lowpower_mode_config), (8 bytes). - Removing at32f435_437_misc.o(.text.systick_clock_source_config), (24 bytes). + Removing at32f435_437_misc.o(.text.systick_clock_source_config), (26 bytes). Removing at32f435_437_misc.o(.ARM.exidx.text.systick_clock_source_config), (8 bytes). Removing at32f435_437_usart.o(.text), (0 bytes). Removing at32f435_437_usart.o(.text.usart_reset), (224 bytes). @@ -1855,7 +1916,7 @@ Removing Unused input sections from the image. Removing at32f435_437_usart.o(.ARM.exidx.text.usart_dma_transmitter_enable), (8 bytes). Removing at32f435_437_usart.o(.text.usart_dma_receiver_enable), (18 bytes). Removing at32f435_437_usart.o(.ARM.exidx.text.usart_dma_receiver_enable), (8 bytes). - Removing at32f435_437_usart.o(.text.usart_wakeup_id_set), (46 bytes). + Removing at32f435_437_usart.o(.text.usart_wakeup_id_set), (38 bytes). Removing at32f435_437_usart.o(.ARM.exidx.text.usart_wakeup_id_set), (8 bytes). Removing at32f435_437_usart.o(.text.usart_wakeup_mode_set), (18 bytes). Removing at32f435_437_usart.o(.ARM.exidx.text.usart_wakeup_mode_set), (8 bytes). @@ -1902,11 +1963,11 @@ Removing Unused input sections from the image. Removing basicmathfunctions.o(.text), (0 bytes). Removing basicmathfunctions.o(.text.arm_abs_f32), (130 bytes). Removing basicmathfunctions.o(.ARM.exidx.text.arm_abs_f32), (8 bytes). - Removing basicmathfunctions.o(.text.arm_abs_q15), (132 bytes). + Removing basicmathfunctions.o(.text.arm_abs_q15), (136 bytes). Removing basicmathfunctions.o(.ARM.exidx.text.arm_abs_q15), (8 bytes). - Removing basicmathfunctions.o(.text.arm_abs_q31), (114 bytes). + Removing basicmathfunctions.o(.text.arm_abs_q31), (118 bytes). Removing basicmathfunctions.o(.ARM.exidx.text.arm_abs_q31), (8 bytes). - Removing basicmathfunctions.o(.text.arm_abs_q7), (132 bytes). + Removing basicmathfunctions.o(.text.arm_abs_q7), (136 bytes). Removing basicmathfunctions.o(.ARM.exidx.text.arm_abs_q7), (8 bytes). Removing basicmathfunctions.o(.text.arm_add_f32), (166 bytes). Removing basicmathfunctions.o(.ARM.exidx.text.arm_add_f32), (8 bytes). @@ -1932,11 +1993,11 @@ Removing Unused input sections from the image. Removing basicmathfunctions.o(.ARM.exidx.text.arm_dot_prod_q7), (8 bytes). Removing basicmathfunctions.o(.text.arm_mult_f32), (166 bytes). Removing basicmathfunctions.o(.ARM.exidx.text.arm_mult_f32), (8 bytes). - Removing basicmathfunctions.o(.text.arm_mult_q15), (134 bytes). + Removing basicmathfunctions.o(.text.arm_mult_q15), (150 bytes). Removing basicmathfunctions.o(.ARM.exidx.text.arm_mult_q15), (8 bytes). Removing basicmathfunctions.o(.text.arm_mult_q31), (166 bytes). Removing basicmathfunctions.o(.ARM.exidx.text.arm_mult_q31), (8 bytes). - Removing basicmathfunctions.o(.text.arm_mult_q7), (162 bytes). + Removing basicmathfunctions.o(.text.arm_mult_q7), (182 bytes). Removing basicmathfunctions.o(.ARM.exidx.text.arm_mult_q7), (8 bytes). Removing basicmathfunctions.o(.text.arm_negate_f32), (130 bytes). Removing basicmathfunctions.o(.ARM.exidx.text.arm_negate_f32), (8 bytes). @@ -2192,11 +2253,11 @@ Removing Unused input sections from the image. Removing complexmathfunctions.o(.ARM.exidx.text.arm_cmplx_conj_q31), (8 bytes). Removing complexmathfunctions.o(.text.arm_cmplx_dot_prod_f32), (348 bytes). Removing complexmathfunctions.o(.ARM.exidx.text.arm_cmplx_dot_prod_f32), (8 bytes). - Removing complexmathfunctions.o(.text.arm_cmplx_dot_prod_q15), (336 bytes). + Removing complexmathfunctions.o(.text.arm_cmplx_dot_prod_q15), (338 bytes). Removing complexmathfunctions.o(.ARM.exidx.text.arm_cmplx_dot_prod_q15), (8 bytes). - Removing complexmathfunctions.o(.text.arm_cmplx_dot_prod_q31), (662 bytes). + Removing complexmathfunctions.o(.text.arm_cmplx_dot_prod_q31), (656 bytes). Removing complexmathfunctions.o(.ARM.exidx.text.arm_cmplx_dot_prod_q31), (8 bytes). - Removing complexmathfunctions.o(.text.arm_cmplx_mag_f32), (316 bytes). + Removing complexmathfunctions.o(.text.arm_cmplx_mag_f32), (344 bytes). Removing complexmathfunctions.o(.ARM.exidx.text.arm_cmplx_mag_f32), (8 bytes). Removing complexmathfunctions.o(.text.arm_cmplx_mag_q15), (140 bytes). Removing complexmathfunctions.o(.ARM.exidx.text.arm_cmplx_mag_q15), (8 bytes). @@ -2216,7 +2277,7 @@ Removing Unused input sections from the image. Removing complexmathfunctions.o(.ARM.exidx.text.arm_cmplx_mult_cmplx_q31), (8 bytes). Removing complexmathfunctions.o(.text.arm_cmplx_mult_real_f32), (230 bytes). Removing complexmathfunctions.o(.ARM.exidx.text.arm_cmplx_mult_real_f32), (8 bytes). - Removing complexmathfunctions.o(.text.arm_cmplx_mult_real_q15), (214 bytes). + Removing complexmathfunctions.o(.text.arm_cmplx_mult_real_q15), (224 bytes). Removing complexmathfunctions.o(.ARM.exidx.text.arm_cmplx_mult_real_q15), (8 bytes). Removing complexmathfunctions.o(.text.arm_cmplx_mult_real_q31), (242 bytes). Removing complexmathfunctions.o(.ARM.exidx.text.arm_cmplx_mult_real_q31), (8 bytes). @@ -2235,38 +2296,38 @@ Removing Unused input sections from the image. Removing controllerfunctions.o(.ARM.exidx.text.arm_pid_reset_q31), (8 bytes). Removing controllerfunctions.o(.text.arm_sin_cos_f32), (292 bytes). Removing controllerfunctions.o(.ARM.exidx.text.arm_sin_cos_f32), (8 bytes). - Removing controllerfunctions.o(.text.arm_sin_cos_q31), (514 bytes). + Removing controllerfunctions.o(.text.arm_sin_cos_q31), (520 bytes). Removing controllerfunctions.o(.ARM.exidx.text.arm_sin_cos_q31), (8 bytes). Removing distancefunctions.o(.text), (0 bytes). - Removing distancefunctions.o(.text.arm_boolean_distance_TT_TF_FT), (170 bytes). + Removing distancefunctions.o(.text.arm_boolean_distance_TT_TF_FT), (186 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_boolean_distance_TT_TF_FT), (8 bytes). - Removing distancefunctions.o(.text.arm_boolean_distance_TF_FT), (148 bytes). + Removing distancefunctions.o(.text.arm_boolean_distance_TF_FT), (160 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_boolean_distance_TF_FT), (8 bytes). - Removing distancefunctions.o(.text.arm_boolean_distance_TT_FF_TF_FT), (226 bytes). + Removing distancefunctions.o(.text.arm_boolean_distance_TT_FF_TF_FT), (234 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_boolean_distance_TT_FF_TF_FT), (8 bytes). - Removing distancefunctions.o(.text.arm_boolean_distance_TT), (96 bytes). + Removing distancefunctions.o(.text.arm_boolean_distance_TT), (100 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_boolean_distance_TT), (8 bytes). Removing distancefunctions.o(.text.arm_braycurtis_distance_f32), (76 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_braycurtis_distance_f32), (8 bytes). - Removing distancefunctions.o(.text.arm_canberra_distance_f32), (104 bytes). + Removing distancefunctions.o(.text.arm_canberra_distance_f32), (108 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_canberra_distance_f32), (8 bytes). Removing distancefunctions.o(.text.arm_chebyshev_distance_f32), (72 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_chebyshev_distance_f32), (8 bytes). Removing distancefunctions.o(.text.arm_cityblock_distance_f32), (52 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_cityblock_distance_f32), (8 bytes). - Removing distancefunctions.o(.text.arm_correlation_distance_f32), (208 bytes). + Removing distancefunctions.o(.text.arm_correlation_distance_f32), (220 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_correlation_distance_f32), (8 bytes). - Removing distancefunctions.o(.text.arm_cosine_distance_f32), (116 bytes). + Removing distancefunctions.o(.text.arm_cosine_distance_f32), (128 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_cosine_distance_f32), (8 bytes). Removing distancefunctions.o(.text.arm_dice_distance), (126 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_dice_distance), (8 bytes). - Removing distancefunctions.o(.text.arm_euclidean_distance_f32), (88 bytes). + Removing distancefunctions.o(.text.arm_euclidean_distance_f32), (104 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_euclidean_distance_f32), (8 bytes). Removing distancefunctions.o(.text.arm_hamming_distance), (68 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_hamming_distance), (8 bytes). Removing distancefunctions.o(.text.arm_jaccard_distance), (74 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_jaccard_distance), (8 bytes). - Removing distancefunctions.o(.text.arm_jensenshannon_distance_f32), (164 bytes). + Removing distancefunctions.o(.text.arm_jensenshannon_distance_f32), (176 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_jensenshannon_distance_f32), (8 bytes). Removing distancefunctions.o(.text.rel_entr), (28 bytes). Removing distancefunctions.o(.ARM.exidx.text.rel_entr), (8 bytes). @@ -2278,7 +2339,7 @@ Removing Unused input sections from the image. Removing distancefunctions.o(.ARM.exidx.text.arm_rogerstanimoto_distance), (8 bytes). Removing distancefunctions.o(.text.arm_russellrao_distance), (70 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_russellrao_distance), (8 bytes). - Removing distancefunctions.o(.text.arm_sokalmichener_distance), (90 bytes). + Removing distancefunctions.o(.text.arm_sokalmichener_distance), (102 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_sokalmichener_distance), (8 bytes). Removing distancefunctions.o(.text.arm_sokalsneath_distance), (76 bytes). Removing distancefunctions.o(.ARM.exidx.text.arm_sokalsneath_distance), (8 bytes). @@ -2308,13 +2369,13 @@ Removing Unused input sections from the image. Removing filteringfunctions.o(.text), (0 bytes). Removing filteringfunctions.o(.text.arm_biquad_cas_df1_32x64_init_q31), (26 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cas_df1_32x64_init_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_biquad_cas_df1_32x64_q31), (884 bytes). + Removing filteringfunctions.o(.text.arm_biquad_cas_df1_32x64_q31), (898 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cas_df1_32x64_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_biquad_cascade_df1_f32), (410 bytes). + Removing filteringfunctions.o(.text.arm_biquad_cascade_df1_f32), (406 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_df1_f32), (8 bytes). - Removing filteringfunctions.o(.text.arm_biquad_cascade_df1_fast_q15), (260 bytes). + Removing filteringfunctions.o(.text.arm_biquad_cascade_df1_fast_q15), (276 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_df1_fast_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_biquad_cascade_df1_fast_q31), (408 bytes). + Removing filteringfunctions.o(.text.arm_biquad_cascade_df1_fast_q31), (412 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_df1_fast_q31), (8 bytes). Removing filteringfunctions.o(.text.arm_biquad_cascade_df1_init_f32), (22 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_df1_init_f32), (8 bytes). @@ -2322,81 +2383,81 @@ Removing Unused input sections from the image. Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_df1_init_q15), (8 bytes). Removing filteringfunctions.o(.text.arm_biquad_cascade_df1_init_q31), (26 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_df1_init_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_biquad_cascade_df1_q15), (296 bytes). + Removing filteringfunctions.o(.text.arm_biquad_cascade_df1_q15), (308 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_df1_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_biquad_cascade_df1_q31), (530 bytes). + Removing filteringfunctions.o(.text.arm_biquad_cascade_df1_q31), (520 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_df1_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_biquad_cascade_df2T_f32), (902 bytes). + Removing filteringfunctions.o(.text.arm_biquad_cascade_df2T_f32), (898 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_df2T_f32), (8 bytes). - Removing filteringfunctions.o(.text.arm_biquad_cascade_df2T_f64), (2630 bytes). + Removing filteringfunctions.o(.text.arm_biquad_cascade_df2T_f64), (2634 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_df2T_f64), (8 bytes). Removing filteringfunctions.o(.text.arm_biquad_cascade_df2T_init_f32), (22 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_df2T_init_f32), (8 bytes). Removing filteringfunctions.o(.text.arm_biquad_cascade_df2T_init_f64), (22 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_df2T_init_f64), (8 bytes). - Removing filteringfunctions.o(.text.arm_biquad_cascade_stereo_df2T_f32), (962 bytes). + Removing filteringfunctions.o(.text.arm_biquad_cascade_stereo_df2T_f32), (958 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_stereo_df2T_f32), (8 bytes). Removing filteringfunctions.o(.text.arm_biquad_cascade_stereo_df2T_init_f32), (22 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_biquad_cascade_stereo_df2T_init_f32), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_f32), (1112 bytes). + Removing filteringfunctions.o(.text.arm_conv_f32), (1152 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_f32), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_fast_opt_q15), (602 bytes). + Removing filteringfunctions.o(.text.arm_conv_fast_opt_q15), (644 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_fast_opt_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_fast_q15), (1150 bytes). + Removing filteringfunctions.o(.text.arm_conv_fast_q15), (1220 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_fast_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_fast_q31), (952 bytes). + Removing filteringfunctions.o(.text.arm_conv_fast_q31), (984 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_fast_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_opt_q15), (708 bytes). + Removing filteringfunctions.o(.text.arm_conv_opt_q15), (772 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_opt_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_opt_q7), (666 bytes). + Removing filteringfunctions.o(.text.arm_conv_opt_q7), (744 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_opt_q7), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_partial_f32), (1212 bytes). + Removing filteringfunctions.o(.text.arm_conv_partial_f32), (1268 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_partial_f32), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_partial_fast_opt_q15), (622 bytes). + Removing filteringfunctions.o(.text.arm_conv_partial_fast_opt_q15), (688 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_partial_fast_opt_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_partial_fast_q15), (1284 bytes). + Removing filteringfunctions.o(.text.arm_conv_partial_fast_q15), (1352 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_partial_fast_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_partial_fast_q31), (1044 bytes). + Removing filteringfunctions.o(.text.arm_conv_partial_fast_q31), (1080 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_partial_fast_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_partial_opt_q15), (736 bytes). + Removing filteringfunctions.o(.text.arm_conv_partial_opt_q15), (800 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_partial_opt_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_partial_opt_q7), (680 bytes). + Removing filteringfunctions.o(.text.arm_conv_partial_opt_q7), (760 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_partial_opt_q7), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_partial_q15), (1568 bytes). + Removing filteringfunctions.o(.text.arm_conv_partial_q15), (1578 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_partial_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_partial_q31), (1104 bytes). + Removing filteringfunctions.o(.text.arm_conv_partial_q31), (1176 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_partial_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_partial_q7), (1156 bytes). + Removing filteringfunctions.o(.text.arm_conv_partial_q7), (1260 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_partial_q7), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_q15), (1290 bytes). + Removing filteringfunctions.o(.text.arm_conv_q15), (1426 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_q31), (1092 bytes). + Removing filteringfunctions.o(.text.arm_conv_q31), (1058 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_conv_q7), (1016 bytes). + Removing filteringfunctions.o(.text.arm_conv_q7), (1112 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_conv_q7), (8 bytes). - Removing filteringfunctions.o(.text.arm_correlate_f32), (1168 bytes). + Removing filteringfunctions.o(.text.arm_correlate_f32), (1188 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_correlate_f32), (8 bytes). - Removing filteringfunctions.o(.text.arm_correlate_fast_opt_q15), (566 bytes). + Removing filteringfunctions.o(.text.arm_correlate_fast_opt_q15), (644 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_correlate_fast_opt_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_correlate_fast_q15), (1044 bytes). + Removing filteringfunctions.o(.text.arm_correlate_fast_q15), (1132 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_correlate_fast_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_correlate_fast_q31), (984 bytes). + Removing filteringfunctions.o(.text.arm_correlate_fast_q31), (1044 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_correlate_fast_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_correlate_opt_q15), (704 bytes). + Removing filteringfunctions.o(.text.arm_correlate_opt_q15), (724 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_correlate_opt_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_correlate_opt_q7), (724 bytes). + Removing filteringfunctions.o(.text.arm_correlate_opt_q7), (780 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_correlate_opt_q7), (8 bytes). - Removing filteringfunctions.o(.text.arm_correlate_q15), (1268 bytes). + Removing filteringfunctions.o(.text.arm_correlate_q15), (1244 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_correlate_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_correlate_q31), (1046 bytes). + Removing filteringfunctions.o(.text.arm_correlate_q31), (1150 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_correlate_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_correlate_q7), (1108 bytes). + Removing filteringfunctions.o(.text.arm_correlate_q7), (1184 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_correlate_q7), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_decimate_f32), (964 bytes). + Removing filteringfunctions.o(.text.arm_fir_decimate_f32), (1048 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_decimate_f32), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_decimate_fast_q15), (602 bytes). + Removing filteringfunctions.o(.text.arm_fir_decimate_fast_q15), (606 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_decimate_fast_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_decimate_fast_q31), (902 bytes). + Removing filteringfunctions.o(.text.arm_fir_decimate_fast_q31), (1026 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_decimate_fast_q31), (8 bytes). Removing filteringfunctions.o(.text.arm_fir_decimate_init_f32), (58 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_decimate_init_f32), (8 bytes). @@ -2404,15 +2465,15 @@ Removing Unused input sections from the image. Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_decimate_init_q15), (8 bytes). Removing filteringfunctions.o(.text.arm_fir_decimate_init_q31), (58 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_decimate_init_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_decimate_q15), (690 bytes). + Removing filteringfunctions.o(.text.arm_fir_decimate_q15), (634 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_decimate_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_decimate_q31), (1046 bytes). + Removing filteringfunctions.o(.text.arm_fir_decimate_q31), (1154 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_decimate_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_f32), (1224 bytes). + Removing filteringfunctions.o(.text.arm_fir_f32), (1244 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_f32), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_fast_q15), (518 bytes). + Removing filteringfunctions.o(.text.arm_fir_fast_q15), (558 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_fast_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_fast_q31), (550 bytes). + Removing filteringfunctions.o(.text.arm_fir_fast_q31), (574 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_fast_q31), (8 bytes). Removing filteringfunctions.o(.text.arm_fir_init_f32), (32 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_init_f32), (8 bytes). @@ -2422,7 +2483,7 @@ Removing Unused input sections from the image. Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_init_q31), (8 bytes). Removing filteringfunctions.o(.text.arm_fir_init_q7), (26 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_init_q7), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_interpolate_f32), (964 bytes). + Removing filteringfunctions.o(.text.arm_fir_interpolate_f32), (1068 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_interpolate_f32), (8 bytes). Removing filteringfunctions.o(.text.arm_fir_interpolate_init_f32), (54 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_interpolate_init_f32), (8 bytes). @@ -2430,11 +2491,11 @@ Removing Unused input sections from the image. Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_interpolate_init_q15), (8 bytes). Removing filteringfunctions.o(.text.arm_fir_interpolate_init_q31), (54 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_interpolate_init_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_interpolate_q15), (1134 bytes). + Removing filteringfunctions.o(.text.arm_fir_interpolate_q15), (1138 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_interpolate_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_interpolate_q31), (1026 bytes). + Removing filteringfunctions.o(.text.arm_fir_interpolate_q31), (1122 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_interpolate_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_lattice_f32), (782 bytes). + Removing filteringfunctions.o(.text.arm_fir_lattice_f32), (786 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_lattice_f32), (8 bytes). Removing filteringfunctions.o(.text.arm_fir_lattice_init_f32), (22 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_lattice_init_f32), (8 bytes). @@ -2442,17 +2503,17 @@ Removing Unused input sections from the image. Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_lattice_init_q15), (8 bytes). Removing filteringfunctions.o(.text.arm_fir_lattice_init_q31), (22 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_lattice_init_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_lattice_q15), (1052 bytes). + Removing filteringfunctions.o(.text.arm_fir_lattice_q15), (1056 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_lattice_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_lattice_q31), (874 bytes). + Removing filteringfunctions.o(.text.arm_fir_lattice_q31), (886 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_lattice_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_q15), (634 bytes). + Removing filteringfunctions.o(.text.arm_fir_q15), (642 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_q31), (562 bytes). + Removing filteringfunctions.o(.text.arm_fir_q31), (590 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_q7), (662 bytes). + Removing filteringfunctions.o(.text.arm_fir_q7), (670 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_q7), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_sparse_f32), (734 bytes). + Removing filteringfunctions.o(.text.arm_fir_sparse_f32), (716 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_sparse_f32), (8 bytes). Removing filteringfunctions.o(.text.arm_fir_sparse_init_f32), (42 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_sparse_init_f32), (8 bytes). @@ -2462,13 +2523,13 @@ Removing Unused input sections from the image. Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_sparse_init_q31), (8 bytes). Removing filteringfunctions.o(.text.arm_fir_sparse_init_q7), (40 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_sparse_init_q7), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_sparse_q15), (784 bytes). + Removing filteringfunctions.o(.text.arm_fir_sparse_q15), (750 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_sparse_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_sparse_q31), (702 bytes). + Removing filteringfunctions.o(.text.arm_fir_sparse_q31), (648 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_sparse_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_fir_sparse_q7), (738 bytes). + Removing filteringfunctions.o(.text.arm_fir_sparse_q7), (714 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_fir_sparse_q7), (8 bytes). - Removing filteringfunctions.o(.text.arm_iir_lattice_f32), (520 bytes). + Removing filteringfunctions.o(.text.arm_iir_lattice_f32), (528 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_iir_lattice_f32), (8 bytes). Removing filteringfunctions.o(.text.arm_iir_lattice_init_f32), (28 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_iir_lattice_init_f32), (8 bytes). @@ -2476,11 +2537,11 @@ Removing Unused input sections from the image. Removing filteringfunctions.o(.ARM.exidx.text.arm_iir_lattice_init_q15), (8 bytes). Removing filteringfunctions.o(.text.arm_iir_lattice_init_q31), (28 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_iir_lattice_init_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_iir_lattice_q15), (578 bytes). + Removing filteringfunctions.o(.text.arm_iir_lattice_q15), (566 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_iir_lattice_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_iir_lattice_q31), (654 bytes). + Removing filteringfunctions.o(.text.arm_iir_lattice_q31), (626 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_iir_lattice_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_lms_f32), (560 bytes). + Removing filteringfunctions.o(.text.arm_lms_f32), (592 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_lms_f32), (8 bytes). Removing filteringfunctions.o(.text.arm_lms_init_f32), (48 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_lms_init_f32), (8 bytes). @@ -2496,26 +2557,26 @@ Removing Unused input sections from the image. Removing filteringfunctions.o(.ARM.exidx.text.arm_lms_norm_init_q15), (8 bytes). Removing filteringfunctions.o(.text.arm_lms_norm_init_q31), (60 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_lms_norm_init_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_lms_norm_q15), (674 bytes). + Removing filteringfunctions.o(.text.arm_lms_norm_q15), (686 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_lms_norm_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_lms_norm_q31), (858 bytes). + Removing filteringfunctions.o(.text.arm_lms_norm_q31), (846 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_lms_norm_q31), (8 bytes). - Removing filteringfunctions.o(.text.arm_lms_q15), (526 bytes). + Removing filteringfunctions.o(.text.arm_lms_q15), (522 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_lms_q15), (8 bytes). - Removing filteringfunctions.o(.text.arm_lms_q31), (618 bytes). + Removing filteringfunctions.o(.text.arm_lms_q31), (614 bytes). Removing filteringfunctions.o(.ARM.exidx.text.arm_lms_q31), (8 bytes). Removing matrixfunctions.o(.text), (0 bytes). Removing matrixfunctions.o(.text.arm_mat_add_f32), (214 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_add_f32), (8 bytes). - Removing matrixfunctions.o(.text.arm_mat_add_q15), (156 bytes). + Removing matrixfunctions.o(.text.arm_mat_add_q15), (140 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_add_q15), (8 bytes). Removing matrixfunctions.o(.text.arm_mat_add_q31), (176 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_add_q31), (8 bytes). - Removing matrixfunctions.o(.text.arm_mat_cmplx_mult_f32), (504 bytes). + Removing matrixfunctions.o(.text.arm_mat_cmplx_mult_f32), (516 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_cmplx_mult_f32), (8 bytes). Removing matrixfunctions.o(.text.arm_mat_cmplx_mult_q15), (512 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_cmplx_mult_q15), (8 bytes). - Removing matrixfunctions.o(.text.arm_mat_cmplx_mult_q31), (492 bytes). + Removing matrixfunctions.o(.text.arm_mat_cmplx_mult_q31), (558 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_cmplx_mult_q31), (8 bytes). Removing matrixfunctions.o(.text.arm_mat_init_f32), (8 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_init_f32), (8 bytes). @@ -2523,45 +2584,45 @@ Removing Unused input sections from the image. Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_init_q15), (8 bytes). Removing matrixfunctions.o(.text.arm_mat_init_q31), (8 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_init_q31), (8 bytes). - Removing matrixfunctions.o(.text.arm_mat_inverse_f32), (708 bytes). + Removing matrixfunctions.o(.text.arm_mat_inverse_f32), (772 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_inverse_f32), (8 bytes). - Removing matrixfunctions.o(.text.arm_mat_inverse_f64), (904 bytes). + Removing matrixfunctions.o(.text.arm_mat_inverse_f64), (960 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_inverse_f64), (8 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_mult_f32), (8 bytes). - Removing matrixfunctions.o(.text.arm_mat_mult_fast_q15), (972 bytes). + Removing matrixfunctions.o(.text.arm_mat_mult_fast_q15), (1048 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_mult_fast_q15), (8 bytes). - Removing matrixfunctions.o(.text.arm_mat_mult_fast_q31), (756 bytes). + Removing matrixfunctions.o(.text.arm_mat_mult_fast_q31), (760 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_mult_fast_q31), (8 bytes). - Removing matrixfunctions.o(.text.arm_mat_mult_q15), (420 bytes). + Removing matrixfunctions.o(.text.arm_mat_mult_q15), (392 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_mult_q15), (8 bytes). - Removing matrixfunctions.o(.text.arm_mat_mult_q31), (304 bytes). + Removing matrixfunctions.o(.text.arm_mat_mult_q31), (320 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_mult_q31), (8 bytes). Removing matrixfunctions.o(.text.arm_mat_scale_f32), (164 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_scale_f32), (8 bytes). - Removing matrixfunctions.o(.text.arm_mat_scale_q15), (180 bytes). + Removing matrixfunctions.o(.text.arm_mat_scale_q15), (168 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_scale_q15), (8 bytes). Removing matrixfunctions.o(.text.arm_mat_scale_q31), (228 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_scale_q31), (8 bytes). Removing matrixfunctions.o(.text.arm_mat_sub_f32), (214 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_sub_f32), (8 bytes). - Removing matrixfunctions.o(.text.arm_mat_sub_q15), (156 bytes). + Removing matrixfunctions.o(.text.arm_mat_sub_q15), (140 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_sub_q15), (8 bytes). Removing matrixfunctions.o(.text.arm_mat_sub_q31), (176 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_sub_q31), (8 bytes). Removing matrixfunctions.o(.text.arm_mat_trans_f32), (170 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_trans_f32), (8 bytes). - Removing matrixfunctions.o(.text.arm_mat_trans_q15), (170 bytes). + Removing matrixfunctions.o(.text.arm_mat_trans_q15), (162 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_trans_q15), (8 bytes). Removing matrixfunctions.o(.text.arm_mat_trans_q31), (170 bytes). Removing matrixfunctions.o(.ARM.exidx.text.arm_mat_trans_q31), (8 bytes). Removing svmfunctions.o(.text), (0 bytes). Removing svmfunctions.o(.text.arm_svm_linear_init_f32), (24 bytes). Removing svmfunctions.o(.ARM.exidx.text.arm_svm_linear_init_f32), (8 bytes). - Removing svmfunctions.o(.text.arm_svm_linear_predict_f32), (144 bytes). + Removing svmfunctions.o(.text.arm_svm_linear_predict_f32), (140 bytes). Removing svmfunctions.o(.ARM.exidx.text.arm_svm_linear_predict_f32), (8 bytes). Removing svmfunctions.o(.text.arm_svm_polynomial_init_f32), (40 bytes). Removing svmfunctions.o(.ARM.exidx.text.arm_svm_polynomial_init_f32), (8 bytes). - Removing svmfunctions.o(.text.arm_svm_polynomial_predict_f32), (192 bytes). + Removing svmfunctions.o(.text.arm_svm_polynomial_predict_f32), (196 bytes). Removing svmfunctions.o(.ARM.exidx.text.arm_svm_polynomial_predict_f32), (8 bytes). Removing svmfunctions.o(.text.arm_exponent_f32), (28 bytes). Removing svmfunctions.o(.ARM.exidx.text.arm_exponent_f32), (8 bytes). @@ -2571,16 +2632,16 @@ Removing Unused input sections from the image. Removing svmfunctions.o(.ARM.exidx.text.arm_svm_rbf_predict_f32), (8 bytes). Removing svmfunctions.o(.text.arm_svm_sigmoid_init_f32), (32 bytes). Removing svmfunctions.o(.ARM.exidx.text.arm_svm_sigmoid_init_f32), (8 bytes). - Removing svmfunctions.o(.text.arm_svm_sigmoid_predict_f32), (176 bytes). + Removing svmfunctions.o(.text.arm_svm_sigmoid_predict_f32), (172 bytes). Removing svmfunctions.o(.ARM.exidx.text.arm_svm_sigmoid_predict_f32), (8 bytes). Removing statisticsfunctions.o(.text), (0 bytes). Removing statisticsfunctions.o(.text.arm_entropy_f32), (64 bytes). Removing statisticsfunctions.o(.ARM.exidx.text.arm_entropy_f32), (8 bytes). - Removing statisticsfunctions.o(.text.arm_entropy_f64), (112 bytes). + Removing statisticsfunctions.o(.text.arm_entropy_f64), (120 bytes). Removing statisticsfunctions.o(.ARM.exidx.text.arm_entropy_f64), (8 bytes). Removing statisticsfunctions.o(.text.arm_kullback_leibler_f32), (76 bytes). Removing statisticsfunctions.o(.ARM.exidx.text.arm_kullback_leibler_f32), (8 bytes). - Removing statisticsfunctions.o(.text.arm_kullback_leibler_f64), (144 bytes). + Removing statisticsfunctions.o(.text.arm_kullback_leibler_f64), (152 bytes). Removing statisticsfunctions.o(.ARM.exidx.text.arm_kullback_leibler_f64), (8 bytes). Removing statisticsfunctions.o(.text.arm_logsumexp_dot_prod_f32), (24 bytes). Removing statisticsfunctions.o(.ARM.exidx.text.arm_logsumexp_dot_prod_f32), (8 bytes). @@ -2617,7 +2678,7 @@ Removing Unused input sections from the image. Removing statisticsfunctions.o(.ARM.exidx.text.arm_power_q31), (8 bytes). Removing statisticsfunctions.o(.text.arm_power_q7), (78 bytes). Removing statisticsfunctions.o(.ARM.exidx.text.arm_power_q7), (8 bytes). - Removing statisticsfunctions.o(.text.arm_rms_f32), (196 bytes). + Removing statisticsfunctions.o(.text.arm_rms_f32), (200 bytes). Removing statisticsfunctions.o(.ARM.exidx.text.arm_rms_f32), (8 bytes). Removing statisticsfunctions.o(.text.arm_rms_q15), (118 bytes). Removing statisticsfunctions.o(.ARM.exidx.text.arm_rms_q15), (8 bytes). @@ -2629,7 +2690,7 @@ Removing Unused input sections from the image. Removing statisticsfunctions.o(.ARM.exidx.text.arm_std_q15), (8 bytes). Removing statisticsfunctions.o(.text.arm_std_q31), (246 bytes). Removing statisticsfunctions.o(.ARM.exidx.text.arm_std_q31), (8 bytes). - Removing statisticsfunctions.o(.text.arm_var_q15), (154 bytes). + Removing statisticsfunctions.o(.text.arm_var_q15), (152 bytes). Removing statisticsfunctions.o(.ARM.exidx.text.arm_var_q15), (8 bytes). Removing statisticsfunctions.o(.text.arm_var_q31), (236 bytes). Removing statisticsfunctions.o(.ARM.exidx.text.arm_var_q31), (8 bytes). @@ -2658,7 +2719,7 @@ Removing Unused input sections from the image. Removing supportfunctions.o(.ARM.exidx.text.arm_fill_q31), (8 bytes). Removing supportfunctions.o(.text.arm_fill_q7), (64 bytes). Removing supportfunctions.o(.ARM.exidx.text.arm_fill_q7), (8 bytes). - Removing supportfunctions.o(.text.arm_heap_sort_f32), (102 bytes). + Removing supportfunctions.o(.text.arm_heap_sort_f32), (100 bytes). Removing supportfunctions.o(.ARM.exidx.text.arm_heap_sort_f32), (8 bytes). Removing supportfunctions.o(.text.arm_heapify), (126 bytes). Removing supportfunctions.o(.ARM.exidx.text.arm_heapify), (8 bytes). @@ -2710,7 +2771,7 @@ Removing Unused input sections from the image. Removing supportfunctions.o(.ARM.exidx.text.arm_q7_to_q15), (8 bytes). Removing supportfunctions.o(.text.arm_q7_to_q31), (94 bytes). Removing supportfunctions.o(.ARM.exidx.text.arm_q7_to_q31), (8 bytes). - Removing supportfunctions.o(.text.topDownMerge), (96 bytes). + Removing supportfunctions.o(.text.topDownMerge), (88 bytes). Removing supportfunctions.o(.ARM.exidx.text.topDownMerge), (8 bytes). Removing supportfunctions.o(.text.arm_quick_sort_partition_f32), (168 bytes). Removing supportfunctions.o(.ARM.exidx.text.arm_quick_sort_partition_f32), (8 bytes). @@ -2731,15 +2792,15 @@ Removing Unused input sections from the image. Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix8by2_f32), (8 bytes). Removing transformfunctions.o(.text.arm_radix8_butterfly_f32), (1458 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_radix8_butterfly_f32), (8 bytes). - Removing transformfunctions.o(.text.arm_cfft_radix8by4_f32), (1232 bytes). + Removing transformfunctions.o(.text.arm_cfft_radix8by4_f32), (1020 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix8by4_f32), (8 bytes). Removing transformfunctions.o(.text.arm_cfft_f32), (238 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_f32), (8 bytes). - Removing transformfunctions.o(.text.arm_radix4_butterfly_f64), (950 bytes). + Removing transformfunctions.o(.text.arm_radix4_butterfly_f64), (952 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_radix4_butterfly_f64), (8 bytes). - Removing transformfunctions.o(.text.arm_cfft_radix4by2_f64), (366 bytes). + Removing transformfunctions.o(.text.arm_cfft_radix4by2_f64), (368 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix4by2_f64), (8 bytes). - Removing transformfunctions.o(.text.arm_cfft_f64), (312 bytes). + Removing transformfunctions.o(.text.arm_cfft_f64), (384 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_f64), (8 bytes). Removing transformfunctions.o(.text.arm_cfft_q15), (214 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_q15), (8 bytes). @@ -2753,13 +2814,13 @@ Removing Unused input sections from the image. Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix4by2_q15), (8 bytes). Removing transformfunctions.o(.text.arm_cfft_q31), (214 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_q31), (8 bytes). - Removing transformfunctions.o(.text.arm_radix4_butterfly_inverse_q31), (924 bytes). + Removing transformfunctions.o(.text.arm_radix4_butterfly_inverse_q31), (974 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_radix4_butterfly_inverse_q31), (8 bytes). - Removing transformfunctions.o(.text.arm_cfft_radix4by2_inverse_q31), (228 bytes). + Removing transformfunctions.o(.text.arm_cfft_radix4by2_inverse_q31), (224 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix4by2_inverse_q31), (8 bytes). - Removing transformfunctions.o(.text.arm_radix4_butterfly_q31), (966 bytes). + Removing transformfunctions.o(.text.arm_radix4_butterfly_q31), (988 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_radix4_butterfly_q31), (8 bytes). - Removing transformfunctions.o(.text.arm_cfft_radix4by2_q31), (246 bytes). + Removing transformfunctions.o(.text.arm_cfft_radix4by2_q31), (232 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix4by2_q31), (8 bytes). Removing transformfunctions.o(.text.arm_cfft_init_f32), (180 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_init_f32), (8 bytes). @@ -2771,9 +2832,9 @@ Removing Unused input sections from the image. Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_init_q31), (8 bytes). Removing transformfunctions.o(.text.arm_cfft_radix2_f32), (62 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix2_f32), (8 bytes). - Removing transformfunctions.o(.text.arm_radix2_butterfly_inverse_f32), (402 bytes). + Removing transformfunctions.o(.text.arm_radix2_butterfly_inverse_f32), (398 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_radix2_butterfly_inverse_f32), (8 bytes). - Removing transformfunctions.o(.text.arm_radix2_butterfly_f32), (382 bytes). + Removing transformfunctions.o(.text.arm_radix2_butterfly_f32), (378 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_radix2_butterfly_f32), (8 bytes). Removing transformfunctions.o(.text.arm_cfft_radix2_init_f32), (228 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix2_init_f32), (8 bytes). @@ -2783,21 +2844,21 @@ Removing Unused input sections from the image. Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix2_init_q31), (8 bytes). Removing transformfunctions.o(.text.arm_cfft_radix2_q15), (48 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix2_q15), (8 bytes). - Removing transformfunctions.o(.text.arm_radix2_butterfly_inverse_q15), (442 bytes). + Removing transformfunctions.o(.text.arm_radix2_butterfly_inverse_q15), (434 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_radix2_butterfly_inverse_q15), (8 bytes). - Removing transformfunctions.o(.text.arm_radix2_butterfly_q15), (444 bytes). + Removing transformfunctions.o(.text.arm_radix2_butterfly_q15), (440 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_radix2_butterfly_q15), (8 bytes). Removing transformfunctions.o(.text.arm_cfft_radix2_q31), (48 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix2_q31), (8 bytes). - Removing transformfunctions.o(.text.arm_radix2_butterfly_inverse_q31), (464 bytes). + Removing transformfunctions.o(.text.arm_radix2_butterfly_inverse_q31), (500 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_radix2_butterfly_inverse_q31), (8 bytes). - Removing transformfunctions.o(.text.arm_radix2_butterfly_q31), (484 bytes). + Removing transformfunctions.o(.text.arm_radix2_butterfly_q31), (516 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_radix2_butterfly_q31), (8 bytes). Removing transformfunctions.o(.text.arm_cfft_radix4_f32), (62 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix4_f32), (8 bytes). Removing transformfunctions.o(.text.arm_radix4_butterfly_inverse_f32), (880 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_radix4_butterfly_inverse_f32), (8 bytes). - Removing transformfunctions.o(.text.arm_radix4_butterfly_f32), (852 bytes). + Removing transformfunctions.o(.text.arm_radix4_butterfly_f32), (860 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_radix4_butterfly_f32), (8 bytes). Removing transformfunctions.o(.text.arm_cfft_radix4_init_f32), (148 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix4_init_f32), (8 bytes). @@ -2809,7 +2870,7 @@ Removing Unused input sections from the image. Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix4_q15), (8 bytes). Removing transformfunctions.o(.text.arm_cfft_radix4_q31), (54 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_cfft_radix4_q31), (8 bytes). - Removing transformfunctions.o(.text.arm_dct4_f32), (388 bytes). + Removing transformfunctions.o(.text.arm_dct4_f32), (404 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_dct4_f32), (8 bytes). Removing transformfunctions.o(.text.arm_rfft_f32), (136 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_rfft_f32), (8 bytes). @@ -2825,7 +2886,7 @@ Removing Unused input sections from the image. Removing transformfunctions.o(.ARM.exidx.text.arm_dct4_init_q31), (8 bytes). Removing transformfunctions.o(.text.arm_rfft_init_q31), (212 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_rfft_init_q31), (8 bytes). - Removing transformfunctions.o(.text.arm_dct4_q15), (396 bytes). + Removing transformfunctions.o(.text.arm_dct4_q15), (388 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_dct4_q15), (8 bytes). Removing transformfunctions.o(.text.arm_rfft_q15), (124 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_rfft_q15), (8 bytes). @@ -2835,17 +2896,17 @@ Removing Unused input sections from the image. Removing transformfunctions.o(.ARM.exidx.text.arm_rfft_q31), (8 bytes). Removing transformfunctions.o(.text.arm_split_rifft_f32), (140 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_split_rifft_f32), (8 bytes). - Removing transformfunctions.o(.text.arm_split_rfft_f32), (256 bytes). + Removing transformfunctions.o(.text.arm_split_rfft_f32), (232 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_split_rfft_f32), (8 bytes). Removing transformfunctions.o(.text.stage_rfft_f32), (186 bytes). Removing transformfunctions.o(.ARM.exidx.text.stage_rfft_f32), (8 bytes). - Removing transformfunctions.o(.text.merge_rfft_f32), (182 bytes). + Removing transformfunctions.o(.text.merge_rfft_f32), (178 bytes). Removing transformfunctions.o(.ARM.exidx.text.merge_rfft_f32), (8 bytes). Removing transformfunctions.o(.text.arm_rfft_fast_f32), (66 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_rfft_fast_f32), (8 bytes). Removing transformfunctions.o(.text.stage_rfft_f64), (456 bytes). Removing transformfunctions.o(.ARM.exidx.text.stage_rfft_f64), (8 bytes). - Removing transformfunctions.o(.text.merge_rfft_f64), (440 bytes). + Removing transformfunctions.o(.text.merge_rfft_f64), (432 bytes). Removing transformfunctions.o(.ARM.exidx.text.merge_rfft_f64), (8 bytes). Removing transformfunctions.o(.text.arm_rfft_fast_f64), (72 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_rfft_fast_f64), (8 bytes). @@ -2887,14 +2948,14 @@ Removing Unused input sections from the image. Removing transformfunctions.o(.ARM.exidx.text.arm_rfft_32_fast_init_f64), (8 bytes). Removing transformfunctions.o(.text.arm_split_rifft_q15), (88 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_split_rifft_q15), (8 bytes). - Removing transformfunctions.o(.text.arm_split_rfft_q15), (180 bytes). + Removing transformfunctions.o(.text.arm_split_rfft_q15), (172 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_split_rfft_q15), (8 bytes). Removing transformfunctions.o(.text.arm_split_rifft_q31), (136 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_split_rifft_q31), (8 bytes). Removing transformfunctions.o(.text.arm_split_rfft_q31), (274 bytes). Removing transformfunctions.o(.ARM.exidx.text.arm_split_rfft_q31), (8 bytes). -1226 unused section(s) (total 1040133 bytes) removed from the image. +1226 unused section(s) (total 1042543 bytes) removed from the image. ============================================================================== @@ -3019,16 +3080,22 @@ Image Symbol Table ../fplib/usenofp.s 0x00000000 Number 0 usenofp.o ABSOLUTE ../mathlib/dunder.c 0x00000000 Number 0 dunder.o ABSOLUTE ../mathlib/expf.c 0x00000000 Number 0 expf.o ABSOLUTE + ../mathlib/expf.c 0x00000000 Number 0 expf_x.o ABSOLUTE ../mathlib/fpclassify.c 0x00000000 Number 0 fpclassify.o ABSOLUTE ../mathlib/fpclassifyf.c 0x00000000 Number 0 fpclassifyf.o ABSOLUTE ../mathlib/funder.c 0x00000000 Number 0 funder.o ABSOLUTE ../mathlib/log.c 0x00000000 Number 0 log.o ABSOLUTE + ../mathlib/log.c 0x00000000 Number 0 log_x.o ABSOLUTE ../mathlib/logf.c 0x00000000 Number 0 logf.o ABSOLUTE + ../mathlib/logf.c 0x00000000 Number 0 logf_x.o ABSOLUTE ../mathlib/poly.c 0x00000000 Number 0 poly.o ABSOLUTE ../mathlib/powf.c 0x00000000 Number 0 powf.o ABSOLUTE + ../mathlib/powf.c 0x00000000 Number 0 powf_x.o ABSOLUTE ../mathlib/qnan.c 0x00000000 Number 0 qnan.o ABSOLUTE ../mathlib/sqrtf.c 0x00000000 Number 0 sqrtf.o ABSOLUTE + ../mathlib/sqrtf.c 0x00000000 Number 0 sqrtf_x.o ABSOLUTE ../mathlib/tanhf.c 0x00000000 Number 0 tanhf.o ABSOLUTE + ../mathlib/tanhf.c 0x00000000 Number 0 tanhf_x.o ABSOLUTE ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\startup\mdk\startup_at32f435_437.s 0x00000000 Number 0 startup_at32f435_437.o ABSOLUTE BasicMathFunctions.c 0x00000000 Number 0 basicmathfunctions.o ABSOLUTE BayesFunctions.c 0x00000000 Number 0 bayesfunctions.o ABSOLUTE @@ -3139,78 +3206,78 @@ Image Symbol Table [Anonymous Symbol] 0x08000b8c Section 0 at32f435_437_int.o(.text.UsageFault_Handler) [Anonymous Symbol] 0x08000b90 Section 0 at32f435_437_board.o(.text._sys_exit) [Anonymous Symbol] 0x08000b94 Section 0 matrixfunctions.o(.text.arm_mat_mult_f32) - [Anonymous Symbol] 0x08000cd4 Section 0 statisticsfunctions.o(.text.arm_max_f32) - [Anonymous Symbol] 0x08000da4 Section 0 statisticsfunctions.o(.text.arm_mean_f32) - [Anonymous Symbol] 0x08000e24 Section 0 statisticsfunctions.o(.text.arm_min_f32) - [Anonymous Symbol] 0x08000ef4 Section 0 statisticsfunctions.o(.text.arm_std_f32) - [Anonymous Symbol] 0x08000f38 Section 0 statisticsfunctions.o(.text.arm_var_f32) - [Anonymous Symbol] 0x08001064 Section 0 at32f435_437_crm.o(.text.crm_ahb_div_set) - [Anonymous Symbol] 0x08001080 Section 0 at32f435_437_crm.o(.text.crm_apb1_div_set) - [Anonymous Symbol] 0x0800109c Section 0 at32f435_437_crm.o(.text.crm_apb2_div_set) - [Anonymous Symbol] 0x080010b8 Section 0 at32f435_437_crm.o(.text.crm_auto_step_mode_enable) - [Anonymous Symbol] 0x080010d0 Section 0 at32f435_437_crm.o(.text.crm_clock_source_enable) - [Anonymous Symbol] 0x0800114c Section 0 at32f435_437_crm.o(.text.crm_clocks_freq_get) - crm_clocks_freq_get.pll_fr_table 0x080011d8 Number 0 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Symbol] 0x08001088 Section 0 at32f435_437_crm.o(.text.crm_ahb_div_set) + [Anonymous Symbol] 0x080010a4 Section 0 at32f435_437_crm.o(.text.crm_apb1_div_set) + [Anonymous Symbol] 0x080010c0 Section 0 at32f435_437_crm.o(.text.crm_apb2_div_set) + [Anonymous Symbol] 0x080010dc Section 0 at32f435_437_crm.o(.text.crm_auto_step_mode_enable) + [Anonymous Symbol] 0x080010f8 Section 0 at32f435_437_crm.o(.text.crm_clock_source_enable) + [Anonymous Symbol] 0x08001174 Section 0 at32f435_437_crm.o(.text.crm_clocks_freq_get) + crm_clocks_freq_get.pll_fr_table 0x08001200 Number 0 at32f435_437_crm.o(.text.crm_clocks_freq_get) + crm_clocks_freq_get.sclk_ahb_div_table 0x08001208 Number 0 at32f435_437_crm.o(.text.crm_clocks_freq_get) + crm_clocks_freq_get.ahb_apb1_div_table 0x08001218 Number 0 at32f435_437_crm.o(.text.crm_clocks_freq_get) + crm_clocks_freq_get.ahb_apb2_div_table 0x08001218 Number 0 at32f435_437_crm.o(.text.crm_clocks_freq_get) + [Anonymous Symbol] 0x08001220 Section 0 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__lcnum_c_grouping 0x0800236b Data 0 lc_numeric_c.o(locale$$data) + __lcnum_c_end 0x0800236c Data 0 lc_numeric_c.o(locale$$data) .bss 0x20000008 Section 96 libspace.o(.bss) testOutput 0x200000d0 Data 320 main.o(.bss.testOutput) [Anonymous Symbol] 0x200000d0 Section 0 main.o(.bss.testOutput) @@ -3447,62 +3514,62 @@ Image Symbol Table SystemInit 0x08000b25 Thumb Code 104 system_at32f435_437.o(.text.SystemInit) UsageFault_Handler 0x08000b8d Thumb Code 2 at32f435_437_int.o(.text.UsageFault_Handler) _sys_exit 0x08000b91 Thumb Code 2 at32f435_437_board.o(.text._sys_exit) - arm_mat_mult_f32 0x08000b95 Thumb Code 320 matrixfunctions.o(.text.arm_mat_mult_f32) - arm_max_f32 0x08000cd5 Thumb Code 206 statisticsfunctions.o(.text.arm_max_f32) - arm_mean_f32 0x08000da5 Thumb Code 128 statisticsfunctions.o(.text.arm_mean_f32) - arm_min_f32 0x08000e25 Thumb Code 206 statisticsfunctions.o(.text.arm_min_f32) - arm_std_f32 0x08000ef5 Thumb Code 68 statisticsfunctions.o(.text.arm_std_f32) - arm_var_f32 0x08000f39 Thumb Code 300 statisticsfunctions.o(.text.arm_var_f32) - crm_ahb_div_set 0x08001065 Thumb Code 26 at32f435_437_crm.o(.text.crm_ahb_div_set) - crm_apb1_div_set 0x08001081 Thumb Code 26 at32f435_437_crm.o(.text.crm_apb1_div_set) - crm_apb2_div_set 0x0800109d Thumb Code 26 at32f435_437_crm.o(.text.crm_apb2_div_set) - crm_auto_step_mode_enable 0x080010b9 Thumb Code 24 at32f435_437_crm.o(.text.crm_auto_step_mode_enable) - crm_clock_source_enable 0x080010d1 Thumb Code 122 at32f435_437_crm.o(.text.crm_clock_source_enable) - crm_clocks_freq_get 0x0800114d Thumb Code 140 at32f435_437_crm.o(.text.crm_clocks_freq_get) - crm_flag_get 0x080011f9 Thumb Code 26 at32f435_437_crm.o(.text.crm_flag_get) - crm_hext_stable_wait 0x08001215 Thumb Code 40 at32f435_437_crm.o(.text.crm_hext_stable_wait) - crm_periph_clock_enable 0x0800123d Thumb Code 40 at32f435_437_crm.o(.text.crm_periph_clock_enable) - crm_pll_config 0x08001265 Thumb Code 90 at32f435_437_crm.o(.text.crm_pll_config) - crm_reset 0x080012c1 Thumb Code 80 at32f435_437_crm.o(.text.crm_reset) - crm_sysclk_switch 0x08001311 Thumb Code 18 at32f435_437_crm.o(.text.crm_sysclk_switch) - crm_sysclk_switch_status_get 0x08001325 Thumb Code 16 at32f435_437_crm.o(.text.crm_sysclk_switch_status_get) - fputc 0x08001335 Thumb Code 36 at32f435_437_board.o(.text.fputc) - gpio_default_para_init 0x08001359 Thumb Code 14 at32f435_437_gpio.o(.text.gpio_default_para_init) - gpio_init 0x08001369 Thumb Code 132 at32f435_437_gpio.o(.text.gpio_init) - gpio_pin_mux_config 0x080013ed Thumb Code 46 at32f435_437_gpio.o(.text.gpio_pin_mux_config) - main 0x0800141d Thumb Code 268 main.o(.text.main) - system_clock_config 0x08001569 Thumb Code 148 at32f435_437_clock.o(.text.system_clock_config) - system_core_clock_update 0x080015fd Thumb Code 116 system_at32f435_437.o(.text.system_core_clock_update) - uart_print_init 0x08001689 Thumb Code 110 at32f435_437_board.o(.text.uart_print_init) - usart_data_transmit 0x080016f9 Thumb Code 8 at32f435_437_usart.o(.text.usart_data_transmit) - usart_enable 0x08001701 Thumb Code 18 at32f435_437_usart.o(.text.usart_enable) - usart_flag_get 0x08001715 Thumb Code 10 at32f435_437_usart.o(.text.usart_flag_get) - usart_init 0x08001721 Thumb Code 180 at32f435_437_usart.o(.text.usart_init) - usart_transmitter_enable 0x080017d5 Thumb Code 18 at32f435_437_usart.o(.text.usart_transmitter_enable) - _btod_d2e 0x080017e7 Thumb Code 62 btod.o(CL$$btod_d2e) - _d2e_denorm_low 0x08001825 Thumb Code 70 btod.o(CL$$btod_d2e_denorm_low) - _d2e_norm_op1 0x0800186b Thumb Code 96 btod.o(CL$$btod_d2e_norm_op1) - __btod_div_common 0x080018cd Thumb Code 696 btod.o(CL$$btod_div_common) - _e2e 0x08001c05 Thumb Code 220 btod.o(CL$$btod_e2e) - _btod_ediv 0x08001ce1 Thumb Code 42 btod.o(CL$$btod_ediv) - _btod_emul 0x08001d0b Thumb Code 42 btod.o(CL$$btod_emul) - __btod_mult_common 0x08001d35 Thumb Code 580 btod.o(CL$$btod_mult_common) - __ARM_fpclassify 0x08001f79 Thumb Code 48 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anon$$obj.o(Region$$Table) + arm_mat_mult_f32 0x08000b95 Thumb Code 344 matrixfunctions.o(.text.arm_mat_mult_f32) + arm_max_f32 0x08000ced Thumb Code 206 statisticsfunctions.o(.text.arm_max_f32) + arm_mean_f32 0x08000dbd Thumb Code 128 statisticsfunctions.o(.text.arm_mean_f32) + arm_min_f32 0x08000e3d Thumb Code 206 statisticsfunctions.o(.text.arm_min_f32) + arm_std_f32 0x08000f0d Thumb Code 80 statisticsfunctions.o(.text.arm_std_f32) + arm_var_f32 0x08000f5d Thumb Code 300 statisticsfunctions.o(.text.arm_var_f32) + crm_ahb_div_set 0x08001089 Thumb Code 26 at32f435_437_crm.o(.text.crm_ahb_div_set) + crm_apb1_div_set 0x080010a5 Thumb Code 26 at32f435_437_crm.o(.text.crm_apb1_div_set) + crm_apb2_div_set 0x080010c1 Thumb Code 26 at32f435_437_crm.o(.text.crm_apb2_div_set) + crm_auto_step_mode_enable 0x080010dd Thumb Code 26 at32f435_437_crm.o(.text.crm_auto_step_mode_enable) + crm_clock_source_enable 0x080010f9 Thumb Code 122 at32f435_437_crm.o(.text.crm_clock_source_enable) + crm_clocks_freq_get 0x08001175 Thumb Code 172 at32f435_437_crm.o(.text.crm_clocks_freq_get) + crm_flag_get 0x08001221 Thumb Code 26 at32f435_437_crm.o(.text.crm_flag_get) + crm_hext_stable_wait 0x0800123d Thumb Code 40 at32f435_437_crm.o(.text.crm_hext_stable_wait) + crm_periph_clock_enable 0x08001265 Thumb Code 40 at32f435_437_crm.o(.text.crm_periph_clock_enable) + crm_pll_config 0x0800128d Thumb Code 90 at32f435_437_crm.o(.text.crm_pll_config) + crm_reset 0x080012e9 Thumb Code 80 at32f435_437_crm.o(.text.crm_reset) + crm_sysclk_switch 0x08001339 Thumb Code 18 at32f435_437_crm.o(.text.crm_sysclk_switch) + crm_sysclk_switch_status_get 0x0800134d Thumb Code 16 at32f435_437_crm.o(.text.crm_sysclk_switch_status_get) + fputc 0x0800135d Thumb Code 36 at32f435_437_board.o(.text.fputc) + gpio_default_para_init 0x08001381 Thumb Code 14 at32f435_437_gpio.o(.text.gpio_default_para_init) + gpio_init 0x08001391 Thumb Code 132 at32f435_437_gpio.o(.text.gpio_init) + gpio_pin_mux_config 0x08001415 Thumb Code 46 at32f435_437_gpio.o(.text.gpio_pin_mux_config) + main 0x08001445 Thumb Code 332 main.o(.text.main) + system_clock_config 0x08001591 Thumb Code 148 at32f435_437_clock.o(.text.system_clock_config) + system_core_clock_update 0x08001625 Thumb Code 140 system_at32f435_437.o(.text.system_core_clock_update) + uart_print_init 0x080016b1 Thumb Code 110 at32f435_437_board.o(.text.uart_print_init) + usart_data_transmit 0x08001721 Thumb Code 8 at32f435_437_usart.o(.text.usart_data_transmit) + usart_enable 0x08001729 Thumb Code 18 at32f435_437_usart.o(.text.usart_enable) + usart_flag_get 0x0800173d Thumb Code 10 at32f435_437_usart.o(.text.usart_flag_get) + usart_init 0x08001749 Thumb Code 166 at32f435_437_usart.o(.text.usart_init) + usart_transmitter_enable 0x080017f1 Thumb Code 18 at32f435_437_usart.o(.text.usart_transmitter_enable) + _btod_d2e 0x08001803 Thumb Code 62 btod.o(CL$$btod_d2e) + _d2e_denorm_low 0x08001841 Thumb Code 70 btod.o(CL$$btod_d2e_denorm_low) + _d2e_norm_op1 0x08001887 Thumb Code 96 btod.o(CL$$btod_d2e_norm_op1) + __btod_div_common 0x080018e7 Thumb Code 696 btod.o(CL$$btod_div_common) + _e2e 0x08001c1f Thumb Code 220 btod.o(CL$$btod_e2e) + _btod_ediv 0x08001cfb Thumb Code 42 btod.o(CL$$btod_ediv) + _btod_emul 0x08001d25 Thumb Code 42 btod.o(CL$$btod_emul) + __btod_mult_common 0x08001d4f Thumb Code 580 btod.o(CL$$btod_mult_common) + __ARM_fpclassify 0x08001f93 Thumb Code 48 fpclassify.o(i.__ARM_fpclassify) + __hardfp_sqrtf 0x08001fc3 Thumb Code 58 sqrtf.o(i.__hardfp_sqrtf) + _get_lc_numeric 0x08001ffd Thumb Code 44 lc_numeric_c.o(locale$$code) + __fpl_dretinf 0x08002029 Thumb Code 12 dretinf.o(x$fpl$dretinf) + __aeabi_f2d 0x08002035 Thumb Code 0 f2d.o(x$fpl$f2d) + _f2d 0x08002035 Thumb Code 86 f2d.o(x$fpl$f2d) + __fpl_fnaninf 0x0800208b Thumb Code 140 fnaninf.o(x$fpl$fnaninf) + _fp_init 0x08002117 Thumb Code 26 fpinit.o(x$fpl$fpinit) + __fplib_config_fpu_vfp 0x0800212f Thumb Code 0 fpinit.o(x$fpl$fpinit) + __fplib_config_pureend_doubles 0x0800212f Thumb Code 0 fpinit.o(x$fpl$fpinit) + _printf_fp_dec 0x08002131 Thumb Code 4 printf1.o(x$fpl$printf1) + __I$use$fp 0x08002134 Number 0 usenofp.o(x$fpl$usenofp) + testMarks_f32 0x080021e0 Data 320 main.o(.rodata.testMarks_f32) + testUnity_f32 0x08002320 Data 16 main.o(.rodata.testUnity_f32) + Region$$Table$$Base 0x08002330 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x08002350 Number 0 anon$$obj.o(Region$$Table) numStudents 0x20000000 Data 4 main.o(.data.numStudents) system_core_clock 0x20000004 Data 4 system_at32f435_437.o(.data.system_core_clock) __libspace_start 0x20000008 Data 96 libspace.o(.bss) @@ -3523,88 +3590,88 @@ Memory Map of the image Image Entry point : 0x0800020d - Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00002360, Max: 0x003f0000, ABSOLUTE) + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00002378, Max: 0x003f0000, ABSOLUTE) - Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00002354, Max: 0x003f0000, ABSOLUTE) + Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x0000236c, Max: 0x003f0000, ABSOLUTE) Exec Addr Load Addr Size Type Attr Idx E Section Name Object 0x08000000 0x08000000 0x0000020c Data RO 119 RESET startup_at32f435_437.o 0x0800020c 0x0800020c 0x00000008 Code RO 1485 * !!!main c_w.l(__main.o) - 0x08000214 0x08000214 0x00000034 Code RO 1843 !!!scatter c_w.l(__scatter.o) - 0x08000248 0x08000248 0x0000001a Code RO 1845 !!handler_copy c_w.l(__scatter_copy.o) + 0x08000214 0x08000214 0x00000034 Code RO 1883 !!!scatter c_w.l(__scatter.o) + 0x08000248 0x08000248 0x0000001a Code RO 1885 !!handler_copy c_w.l(__scatter_copy.o) 0x08000262 0x08000262 0x00000002 PAD - 0x08000264 0x08000264 0x0000001c Code RO 1847 !!handler_zi c_w.l(__scatter_zi.o) + 0x08000264 0x08000264 0x0000001c Code RO 1887 !!handler_zi c_w.l(__scatter_zi.o) 0x08000280 0x08000280 0x00000000 Code RO 1474 .ARM.Collect$$_printf_percent$$00000000 c_w.l(_printf_percent.o) 0x08000280 0x08000280 0x00000006 Code RO 1473 .ARM.Collect$$_printf_percent$$00000003 c_w.l(_printf_f.o) - 0x08000286 0x08000286 0x00000004 Code RO 1572 .ARM.Collect$$_printf_percent$$00000017 c_w.l(_printf_percent_end.o) - 0x0800028a 0x0800028a 0x00000002 Code RO 1718 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o) - 0x0800028c 0x0800028c 0x00000004 Code RO 1719 .ARM.Collect$$libinit$$00000001 c_w.l(libinit2.o) - 0x08000290 0x08000290 0x00000000 Code RO 1722 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o) - 0x08000290 0x08000290 0x00000000 Code RO 1725 .ARM.Collect$$libinit$$0000000A c_w.l(libinit2.o) - 0x08000290 0x08000290 0x00000000 Code RO 1727 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o) - 0x08000290 0x08000290 0x00000000 Code RO 1729 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o) - 0x08000290 0x08000290 0x00000006 Code RO 1730 .ARM.Collect$$libinit$$0000000F c_w.l(libinit2.o) - 0x08000296 0x08000296 0x00000000 Code RO 1732 .ARM.Collect$$libinit$$00000011 c_w.l(libinit2.o) - 0x08000296 0x08000296 0x00000000 Code RO 1734 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o) - 0x08000296 0x08000296 0x00000000 Code RO 1736 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o) - 0x08000296 0x08000296 0x0000000a Code RO 1737 .ARM.Collect$$libinit$$00000016 c_w.l(libinit2.o) - 0x080002a0 0x080002a0 0x00000000 Code RO 1738 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o) - 0x080002a0 0x080002a0 0x00000000 Code RO 1740 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o) - 0x080002a0 0x080002a0 0x00000000 Code RO 1742 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o) - 0x080002a0 0x080002a0 0x00000000 Code RO 1744 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o) - 0x080002a0 0x080002a0 0x00000000 Code RO 1746 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o) - 0x080002a0 0x080002a0 0x00000000 Code RO 1748 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o) - 0x080002a0 0x080002a0 0x00000000 Code RO 1750 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o) - 0x080002a0 0x080002a0 0x00000000 Code RO 1752 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o) - 0x080002a0 0x080002a0 0x00000000 Code RO 1756 .ARM.Collect$$libinit$$0000002C c_w.l(libinit2.o) - 0x080002a0 0x080002a0 0x00000000 Code RO 1758 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o) - 0x080002a0 0x080002a0 0x00000000 Code RO 1760 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o) - 0x080002a0 0x080002a0 0x00000000 Code RO 1762 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o) - 0x080002a0 0x080002a0 0x00000002 Code RO 1763 .ARM.Collect$$libinit$$00000033 c_w.l(libinit2.o) - 0x080002a2 0x080002a2 0x00000002 Code RO 1807 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o) - 0x080002a4 0x080002a4 0x00000000 Code RO 1826 .ARM.Collect$$libshutdown$$00000002 c_w.l(libshutdown2.o) - 0x080002a4 0x080002a4 0x00000000 Code RO 1828 .ARM.Collect$$libshutdown$$00000004 c_w.l(libshutdown2.o) - 0x080002a4 0x080002a4 0x00000000 Code RO 1831 .ARM.Collect$$libshutdown$$00000007 c_w.l(libshutdown2.o) - 0x080002a4 0x080002a4 0x00000000 Code RO 1834 .ARM.Collect$$libshutdown$$0000000A c_w.l(libshutdown2.o) - 0x080002a4 0x080002a4 0x00000000 Code RO 1836 .ARM.Collect$$libshutdown$$0000000C c_w.l(libshutdown2.o) - 0x080002a4 0x080002a4 0x00000000 Code RO 1839 .ARM.Collect$$libshutdown$$0000000F c_w.l(libshutdown2.o) - 0x080002a4 0x080002a4 0x00000002 Code RO 1840 .ARM.Collect$$libshutdown$$00000010 c_w.l(libshutdown2.o) - 0x080002a6 0x080002a6 0x00000000 Code RO 1559 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o) - 0x080002a6 0x080002a6 0x00000000 Code RO 1626 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o) - 0x080002a6 0x080002a6 0x00000006 Code RO 1638 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o) - 0x080002ac 0x080002ac 0x00000000 Code RO 1628 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o) - 0x080002ac 0x080002ac 0x00000004 Code RO 1629 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o) - 0x080002b0 0x080002b0 0x00000000 Code RO 1631 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o) - 0x080002b0 0x080002b0 0x00000008 Code RO 1632 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o) - 0x080002b8 0x080002b8 0x00000002 Code RO 1764 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o) - 0x080002ba 0x080002ba 0x00000000 Code RO 1779 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o) - 0x080002ba 0x080002ba 0x00000004 Code RO 1780 .ARM.Collect$$rtexit$$00000003 c_w.l(rtexit2.o) - 0x080002be 0x080002be 0x00000006 Code RO 1781 .ARM.Collect$$rtexit$$00000004 c_w.l(rtexit2.o) + 0x08000286 0x08000286 0x00000004 Code RO 1612 .ARM.Collect$$_printf_percent$$00000017 c_w.l(_printf_percent_end.o) + 0x0800028a 0x0800028a 0x00000002 Code RO 1758 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o) + 0x0800028c 0x0800028c 0x00000004 Code RO 1759 .ARM.Collect$$libinit$$00000001 c_w.l(libinit2.o) + 0x08000290 0x08000290 0x00000000 Code RO 1762 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o) + 0x08000290 0x08000290 0x00000000 Code RO 1765 .ARM.Collect$$libinit$$0000000A c_w.l(libinit2.o) + 0x08000290 0x08000290 0x00000000 Code RO 1767 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o) + 0x08000290 0x08000290 0x00000000 Code RO 1769 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o) + 0x08000290 0x08000290 0x00000006 Code RO 1770 .ARM.Collect$$libinit$$0000000F c_w.l(libinit2.o) + 0x08000296 0x08000296 0x00000000 Code RO 1772 .ARM.Collect$$libinit$$00000011 c_w.l(libinit2.o) + 0x08000296 0x08000296 0x00000000 Code RO 1774 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o) + 0x08000296 0x08000296 0x00000000 Code RO 1776 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o) + 0x08000296 0x08000296 0x0000000a Code RO 1777 .ARM.Collect$$libinit$$00000016 c_w.l(libinit2.o) + 0x080002a0 0x080002a0 0x00000000 Code RO 1778 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o) + 0x080002a0 0x080002a0 0x00000000 Code RO 1780 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o) + 0x080002a0 0x080002a0 0x00000000 Code RO 1782 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o) + 0x080002a0 0x080002a0 0x00000000 Code RO 1784 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o) + 0x080002a0 0x080002a0 0x00000000 Code RO 1786 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o) + 0x080002a0 0x080002a0 0x00000000 Code RO 1788 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o) + 0x080002a0 0x080002a0 0x00000000 Code RO 1790 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o) + 0x080002a0 0x080002a0 0x00000000 Code RO 1792 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o) + 0x080002a0 0x080002a0 0x00000000 Code RO 1796 .ARM.Collect$$libinit$$0000002C c_w.l(libinit2.o) + 0x080002a0 0x080002a0 0x00000000 Code RO 1798 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o) + 0x080002a0 0x080002a0 0x00000000 Code RO 1800 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o) + 0x080002a0 0x080002a0 0x00000000 Code RO 1802 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o) + 0x080002a0 0x080002a0 0x00000002 Code RO 1803 .ARM.Collect$$libinit$$00000033 c_w.l(libinit2.o) + 0x080002a2 0x080002a2 0x00000002 Code RO 1847 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o) + 0x080002a4 0x080002a4 0x00000000 Code RO 1866 .ARM.Collect$$libshutdown$$00000002 c_w.l(libshutdown2.o) + 0x080002a4 0x080002a4 0x00000000 Code RO 1868 .ARM.Collect$$libshutdown$$00000004 c_w.l(libshutdown2.o) + 0x080002a4 0x080002a4 0x00000000 Code RO 1871 .ARM.Collect$$libshutdown$$00000007 c_w.l(libshutdown2.o) + 0x080002a4 0x080002a4 0x00000000 Code RO 1874 .ARM.Collect$$libshutdown$$0000000A c_w.l(libshutdown2.o) + 0x080002a4 0x080002a4 0x00000000 Code RO 1876 .ARM.Collect$$libshutdown$$0000000C c_w.l(libshutdown2.o) + 0x080002a4 0x080002a4 0x00000000 Code RO 1879 .ARM.Collect$$libshutdown$$0000000F c_w.l(libshutdown2.o) + 0x080002a4 0x080002a4 0x00000002 Code RO 1880 .ARM.Collect$$libshutdown$$00000010 c_w.l(libshutdown2.o) + 0x080002a6 0x080002a6 0x00000000 Code RO 1599 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o) + 0x080002a6 0x080002a6 0x00000000 Code RO 1666 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o) + 0x080002a6 0x080002a6 0x00000006 Code RO 1678 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o) + 0x080002ac 0x080002ac 0x00000000 Code RO 1668 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o) + 0x080002ac 0x080002ac 0x00000004 Code RO 1669 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o) + 0x080002b0 0x080002b0 0x00000000 Code RO 1671 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o) + 0x080002b0 0x080002b0 0x00000008 Code RO 1672 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o) + 0x080002b8 0x080002b8 0x00000002 Code RO 1804 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o) + 0x080002ba 0x080002ba 0x00000000 Code RO 1819 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o) + 0x080002ba 0x080002ba 0x00000004 Code RO 1820 .ARM.Collect$$rtexit$$00000003 c_w.l(rtexit2.o) + 0x080002be 0x080002be 0x00000006 Code RO 1821 .ARM.Collect$$rtexit$$00000004 c_w.l(rtexit2.o) 0x080002c4 0x080002c4 0x00000040 Code RO 120 .text startup_at32f435_437.o 0x08000304 0x08000304 0x00000002 Code RO 1441 .text c_w.l(use_no_semi_2.o) 0x08000306 0x08000306 0x00000002 PAD 0x08000308 0x08000308 0x00000018 Code RO 1449 .text c_w.l(noretval__2printf.o) 0x08000320 0x08000320 0x00000068 Code RO 1451 .text c_w.l(__printf.o) 0x08000388 0x08000388 0x00000006 Code RO 1483 .text c_w.l(heapauxi.o) - 0x0800038e 0x0800038e 0x00000002 Code RO 1557 .text c_w.l(use_no_semi.o) - 0x08000390 0x08000390 0x00000016 Code RO 1564 .text c_w.l(_rserrno.o) - 0x080003a6 0x080003a6 0x0000041c Code RO 1566 .text c_w.l(_printf_fp_dec.o) + 0x0800038e 0x0800038e 0x00000002 Code RO 1597 .text c_w.l(use_no_semi.o) + 0x08000390 0x08000390 0x00000016 Code RO 1604 .text c_w.l(_rserrno.o) + 0x080003a6 0x080003a6 0x0000041c Code RO 1606 .text c_w.l(_printf_fp_dec.o) 0x080007c2 0x080007c2 0x00000002 PAD - 0x080007c4 0x080007c4 0x00000024 Code RO 1570 .text c_w.l(_printf_char_file.o) - 0x080007e8 0x080007e8 0x00000008 Code RO 1645 .text c_w.l(rt_locale_intlibspace.o) - 0x080007f0 0x080007f0 0x00000008 Code RO 1650 .text c_w.l(rt_errno_addr_intlibspace.o) - 0x080007f8 0x080007f8 0x0000008a Code RO 1652 .text c_w.l(lludiv10.o) + 0x080007c4 0x080007c4 0x00000024 Code RO 1610 .text c_w.l(_printf_char_file.o) + 0x080007e8 0x080007e8 0x00000008 Code RO 1685 .text c_w.l(rt_locale_intlibspace.o) + 0x080007f0 0x080007f0 0x00000008 Code RO 1690 .text c_w.l(rt_errno_addr_intlibspace.o) + 0x080007f8 0x080007f8 0x0000008a Code RO 1692 .text c_w.l(lludiv10.o) 0x08000882 0x08000882 0x00000002 PAD - 0x08000884 0x08000884 0x00000030 Code RO 1654 .text c_w.l(_printf_char_common.o) - 0x080008b4 0x080008b4 0x00000080 Code RO 1656 .text c_w.l(_printf_fp_infnan.o) - 0x08000934 0x08000934 0x000000e4 Code RO 1658 .text c_w.l(bigflt0.o) - 0x08000a18 0x08000a18 0x00000008 Code RO 1685 .text c_w.l(ferror.o) - 0x08000a20 0x08000a20 0x00000008 Code RO 1696 .text c_w.l(libspace.o) - 0x08000a28 0x08000a28 0x0000004a Code RO 1699 .text c_w.l(sys_stackheap_outer.o) - 0x08000a72 0x08000a72 0x00000012 Code RO 1705 .text c_w.l(exit.o) + 0x08000884 0x08000884 0x00000030 Code RO 1694 .text c_w.l(_printf_char_common.o) + 0x080008b4 0x080008b4 0x00000080 Code RO 1696 .text c_w.l(_printf_fp_infnan.o) + 0x08000934 0x08000934 0x000000e4 Code RO 1698 .text c_w.l(bigflt0.o) + 0x08000a18 0x08000a18 0x00000008 Code RO 1725 .text c_w.l(ferror.o) + 0x08000a20 0x08000a20 0x00000008 Code RO 1736 .text c_w.l(libspace.o) + 0x08000a28 0x08000a28 0x0000004a Code RO 1739 .text c_w.l(sys_stackheap_outer.o) + 0x08000a72 0x08000a72 0x00000012 Code RO 1745 .text c_w.l(exit.o) 0x08000a84 0x08000a84 0x00000004 PAD - 0x08000a88 0x08000a88 0x0000007c Code RO 1711 .text c_w.l(strcmpv7em.o) + 0x08000a88 0x08000a88 0x0000007c Code RO 1751 .text c_w.l(strcmpv7em.o) 0x08000b04 0x08000b04 0x00000002 Code RO 31 .text.BusFault_Handler at32f435_437_int.o 0x08000b06 0x08000b06 0x00000002 PAD 0x08000b08 0x08000b08 0x00000002 Code RO 37 .text.DebugMon_Handler at32f435_437_int.o @@ -3626,88 +3693,88 @@ Memory Map of the image 0x08000b8e 0x08000b8e 0x00000002 PAD 0x08000b90 0x08000b90 0x00000002 Code RO 58 .text._sys_exit at32f435_437_board.o 0x08000b92 0x08000b92 0x00000002 PAD - 0x08000b94 0x08000b94 0x00000140 Code RO 1032 .text.arm_mat_mult_f32 matrixfunctions.o - 0x08000cd4 0x08000cd4 0x000000ce Code RO 1106 .text.arm_max_f32 statisticsfunctions.o - 0x08000da2 0x08000da2 0x00000002 PAD - 0x08000da4 0x08000da4 0x00000080 Code RO 1116 .text.arm_mean_f32 statisticsfunctions.o - 0x08000e24 0x08000e24 0x000000ce Code RO 1124 .text.arm_min_f32 statisticsfunctions.o - 0x08000ef2 0x08000ef2 0x00000002 PAD - 0x08000ef4 0x08000ef4 0x00000044 Code RO 1146 .text.arm_std_f32 statisticsfunctions.o - 0x08000f38 0x08000f38 0x0000012c Code RO 1148 .text.arm_var_f32 statisticsfunctions.o - 0x08001064 0x08001064 0x0000001a Code RO 155 .text.crm_ahb_div_set at32f435_437_crm.o - 0x0800107e 0x0800107e 0x00000002 PAD - 0x08001080 0x08001080 0x0000001a Code RO 157 .text.crm_apb1_div_set at32f435_437_crm.o - 0x0800109a 0x0800109a 0x00000002 PAD - 0x0800109c 0x0800109c 0x0000001a Code RO 159 .text.crm_apb2_div_set at32f435_437_crm.o - 0x080010b6 0x080010b6 0x00000002 PAD - 0x080010b8 0x080010b8 0x00000018 Code RO 167 .text.crm_auto_step_mode_enable at32f435_437_crm.o - 0x080010d0 0x080010d0 0x0000007a Code RO 147 .text.crm_clock_source_enable at32f435_437_crm.o - 0x0800114a 0x0800114a 0x00000002 PAD - 0x0800114c 0x0800114c 0x000000ac Code RO 183 .text.crm_clocks_freq_get at32f435_437_crm.o - 0x080011f8 0x080011f8 0x0000001a Code RO 133 .text.crm_flag_get at32f435_437_crm.o - 0x08001212 0x08001212 0x00000002 PAD - 0x08001214 0x08001214 0x00000028 Code RO 135 .text.crm_hext_stable_wait at32f435_437_crm.o - 0x0800123c 0x0800123c 0x00000028 Code RO 141 .text.crm_periph_clock_enable at32f435_437_crm.o - 0x08001264 0x08001264 0x0000005a Code RO 177 .text.crm_pll_config at32f435_437_crm.o - 0x080012be 0x080012be 0x00000002 PAD - 0x080012c0 0x080012c0 0x00000050 Code RO 127 .text.crm_reset at32f435_437_crm.o - 0x08001310 0x08001310 0x00000012 Code RO 179 .text.crm_sysclk_switch at32f435_437_crm.o - 0x08001322 0x08001322 0x00000002 PAD - 0x08001324 0x08001324 0x00000010 Code RO 181 .text.crm_sysclk_switch_status_get at32f435_437_crm.o - 0x08001334 0x08001334 0x00000024 Code RO 62 .text.fputc at32f435_437_board.o - 0x08001358 0x08001358 0x0000000e Code RO 209 .text.gpio_default_para_init at32f435_437_gpio.o - 0x08001366 0x08001366 0x00000002 PAD - 0x08001368 0x08001368 0x00000084 Code RO 207 .text.gpio_init at32f435_437_gpio.o - 0x080013ec 0x080013ec 0x0000002e Code RO 231 .text.gpio_pin_mux_config at32f435_437_gpio.o - 0x0800141a 0x0800141a 0x00000002 PAD - 0x0800141c 0x0800141c 0x0000014c Code RO 2 .text.main main.o - 0x08001568 0x08001568 0x00000094 Code RO 50 .text.system_clock_config at32f435_437_clock.o - 0x080015fc 0x080015fc 0x0000008c Code RO 107 .text.system_core_clock_update system_at32f435_437.o - 0x08001688 0x08001688 0x0000006e Code RO 64 .text.uart_print_init at32f435_437_board.o - 0x080016f6 0x080016f6 0x00000002 PAD - 0x080016f8 0x080016f8 0x00000008 Code RO 309 .text.usart_data_transmit at32f435_437_usart.o - 0x08001700 0x08001700 0x00000012 Code RO 283 .text.usart_enable at32f435_437_usart.o - 0x08001712 0x08001712 0x00000002 PAD - 0x08001714 0x08001714 0x0000000a Code RO 331 .text.usart_flag_get at32f435_437_usart.o + 0x08000b94 0x08000b94 0x00000158 Code RO 1032 .text.arm_mat_mult_f32 matrixfunctions.o + 0x08000cec 0x08000cec 0x000000ce Code RO 1106 .text.arm_max_f32 statisticsfunctions.o + 0x08000dba 0x08000dba 0x00000002 PAD + 0x08000dbc 0x08000dbc 0x00000080 Code RO 1116 .text.arm_mean_f32 statisticsfunctions.o + 0x08000e3c 0x08000e3c 0x000000ce Code RO 1124 .text.arm_min_f32 statisticsfunctions.o + 0x08000f0a 0x08000f0a 0x00000002 PAD + 0x08000f0c 0x08000f0c 0x00000050 Code RO 1146 .text.arm_std_f32 statisticsfunctions.o + 0x08000f5c 0x08000f5c 0x0000012c Code RO 1148 .text.arm_var_f32 statisticsfunctions.o + 0x08001088 0x08001088 0x0000001a Code RO 155 .text.crm_ahb_div_set at32f435_437_crm.o + 0x080010a2 0x080010a2 0x00000002 PAD + 0x080010a4 0x080010a4 0x0000001a Code RO 157 .text.crm_apb1_div_set at32f435_437_crm.o + 0x080010be 0x080010be 0x00000002 PAD + 0x080010c0 0x080010c0 0x0000001a Code RO 159 .text.crm_apb2_div_set at32f435_437_crm.o + 0x080010da 0x080010da 0x00000002 PAD + 0x080010dc 0x080010dc 0x0000001a Code RO 167 .text.crm_auto_step_mode_enable at32f435_437_crm.o + 0x080010f6 0x080010f6 0x00000002 PAD + 0x080010f8 0x080010f8 0x0000007a Code RO 147 .text.crm_clock_source_enable at32f435_437_crm.o + 0x08001172 0x08001172 0x00000002 PAD + 0x08001174 0x08001174 0x000000ac Code RO 183 .text.crm_clocks_freq_get at32f435_437_crm.o + 0x08001220 0x08001220 0x0000001a Code RO 133 .text.crm_flag_get at32f435_437_crm.o + 0x0800123a 0x0800123a 0x00000002 PAD + 0x0800123c 0x0800123c 0x00000028 Code RO 135 .text.crm_hext_stable_wait at32f435_437_crm.o + 0x08001264 0x08001264 0x00000028 Code RO 141 .text.crm_periph_clock_enable at32f435_437_crm.o + 0x0800128c 0x0800128c 0x0000005a Code RO 177 .text.crm_pll_config at32f435_437_crm.o + 0x080012e6 0x080012e6 0x00000002 PAD + 0x080012e8 0x080012e8 0x00000050 Code RO 127 .text.crm_reset at32f435_437_crm.o + 0x08001338 0x08001338 0x00000012 Code RO 179 .text.crm_sysclk_switch at32f435_437_crm.o + 0x0800134a 0x0800134a 0x00000002 PAD + 0x0800134c 0x0800134c 0x00000010 Code RO 181 .text.crm_sysclk_switch_status_get at32f435_437_crm.o + 0x0800135c 0x0800135c 0x00000024 Code RO 62 .text.fputc at32f435_437_board.o + 0x08001380 0x08001380 0x0000000e Code RO 209 .text.gpio_default_para_init at32f435_437_gpio.o + 0x0800138e 0x0800138e 0x00000002 PAD + 0x08001390 0x08001390 0x00000084 Code RO 207 .text.gpio_init at32f435_437_gpio.o + 0x08001414 0x08001414 0x0000002e Code RO 231 .text.gpio_pin_mux_config at32f435_437_gpio.o + 0x08001442 0x08001442 0x00000002 PAD + 0x08001444 0x08001444 0x0000014c Code RO 2 .text.main main.o + 0x08001590 0x08001590 0x00000094 Code RO 50 .text.system_clock_config at32f435_437_clock.o + 0x08001624 0x08001624 0x0000008c Code RO 107 .text.system_core_clock_update system_at32f435_437.o + 0x080016b0 0x080016b0 0x0000006e Code RO 64 .text.uart_print_init at32f435_437_board.o 0x0800171e 0x0800171e 0x00000002 PAD - 0x08001720 0x08001720 0x000000b4 Code RO 279 .text.usart_init at32f435_437_usart.o - 0x080017d4 0x080017d4 0x00000012 Code RO 285 .text.usart_transmitter_enable at32f435_437_usart.o - 0x080017e6 0x080017e6 0x0000003e Code RO 1661 CL$$btod_d2e c_w.l(btod.o) - 0x08001824 0x08001824 0x00000046 Code RO 1663 CL$$btod_d2e_denorm_low c_w.l(btod.o) - 0x0800186a 0x0800186a 0x00000060 Code RO 1662 CL$$btod_d2e_norm_op1 c_w.l(btod.o) - 0x080018ca 0x080018ca 0x00000002 PAD - 0x080018cc 0x080018cc 0x00000338 Code RO 1671 CL$$btod_div_common c_w.l(btod.o) - 0x08001c04 0x08001c04 0x000000dc Code RO 1668 CL$$btod_e2e c_w.l(btod.o) - 0x08001ce0 0x08001ce0 0x0000002a Code RO 1665 CL$$btod_ediv c_w.l(btod.o) - 0x08001d0a 0x08001d0a 0x0000002a Code RO 1664 CL$$btod_emul c_w.l(btod.o) - 0x08001d34 0x08001d34 0x00000244 Code RO 1670 CL$$btod_mult_common c_w.l(btod.o) - 0x08001f78 0x08001f78 0x00000030 Code RO 1694 i.__ARM_fpclassify m_wm.l(fpclassify.o) - 0x08001fa8 0x08001fa8 0x0000003a Code RO 1545 i.__hardfp_sqrtf m_wm.l(sqrtf.o) - 0x08001fe2 0x08001fe2 0x00000002 PAD - 0x08001fe4 0x08001fe4 0x0000002c Code RO 1690 locale$$code c_w.l(lc_numeric_c.o) - 0x08002010 0x08002010 0x0000000c Code RO 1583 x$fpl$dretinf fz_wm.l(dretinf.o) - 0x0800201c 0x0800201c 0x00000056 Code RO 1509 x$fpl$f2d fz_wm.l(f2d.o) - 0x08002072 0x08002072 0x0000008c Code RO 1585 x$fpl$fnaninf fz_wm.l(fnaninf.o) - 0x080020fe 0x080020fe 0x0000001a Code RO 1776 x$fpl$fpinit fz_wm.l(fpinit.o) - 0x08002118 0x08002118 0x00000004 Code RO 1515 x$fpl$printf1 fz_wm.l(printf1.o) - 0x0800211c 0x0800211c 0x00000000 Code RO 1591 x$fpl$usenofp fz_wm.l(usenofp.o) - 0x0800211c 0x0800211c 0x00000094 Data RO 1659 .constdata c_w.l(bigflt0.o) - 0x080021b0 0x080021b0 0x00000008 Data RO 11 .rodata..L__const.main.dstC main.o - 0x080021b8 0x080021b8 0x00000008 Data RO 8 .rodata..L__const.main.srcA main.o - 0x080021c0 0x080021c0 0x00000008 Data RO 9 .rodata..L__const.main.srcB main.o - 0x080021c8 0x080021c8 0x00000140 Data RO 4 .rodata.testMarks_f32 main.o - 0x08002308 0x08002308 0x00000010 Data RO 5 .rodata.testUnity_f32 main.o - 0x08002318 0x08002318 0x00000020 Data RO 1842 Region$$Table anon$$obj.o - 0x08002338 0x08002338 0x0000001c Data RO 1689 locale$$data c_w.l(lc_numeric_c.o) + 0x08001720 0x08001720 0x00000008 Code RO 309 .text.usart_data_transmit at32f435_437_usart.o + 0x08001728 0x08001728 0x00000012 Code RO 283 .text.usart_enable at32f435_437_usart.o + 0x0800173a 0x0800173a 0x00000002 PAD + 0x0800173c 0x0800173c 0x0000000a Code RO 331 .text.usart_flag_get at32f435_437_usart.o + 0x08001746 0x08001746 0x00000002 PAD + 0x08001748 0x08001748 0x000000a6 Code RO 279 .text.usart_init at32f435_437_usart.o + 0x080017ee 0x080017ee 0x00000002 PAD + 0x080017f0 0x080017f0 0x00000012 Code RO 285 .text.usart_transmitter_enable at32f435_437_usart.o + 0x08001802 0x08001802 0x0000003e Code RO 1701 CL$$btod_d2e c_w.l(btod.o) + 0x08001840 0x08001840 0x00000046 Code RO 1703 CL$$btod_d2e_denorm_low c_w.l(btod.o) + 0x08001886 0x08001886 0x00000060 Code RO 1702 CL$$btod_d2e_norm_op1 c_w.l(btod.o) + 0x080018e6 0x080018e6 0x00000338 Code RO 1711 CL$$btod_div_common c_w.l(btod.o) + 0x08001c1e 0x08001c1e 0x000000dc Code RO 1708 CL$$btod_e2e c_w.l(btod.o) + 0x08001cfa 0x08001cfa 0x0000002a Code RO 1705 CL$$btod_ediv c_w.l(btod.o) + 0x08001d24 0x08001d24 0x0000002a Code RO 1704 CL$$btod_emul c_w.l(btod.o) + 0x08001d4e 0x08001d4e 0x00000244 Code RO 1710 CL$$btod_mult_common c_w.l(btod.o) + 0x08001f92 0x08001f92 0x00000030 Code RO 1734 i.__ARM_fpclassify m_wm.l(fpclassify.o) + 0x08001fc2 0x08001fc2 0x0000003a Code RO 1573 i.__hardfp_sqrtf m_wm.l(sqrtf.o) + 0x08001ffc 0x08001ffc 0x0000002c Code RO 1730 locale$$code c_w.l(lc_numeric_c.o) + 0x08002028 0x08002028 0x0000000c Code RO 1623 x$fpl$dretinf fz_wm.l(dretinf.o) + 0x08002034 0x08002034 0x00000056 Code RO 1509 x$fpl$f2d fz_wm.l(f2d.o) + 0x0800208a 0x0800208a 0x0000008c Code RO 1625 x$fpl$fnaninf fz_wm.l(fnaninf.o) + 0x08002116 0x08002116 0x0000001a Code RO 1816 x$fpl$fpinit fz_wm.l(fpinit.o) + 0x08002130 0x08002130 0x00000004 Code RO 1515 x$fpl$printf1 fz_wm.l(printf1.o) + 0x08002134 0x08002134 0x00000000 Code RO 1631 x$fpl$usenofp fz_wm.l(usenofp.o) + 0x08002134 0x08002134 0x00000094 Data RO 1699 .constdata c_w.l(bigflt0.o) + 0x080021c8 0x080021c8 0x00000008 Data RO 11 .rodata..L__const.main.dstC main.o + 0x080021d0 0x080021d0 0x00000008 Data RO 8 .rodata..L__const.main.srcA main.o + 0x080021d8 0x080021d8 0x00000008 Data RO 9 .rodata..L__const.main.srcB main.o + 0x080021e0 0x080021e0 0x00000140 Data RO 4 .rodata.testMarks_f32 main.o + 0x08002320 0x08002320 0x00000010 Data RO 5 .rodata.testUnity_f32 main.o + 0x08002330 0x08002330 0x00000020 Data RO 1882 Region$$Table anon$$obj.o + 0x08002350 0x08002350 0x0000001c Data RO 1729 locale$$data c_w.l(lc_numeric_c.o) - Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x08002358, Size: 0x00000818, Max: 0x00060000, ABSOLUTE) + Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x08002370, Size: 0x00000818, Max: 0x00060000, ABSOLUTE) Exec Addr Load Addr Size Type Attr Idx E Section Name Object - 0x20000000 0x08002358 0x00000004 Data RW 6 .data.numStudents main.o - 0x20000004 0x0800235c 0x00000004 Data RW 109 .data.system_core_clock system_at32f435_437.o - 0x20000008 - 0x00000060 Zero RW 1697 .bss c_w.l(libspace.o) + 0x20000000 0x08002370 0x00000004 Data RW 6 .data.numStudents main.o + 0x20000004 0x08002374 0x00000004 Data RW 109 .data.system_core_clock system_at32f435_437.o + 0x20000008 - 0x00000060 Zero RW 1737 .bss c_w.l(libspace.o) 0x20000068 - 0x00000054 Zero RW 96 .bss.__stdout at32f435_437_board.o 0x200000bc - 0x00000004 Zero RW 12 .bss.max_marks main.o 0x200000c0 - 0x00000004 Zero RW 15 .bss.mean main.o @@ -3716,7 +3783,7 @@ Memory Map of the image 0x200000cc - 0x00000004 Zero RW 13 .bss.student_num main.o 0x200000d0 - 0x00000140 Zero RW 10 .bss.testOutput main.o 0x20000210 - 0x00000004 Zero RW 17 .bss.var main.o - 0x20000214 0x08002360 0x00000004 PAD + 0x20000214 0x08002378 0x00000004 PAD 0x20000218 - 0x00000200 Zero RW 118 HEAP startup_at32f435_437.o 0x20000418 - 0x00000400 Zero RW 117 STACK startup_at32f435_437.o @@ -3728,22 +3795,22 @@ Image component sizes Code (inc. data) RO Data RW Data ZI Data Debug Object Name - 148 0 0 0 84 15093 at32f435_437_board.o - 148 0 0 0 0 8573 at32f435_437_clock.o - 706 38 0 0 0 28784 at32f435_437_crm.o - 192 0 0 0 0 12226 at32f435_437_gpio.o - 18 0 0 0 0 1072 at32f435_437_int.o - 234 0 0 0 0 13213 at32f435_437_usart.o - 332 64 360 4 344 1693 main.o - 320 4 0 0 0 41169 matrixfunctions.o + 148 0 0 0 84 14950 at32f435_437_board.o + 148 0 0 0 0 8560 at32f435_437_clock.o + 708 38 0 0 0 28145 at32f435_437_crm.o + 192 0 0 0 0 12061 at32f435_437_gpio.o + 18 0 0 0 0 1082 at32f435_437_int.o + 220 0 0 0 0 12663 at32f435_437_usart.o + 332 64 360 4 344 1461 main.o + 344 4 0 0 0 43566 matrixfunctions.o 64 26 524 0 1536 1044 startup_at32f435_437.o - 908 12 0 0 0 24028 statisticsfunctions.o - 244 24 0 4 0 11861 system_at32f435_437.o + 920 12 0 0 0 23010 statisticsfunctions.o + 244 24 0 4 0 11832 system_at32f435_437.o ---------------------------------------------------------------------- - 3362 168 916 8 1968 158756 Object Totals + 3390 168 916 8 1968 158374 Object Totals 0 0 32 0 0 0 (incl. Generated) - 48 0 0 0 4 0 (incl. Padding) + 52 0 0 0 4 0 (incl. Padding) ---------------------------------------------------------------------- @@ -3766,7 +3833,7 @@ Image component sizes 4 0 0 0 0 0 _printf_percent_end.o 22 0 0 0 0 100 _rserrno.o 228 4 148 0 0 96 bigflt0.o - 1936 128 0 0 0 668 btod.o + 1936 128 0 0 0 672 btod.o 18 0 0 0 0 80 exit.o 8 0 0 0 0 68 ferror.o 6 0 0 0 0 152 heapauxi.o @@ -3796,19 +3863,19 @@ Image component sizes 58 0 0 0 0 136 sqrtf.o ---------------------------------------------------------------------- - 4590 200 176 0 96 3344 Library Totals - 16 0 0 0 0 0 (incl. Padding) + 4586 200 176 0 96 3348 Library Totals + 12 0 0 0 0 0 (incl. Padding) ---------------------------------------------------------------------- Code (inc. data) RO Data RW Data ZI Data Debug Library Name - 4200 192 176 0 96 2472 c_w.l + 4200 192 176 0 96 2476 c_w.l 268 8 0 0 0 612 fz_wm.l 106 0 0 0 0 260 m_wm.l ---------------------------------------------------------------------- - 4590 200 176 0 96 3344 Library Totals + 4586 200 176 0 96 3348 Library Totals ---------------------------------------------------------------------- @@ -3817,15 +3884,15 @@ Image component sizes Code (inc. data) RO Data RW Data ZI Data Debug - 7952 368 1092 8 2064 160120 Grand Totals - 7952 368 1092 8 2064 160120 ELF Image Totals - 7952 368 1092 8 0 0 ROM Totals + 7976 368 1092 8 2064 159778 Grand Totals + 7976 368 1092 8 2064 159778 ELF Image Totals + 7976 368 1092 8 0 0 ROM Totals ============================================================================== - Total RO Size (Code + RO Data) 9044 ( 8.83kB) + Total RO Size (Code + RO Data) 9068 ( 8.86kB) Total RW Size (RW Data + ZI Data) 2072 ( 2.02kB) - Total ROM Size (Code + RO Data + RW Data) 9052 ( 8.84kB) + Total ROM Size (Code + RO Data + RW Data) 9076 ( 8.86kB) ============================================================================== diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Listings/startup_at32f435_437.lst b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Listings/startup_at32f435_437.lst index 0b46c26f..073f78fd 100644 --- a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Listings/startup_at32f435_437.lst +++ b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Listings/startup_at32f435_437.lst @@ -737,10 +737,11 @@ ARM Macro Assembler Page 12 00000000 Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4.fp.sp --depen d=.\objects\startup_at32f435_437.d -o.\objects\startup_at32f435_437.o -IC:\User -s\Arm\Packs\ArteryTek\AT32F435_437_DFP\2.1.0\Device\Include --predefine="__UVIS -ION_VERSION SETA 536" --predefine="AT32F435ZMT7 SETA 1" --list=.\listings\start -up_at32f435_437.lst ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\startu -p\mdk\startup_at32f435_437.s +s\sheltonyu\AppData\Local\Arm\Packs\ArteryTek\AT32F435_437_DFP\2.0.1\Device\Inc +lude -IC:\Keil_v5\ARM\CMSIS\Include --predefine="__UVISION_VERSION SETA 531" -- +predefine="AT32F435ZMT7 SETA 1" --list=.\listings\startup_at32f435_437.lst ..\. +.\..\..\..\..\libraries\cmsis\cm4\device_support\startup\mdk\startup_at32f435_4 +37.s diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_board.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_board.o index c1db1cd4..4c59327b 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_board.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_board.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_clock.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_clock.o index 3d860b72..14c45db7 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_clock.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_clock.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_crm.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_crm.o index 0307a0eb..7ee50be8 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_crm.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_crm.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_gpio.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_gpio.o index c6999efa..8527211a 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_gpio.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_gpio.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_int.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_int.o index 22147fe7..0da5e01b 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_int.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_int.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_misc.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_misc.o index 8f366398..3fcaab67 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_misc.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_misc.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_usart.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_usart.o index bdb07bed..e5ffc4d0 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_usart.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/at32f435_437_usart.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/basicmathfunctions.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/basicmathfunctions.o index 757385e3..54ad0856 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/basicmathfunctions.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/basicmathfunctions.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/bayesfunctions.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/bayesfunctions.o index 8e525a9a..4c3823d4 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/bayesfunctions.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/bayesfunctions.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.axf b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.axf index 80622458..6e824df7 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.axf and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.axf differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.build_log.htm b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.build_log.htm index ed3a97a4..db0794ed 100644 --- a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.build_log.htm +++ b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.build_log.htm @@ -3,55 +3,55 @@ 
 
Vision Build Log

 
Tool Versions:

-IDE-Version: Vision V5.36.0.0
-Copyright (C) 2021 ARM Ltd and ARM Germany GmbH. All rights reserved.
-License Information: ATK ATK, ATK, LIC=WHYH9-49PHK-74XS0-BHWL1-YISFU-3H549
+IDE-Version: Vision V5.31.0.0
+Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: dd admin, dd, LIC=PE7DL-0FWKW-2Z1W4-FBZ7U-PL126-VPCQJ
  
 Tool Versions:
-Toolchain:       MDK-ARM Plus  Version: 5.36.0.0
+Toolchain:       MDK-ARM Plus  Version: 5.31.0.0
 Toolchain Path:  C:\Keil_v5\ARM\ARMCLANG\Bin
-C Compiler:      ArmClang.exe V6.16
-Assembler:       Armasm.exe V6.16
-Linker/Locator:  ArmLink.exe V6.16
-Library Manager: ArmAr.exe V6.16
-Hex Converter:   FromElf.exe V6.16
-CPU DLL:         SARMCM3.DLL V5.36.0.0
+C Compiler:      ArmClang.exe V6.14
+Assembler:       Armasm.exe V6.14
+Linker/Locator:  ArmLink.exe V6.14
+Library Manager: ArmAr.exe V6.14
+Hex Converter:   FromElf.exe V6.14
+CPU DLL:         SARMCM3.DLL V5.31.0.0
 Dialog DLL:      DCM.DLL V1.17.3.0
-Target DLL:      UL2CM3.DLL V1.164.0.0
-Dialog DLL:      TCM.DLL V1.53.0.0
+Target DLL:      UL2CM3.DLL V1.163.4.0
+Dialog DLL:      TCM.DLL V1.46.0.0
  
 
Project:

-D:\WorkSrc\BSPs_PACKs\package_shell\AT32F435_437_Firmware_Library_V2.1.1\project\at_start_f435\examples\cortex_m4\cmsis_dsp\mdk_v5\cmsis_dsp.uvprojx
-Project File Date:  11/17/2022
+F:\WorkSrc\BSPs_PACKs\package_shell\AT32F435_437_Firmware_Library_V2.1.2\project\at_start_f435\examples\cortex_m4\cmsis_dsp\mdk_v5\cmsis_dsp.uvprojx
+Project File Date:  02/17/2023
 
 
Output:

-*** Using Compiler 'V6.16', folder: 'C:\Keil_v5\ARM\ARMCLANG\Bin'
+*** Using Compiler 'V6.14', folder: 'C:\Keil_v5\ARM\ARMCLANG\Bin'
 Build target 'cmsis_dsp'
-compiling at32f435_437_clock.c...
-compiling at32f435_437_int.c...
-compiling main.c...
 assembling startup_at32f435_437.s...
+compiling at32f435_437_clock.c...
 compiling system_at32f435_437.c...
-compiling at32f435_437_board.c...
-compiling at32f435_437_crm.c...
+compiling at32f435_437_int.c...
 compiling at32f435_437_gpio.c...
-compiling at32f435_437_misc.c...
+compiling at32f435_437_board.c...
+compiling main.c...
 compiling at32f435_437_usart.c...
+compiling at32f435_437_misc.c...
+compiling at32f435_437_crm.c...
 compiling BayesFunctions.c...
 compiling BasicMathFunctions.c...
-compiling ComplexMathFunctions.c...
 compiling ControllerFunctions.c...
-compiling DistanceFunctions.c...
+compiling ComplexMathFunctions.c...
 compiling FastMathFunctions.c...
-compiling CommonTables.c...
+compiling DistanceFunctions.c...
 compiling SVMFunctions.c...
-compiling MatrixFunctions.c...
 compiling StatisticsFunctions.c...
+compiling MatrixFunctions.c...
 compiling SupportFunctions.c...
+compiling CommonTables.c...
 compiling TransformFunctions.c...
 compiling FilteringFunctions.c...
 linking...
-Program Size: Code=7952 RO-data=1092 RW-data=8 ZI-data=2064  
+Program Size: Code=7976 RO-data=1092 RW-data=8 ZI-data=2064  
 FromELF: creating hex file...
 ".\Objects\cmsis_dsp.axf" - 0 Error(s), 0 Warning(s).
 
@@ -59,14 +59,14 @@ FromELF: creating hex file...
 
 Package Vendor: ArteryTek
                 
-                ArteryTek.AT32F435_437_DFP.2.1.0
+                ArteryTek.AT32F435_437_DFP.2.0.1
                 ArteryTek AT32F4 Series Device Support,Drivers
 
 
Collection of Component include folders:

-  C:\Users\Arm\Packs\ArteryTek\AT32F435_437_DFP\2.1.0\Device\Include
+  C:\Users\sheltonyu\AppData\Local\Arm\Packs\ArteryTek\AT32F435_437_DFP\2.0.1\Device\Include
 
 
Collection of Component Files used:

-Build Time Elapsed:  00:00:07
+Build Time Elapsed:  00:00:06
diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.hex b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.hex index 6f0400ce..75289b17 100644 --- a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.hex +++ b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.hex @@ -35,14 +35,14 @@ :1002100000F049F80AA090E8000C82448344AAF157 :100220000107DA4501D100F03EF8AFF2090EBAE855 :100230000F0013F0010F18BFFB1A43F0010318471A -:10024000D8200000F8200000103A24BF78C878C1F8 +:10024000F020000010210000103A24BF78C878C1C7 :10025000FAD8520724BF30C830C144BF04680C60CC :10026000704700000023002400250026103A28BF14 :1002700078C1FBD8520728BF30C148BF0B60704718 -:10028000662901F04987002070471FB501F037FF4C -:1002900000F0AAFA04000020002101F0A3FEE060B3 +:10028000662901F05587002070471FB501F043FF34 +:1002900000F0AAFA04000020002101F0AFFEE060A7 :1002A0001FBD10B510BD00F0BFFB1146FFF7EDFFFD -:1002B00001F0B4F800F0DDFB03B4FFF7F2FF03BC7C +:1002B00001F0C8F800F0DDFB03B4FFF7F2FF03BC68 :1002C00000F066FC0948804709480047FEE7FEE762 :1002D000FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE7F6 :1002E00004480549054A064B70470000250B0008E5 @@ -69,11 +69,11 @@ :10043000FBDB30460022002121540B99C1F80880D3 :10044000C1E900200FB0BDE8F08FBD1B6D1CDEE7D9 :100450004A4600DA694206A800F06CFA06AB93E857 -:10046000070003AB83E8070050460A9901F0BBF987 +:10046000070003AB83E8070050460A9901F0C9F979 :100470008DE80700A0F500501F3800900398002D6C :100480000ADD42F21F014A460844002303A90390F3 -:10049000684601F025FC09E0A0F500504A461F38E7 -:1004A000002303A90390684601F02FFC8DE80700A4 +:10049000684601F032FC09E0A0F500504A461F38DA +:1004A000002303A90390684601F03CFC8DE8070097 :1004B0000004000C03D04FF0FF30410800E010466C :1004C000B8F1000F03D00022009215461EE0751E01 :1004D00005D400F091F9303262556D1EF9D5B3465E @@ -86,7 +86,7 @@ :100540000B98099AC0F80880C0E9002B7AE71126B9 :100550004FF0000857E72DE9F04F88460446D21DBA :1005600022F0070191B0D1E90001CDE90A0101F0C3 -:1005700003FD02460B98C00F01D02D2007E0206834 +:1005700010FD02460B98C00F01D02D2007E0206827 :10058000810701D52B2002E0202101EAC000032AC7 :10059000099001D0072A05DB03464146204600F0BA :1005A00089F90BE12078800601D5E06900E006209A @@ -125,7 +125,7 @@ :1007B000A7F10107F3DC2046AFF30080032011B05E :1007C00041E60000074B70B50D467B4400F05FF832 :1007D0000446284600F020F910B14FF0FF3070BDFC -:1007E000204670BD670B00000048704728000020BD +:1007E000204670BD8F0B0000004870472800002095 :1007F000004870470800002030B5B0F10A0271F1DE :1008000000034FEA900E4EEA817EB0EB0E0061EBE2 :1008100091014FEA101E4EEA017E10EB0E0041EBF3 @@ -152,15 +152,15 @@ :10096000F1F290FBF1F5A5F1800501FB12041B3CAF :1009700002D56442012000E00020DFF898A0804604 :100980000027FA44AAF1BE0A0EE0E0070AD0324678 -:10099000684607EB470101230AEB810101F0B5F935 +:10099000684607EB470101230AEB810101F0C2F928 :1009A0008DE8070064107F1C002CEED1194F7F44A6 :1009B000AE3F19E0E80715D007EB04100DF1180A57 :1009C00090E80E008AE80E00C068F04201D1981944 -:1009D00008903246012306A903A801F096F903AB5B +:1009D00008903246012306A903A801F0A3F903AB4E :1009E00083E807006D10641C002DE3D14FF0010374 -:1009F00032466946B8F1000F03A802D001F070F941 -:100A000001E001F082F9C9E90001C9F808200AB043 -:100A1000BDE8F08754180000007B00F080007047AC +:1009F00032466946B8F1000F03A802D001F07DF934 +:100A000001E001F08FF9C9E90001C9F808200AB036 +:100A1000BDE8F0876C180000007B00F08000704794 :100A200000487047080000207546FFF7F9FFAE4602 :100A300005006946534620F00700854618B020B5EA :100A4000FFF74EFCBDE820404FF000064FF00007D6 @@ -184,386 +184,388 @@ :100B6000FF73CFF6F2631A4043F202030A600022D9 :100B7000C0F203038A604B60C1F8A0204FF41F024B :100B8000CA604FF0006140F8801C7047FEE700002B -:100B9000704700002DE9F04F88B047880B889F42CE -:100BA00040F08B80058813889D4240F08880B1F822 -:100BB00002E053889E4540F08480466848689FED77 -:100BC000440A02905068BC080190B80007F0030B7B -:100BD000A6F1100200904FEA0E104FEA8E0100239A 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+:10217000B5400000504BCFD06607E2CF0100000011 +:102180006C4100003E8251AADFEEA734010000003E +:10219000D9420000DCB5A0E23A301F97FFFFFFFFF5 +:1021A000B4450000FD25A0C8E9A3C14FFFFFFFFF14 +:1021B000FF3F00000000008000000000FF3F000023 +:1021C000000000800000000014000100D00000208A +:1021D00014000400E021000804000100202300088E +:1021E00000002842000014420000A2420000E0412A +:1021F0000000A64200009042000010420000184279 +:102200000000004200004C4200007C42000080427E +:102210000000C2420000A4420000BE420000B442DE +:102220000000844200004C42000058420000284256 +:102230000000864200006042000034420000644218 +:102240000000864200008A4200000C42000050421A +:102250000000E8410000A2420000684200003C4249 +:1022600000001842000098420000C8420000E84107 +:102270000000044200003C420000E84100004842E7 +:10228000000008420000244200007442000038426E +:10229000000050420000484200004042000010424E +:1022A00000003C4200005C4200003042000020423E +:1022B0000000C8420000BC420000A84200001442D6 +:1022C0000000004200008E4200003C4200009A42A2 +:1022D0000000F841000048420000444200000C4267 +:1022E00000007C4200008642000020420000F841CD +:1022F0000000E841000088420000744200001842DB +:102300000000F8410000E0410000E0410000984278 +:1023100000005C42000004420000E84100001C4252 +:102320000000803F0000803F0000803F0000803FB1 +:102330007023000800000020080000004802000888 +:10234000782300080800002010080000640200083C +:102350001C00000043000000F8FFFFFF0C0000001D +:102360000E0000000F0000002E0000000000000022 +:082370001400000000127A00C5 :040000050800020DE0 :00000001FF diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.htm b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.htm index 97df4968..d09cabcf 100644 --- a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.htm +++ b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.htm @@ -3,7 +3,7 @@ Static Call Graph - [.\Objects\cmsis_dsp.axf]

Static Call Graph for image .\Objects\cmsis_dsp.axf

-

#<CALLGRAPH># ARM Linker, 6160001: Last Updated: Thu Nov 17 20:19:38 2022 +

#<CALLGRAPH># ARM Linker, 6140002: Last Updated: Fri Feb 17 14:43:44 2023

Maximum Stack Usage = 324 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)

Call chain for Maximum Stack Depth:

@@ -647,10 +647,10 @@ Global Symbols

_printf_fp_dec_real (Thumb, 620 bytes, Stack size 104 bytes, _printf_fp_dec.o(.text))

[Stack]

  • Max Depth = 324
  • Call Chain = _printf_fp_dec_real ⇒ _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e
-
[Calls]
  • >>   _fp_digits -
  • >>   __ARM_fpclassify +
    [Calls]
    • >>   __ARM_fpclassify
    • >>   _printf_fp_infnan
    • >>   __rt_locale +
    • >>   _fp_digits

    [Called By]
    • >>   _printf_fp_dec
    @@ -666,8 +666,8 @@ Global Symbols

__rt_locale (Thumb, 8 bytes, Stack size 0 bytes, rt_locale_intlibspace.o(.text)) -

[Called By]

  • >>   _printf_fp_dec_real -
  • >>   __rt_lib_init_lc_common +

    [Called By]
    • >>   __rt_lib_init_lc_common +
    • >>   _printf_fp_dec_real

    __aeabi_errno_addr (Thumb, 8 bytes, Stack size 0 bytes, rt_errno_addr_intlibspace.o(.text)) @@ -796,7 +796,7 @@ Global Symbols

    [Called By]

    • >>   __rt_exit_exit
    -

    arm_mat_mult_f32 (Thumb, 320 bytes, Stack size 68 bytes, matrixfunctions.o(.text.arm_mat_mult_f32)) +

    arm_mat_mult_f32 (Thumb, 344 bytes, Stack size 68 bytes, matrixfunctions.o(.text.arm_mat_mult_f32))

    [Stack]

    • Max Depth = 68
    • Call Chain = arm_mat_mult_f32

    [Called By]
    • >>   main @@ -820,8 +820,8 @@ Global Symbols
      [Called By]
      • >>   main
      -

      arm_std_f32 (Thumb, 68 bytes, Stack size 16 bytes, statisticsfunctions.o(.text.arm_std_f32)) -

      [Stack]

      • Max Depth = 40
      • Call Chain = arm_std_f32 ⇒ __hardfp_sqrtf ⇒ __set_errno +

        arm_std_f32 (Thumb, 80 bytes, Stack size 24 bytes, statisticsfunctions.o(.text.arm_std_f32)) +

        [Stack]

        • Max Depth = 48
        • Call Chain = arm_std_f32 ⇒ __hardfp_sqrtf ⇒ __set_errno

        [Calls]
        • >>   arm_var_f32
        • >>   __hardfp_sqrtf @@ -848,7 +848,7 @@ Global Symbols

          [Called By]
          • >>   system_clock_config
          -

          crm_auto_step_mode_enable (Thumb, 24 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_auto_step_mode_enable)) +

          crm_auto_step_mode_enable (Thumb, 26 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_auto_step_mode_enable))

          [Called By]

          • >>   system_clock_config
          @@ -856,7 +856,7 @@ Global Symbols

          [Called By]
          • >>   system_clock_config
          -

          crm_clocks_freq_get (Thumb, 140 bytes, Stack size 16 bytes, at32f435_437_crm.o(.text.crm_clocks_freq_get)) +

          crm_clocks_freq_get (Thumb, 172 bytes, Stack size 16 bytes, at32f435_437_crm.o(.text.crm_clocks_freq_get))

          [Stack]

          • Max Depth = 16
          • Call Chain = crm_clocks_freq_get

          [Calls]
          • >>   crm_sysclk_switch_status_get @@ -877,7 +877,7 @@ Global Symbols
            [Called By]
            • >>   system_clock_config
            -

            crm_periph_clock_enable (Thumb, 40 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_periph_clock_enable)) +

            crm_periph_clock_enable (Thumb, 40 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_periph_clock_enable))

            [Called By]

            • >>   uart_print_init
            • >>   system_clock_config
            @@ -888,7 +888,7 @@ Global Symbols
            [Called By]
            • >>   system_clock_config
            -

            crm_reset (Thumb, 80 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_reset)) +

            crm_reset (Thumb, 80 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_reset))

            [Called By]

            • >>   system_clock_config
            @@ -897,9 +897,9 @@ Global Symbols

          crm_sysclk_switch_status_get (Thumb, 16 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_sysclk_switch_status_get)) -

          [Called By]

          • >>   crm_clocks_freq_get -
          • >>   system_core_clock_update +

            [Called By]
            • >>   system_core_clock_update
            • >>   system_clock_config +
            • >>   crm_clocks_freq_get

            fputc (Thumb, 36 bytes, Stack size 16 bytes, at32f435_437_board.o(.text.fputc)) @@ -926,7 +926,7 @@ Global Symbols
            [Called By]

            • >>   uart_print_init
            -

            main (Thumb, 268 bytes, Stack size 56 bytes, main.o(.text.main)) +

            main (Thumb, 332 bytes, Stack size 56 bytes, main.o(.text.main))

            [Stack]

            • Max Depth = 184 + Unknown Stack Size
            • Call Chain = main ⇒ __2printf ⇒ _printf_char_file ⇒ _printf_char_common ⇒ __printf
            @@ -950,9 +950,9 @@ Global Symbols
            [Calls]
            • >>   system_core_clock_update
            • >>   crm_sysclk_switch_status_get
            • >>   crm_sysclk_switch -
            • >>   crm_reset +
            • >>   crm_reset
            • >>   crm_pll_config -
            • >>   crm_periph_clock_enable +
            • >>   crm_periph_clock_enable
            • >>   crm_hext_stable_wait
            • >>   crm_flag_get
            • >>   crm_clock_source_enable @@ -964,7 +964,7 @@ Global Symbols
              [Called By]
              • >>   main
              -

              system_core_clock_update (Thumb, 116 bytes, Stack size 16 bytes, system_at32f435_437.o(.text.system_core_clock_update)) +

              system_core_clock_update (Thumb, 140 bytes, Stack size 16 bytes, system_at32f435_437.o(.text.system_core_clock_update))

              [Stack]

              • Max Depth = 16
              • Call Chain = system_core_clock_update

              [Calls]
              • >>   crm_sysclk_switch_status_get @@ -981,7 +981,7 @@ Global Symbols
              • >>   gpio_pin_mux_config
              • >>   gpio_init
              • >>   gpio_default_para_init -
              • >>   crm_periph_clock_enable +
              • >>   crm_periph_clock_enable

              [Called By]
              • >>   main
              @@ -998,7 +998,7 @@ Global Symbols

              [Called By]
              • >>   fputc
              -

              usart_init (Thumb, 180 bytes, Stack size 40 bytes, at32f435_437_usart.o(.text.usart_init)) +

              usart_init (Thumb, 166 bytes, Stack size 40 bytes, at32f435_437_usart.o(.text.usart_init))

              [Stack]

              • Max Depth = 56
              • Call Chain = usart_init ⇒ crm_clocks_freq_get

              [Calls]
              • >>   crm_clocks_freq_get @@ -1045,8 +1045,8 @@ Global Symbols
                [Calls]
                • >>   _e2e
                • >>   __btod_div_common
                -
                [Called By]
                • >>   _fp_digits -
                • >>   _btod_etento +
                  [Called By]
                  • >>   _btod_etento +
                  • >>   _fp_digits

                  _btod_emul (Thumb, 42 bytes, Stack size 28 bytes, btod.o(CL$$btod_emul)) @@ -1055,8 +1055,8 @@ Global Symbols
                  [Calls]

                  • >>   __btod_mult_common
                  • >>   _e2e
                  -
                  [Called By]
                  • >>   _fp_digits -
                  • >>   _btod_etento +
                    [Called By]
                    • >>   _btod_etento +
                    • >>   _fp_digits

                    __btod_mult_common (Thumb, 580 bytes, Stack size 16 bytes, btod.o(CL$$btod_mult_common)) diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/commontables.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/commontables.o index 47071a52..10432b6e 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/commontables.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/commontables.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/complexmathfunctions.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/complexmathfunctions.o index 0938a575..314991ea 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/complexmathfunctions.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/complexmathfunctions.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/controllerfunctions.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/controllerfunctions.o index 65df9afa..b23ba738 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/controllerfunctions.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/controllerfunctions.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/distancefunctions.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/distancefunctions.o index 5a7dd7ee..21efdb58 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/distancefunctions.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/distancefunctions.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/fastmathfunctions.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/fastmathfunctions.o index ddc01232..25dd88aa 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/fastmathfunctions.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/fastmathfunctions.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/filteringfunctions.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/filteringfunctions.o index ed04e7b9..e65b7388 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/filteringfunctions.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/filteringfunctions.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/main.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/main.o index cd5d2825..ecf4fb4c 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/main.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/main.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/matrixfunctions.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/matrixfunctions.o index b3a7014a..30388280 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/matrixfunctions.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/matrixfunctions.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/startup_at32f435_437.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/startup_at32f435_437.o index e6e0ea18..9080cf18 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/startup_at32f435_437.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/startup_at32f435_437.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/statisticsfunctions.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/statisticsfunctions.o index 939808b1..e370e959 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/statisticsfunctions.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/statisticsfunctions.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/supportfunctions.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/supportfunctions.o index d62ad42a..b85c0d7e 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/supportfunctions.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/supportfunctions.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/svmfunctions.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/svmfunctions.o index dfa8fb4d..84990d9c 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/svmfunctions.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/svmfunctions.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/system_at32f435_437.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/system_at32f435_437.o index bbe900e3..67b64c24 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/system_at32f435_437.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/system_at32f435_437.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/transformfunctions.o b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/transformfunctions.o index 8e6def2d..4a009193 100644 Binary files a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/transformfunctions.o and b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/transformfunctions.o differ diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvoptx b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvoptx index e8533c9e..8eb72788 100644 --- a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvoptx +++ b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvprojx b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvprojx index ff182e3c..73a4798d 100644 --- a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvprojx +++ b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -543,6 +543,11 @@ template + + + + + 0 1 diff --git a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/src/at32f435_437_clock.c b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/src/at32f435_437_clock.c index 91da3687..902401af 100644 --- a/project/at_start_f435/examples/cortex_m4/cmsis_dsp/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/cortex_m4/cmsis_dsp/src/at32f435_437_clock.c @@ -54,6 +54,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -63,9 +66,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/cortex_m4/fpu/inc/at32f435_437_conf.h b/project/at_start_f435/examples/cortex_m4/fpu/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/cortex_m4/fpu/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/cortex_m4/fpu/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/cortex_m4/fpu/mdk_v5/fpu.uvoptx b/project/at_start_f435/examples/cortex_m4/fpu/mdk_v5/fpu.uvoptx index b6b394f7..045b747b 100644 --- a/project/at_start_f435/examples/cortex_m4/fpu/mdk_v5/fpu.uvoptx +++ b/project/at_start_f435/examples/cortex_m4/fpu/mdk_v5/fpu.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/cortex_m4/fpu/mdk_v5/fpu.uvprojx b/project/at_start_f435/examples/cortex_m4/fpu/mdk_v5/fpu.uvprojx index 8d65d5a8..2d773be2 100644 --- a/project/at_start_f435/examples/cortex_m4/fpu/mdk_v5/fpu.uvprojx +++ b/project/at_start_f435/examples/cortex_m4/fpu/mdk_v5/fpu.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -938,6 +938,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/cortex_m4/fpu/src/at32f435_437_clock.c b/project/at_start_f435/examples/cortex_m4/fpu/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/cortex_m4/fpu/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/cortex_m4/fpu/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/cortex_m4/systick_interrupt/inc/at32f435_437_conf.h b/project/at_start_f435/examples/cortex_m4/systick_interrupt/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/cortex_m4/systick_interrupt/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/cortex_m4/systick_interrupt/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvoptx b/project/at_start_f435/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvoptx index 4b5a62d8..f60bf271 100644 --- a/project/at_start_f435/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvoptx +++ b/project/at_start_f435/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvprojx b/project/at_start_f435/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvprojx index 5cb0edae..d49552d4 100644 --- a/project/at_start_f435/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvprojx +++ b/project/at_start_f435/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/cortex_m4/systick_interrupt/src/at32f435_437_clock.c b/project/at_start_f435/examples/cortex_m4/systick_interrupt/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/cortex_m4/systick_interrupt/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/cortex_m4/systick_interrupt/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/crc/calculation/inc/at32f435_437_conf.h b/project/at_start_f435/examples/crc/calculation/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/crc/calculation/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/crc/calculation/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/crc/calculation/mdk_v5/calculation.uvoptx b/project/at_start_f435/examples/crc/calculation/mdk_v5/calculation.uvoptx index 8c0edb6a..a884eca7 100644 --- a/project/at_start_f435/examples/crc/calculation/mdk_v5/calculation.uvoptx +++ b/project/at_start_f435/examples/crc/calculation/mdk_v5/calculation.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/crc/calculation/mdk_v5/calculation.uvprojx b/project/at_start_f435/examples/crc/calculation/mdk_v5/calculation.uvprojx index a5d41d2b..25a24c58 100644 --- a/project/at_start_f435/examples/crc/calculation/mdk_v5/calculation.uvprojx +++ b/project/at_start_f435/examples/crc/calculation/mdk_v5/calculation.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/crc/calculation/src/at32f435_437_clock.c b/project/at_start_f435/examples/crc/calculation/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/crc/calculation/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/crc/calculation/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/crm/clock_failure_detection/inc/at32f435_437_conf.h b/project/at_start_f435/examples/crm/clock_failure_detection/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/crm/clock_failure_detection/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/crm/clock_failure_detection/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvoptx b/project/at_start_f435/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvoptx index 383402ff..1e6136fd 100644 --- a/project/at_start_f435/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvoptx +++ b/project/at_start_f435/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvprojx b/project/at_start_f435/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvprojx index 185b00cd..4e580ba9 100644 --- a/project/at_start_f435/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvprojx +++ b/project/at_start_f435/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/crm/clock_failure_detection/src/at32f435_437_clock.c b/project/at_start_f435/examples/crm/clock_failure_detection/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/crm/clock_failure_detection/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/crm/clock_failure_detection/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/crm/clock_failure_detection/src/main.c b/project/at_start_f435/examples/crm/clock_failure_detection/src/main.c index cca7ff60..89a581d4 100644 --- a/project/at_start_f435/examples/crm/clock_failure_detection/src/main.c +++ b/project/at_start_f435/examples/crm/clock_failure_detection/src/main.c @@ -108,6 +108,9 @@ void clock_failure_detection_handler(void) */ static void sclk_288m_hick_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -117,9 +120,6 @@ static void sclk_288m_hick_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); /* wait till hick is ready */ diff --git a/project/at_start_f435/examples/crm/pll_parameter_calculate/inc/at32f435_437_conf.h b/project/at_start_f435/examples/crm/pll_parameter_calculate/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/crm/pll_parameter_calculate/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/crm/pll_parameter_calculate/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvoptx b/project/at_start_f435/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvoptx index 0361ceef..919fcb17 100644 --- a/project/at_start_f435/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvoptx +++ b/project/at_start_f435/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvprojx b/project/at_start_f435/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvprojx index 0a08b44a..107ff993 100644 --- a/project/at_start_f435/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvprojx +++ b/project/at_start_f435/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/crm/pll_parameter_calculate/src/at32f435_437_clock.c b/project/at_start_f435/examples/crm/pll_parameter_calculate/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/crm/pll_parameter_calculate/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/crm/pll_parameter_calculate/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/crm/pll_parameter_calculate/src/main.c b/project/at_start_f435/examples/crm/pll_parameter_calculate/src/main.c index 260a0d03..f8db328f 100644 --- a/project/at_start_f435/examples/crm/pll_parameter_calculate/src/main.c +++ b/project/at_start_f435/examples/crm/pll_parameter_calculate/src/main.c @@ -85,6 +85,9 @@ void system_clock_config_200mhz(void) { uint16_t pll_ns, pll_ms, pll_fr; + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -94,9 +97,6 @@ void system_clock_config_200mhz(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/crm/sysclk_switch/inc/at32f435_437_conf.h b/project/at_start_f435/examples/crm/sysclk_switch/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/crm/sysclk_switch/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/crm/sysclk_switch/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvoptx b/project/at_start_f435/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvoptx index 0fdaff14..931dec8a 100644 --- a/project/at_start_f435/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvoptx +++ b/project/at_start_f435/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvprojx b/project/at_start_f435/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvprojx index 0edafc60..f6909e15 100644 --- a/project/at_start_f435/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvprojx +++ b/project/at_start_f435/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/crm/sysclk_switch/src/at32f435_437_clock.c b/project/at_start_f435/examples/crm/sysclk_switch/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/crm/sysclk_switch/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/crm/sysclk_switch/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/crm/sysclk_switch/src/main.c b/project/at_start_f435/examples/crm/sysclk_switch/src/main.c index ed3b25bd..afe7de79 100644 --- a/project/at_start_f435/examples/crm/sysclk_switch/src/main.c +++ b/project/at_start_f435/examples/crm/sysclk_switch/src/main.c @@ -105,6 +105,9 @@ static void switch_system_clock(void) */ static void sclk_64m_hick_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -114,9 +117,6 @@ static void sclk_64m_hick_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); /* wait till hick is ready */ @@ -192,6 +192,9 @@ static void sclk_64m_hick_config(void) */ static void sclk_96m_hext_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -201,9 +204,6 @@ static void sclk_96m_hext_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/dac/double_mode_dma_sinewave/inc/at32f435_437_conf.h b/project/at_start_f435/examples/dac/double_mode_dma_sinewave/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/dac/double_mode_dma_sinewave/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/dac/double_mode_dma_sinewave/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvoptx b/project/at_start_f435/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvoptx index 2f7303b2..8c6de5fe 100644 --- a/project/at_start_f435/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvoptx +++ b/project/at_start_f435/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvprojx b/project/at_start_f435/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvprojx index 27f81dbf..a2e90eee 100644 --- a/project/at_start_f435/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvprojx +++ b/project/at_start_f435/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/dac/double_mode_dma_sinewave/src/at32f435_437_clock.c b/project/at_start_f435/examples/dac/double_mode_dma_sinewave/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/dac/double_mode_dma_sinewave/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/dac/double_mode_dma_sinewave/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/dac/double_mode_dma_squarewave/inc/at32f435_437_conf.h b/project/at_start_f435/examples/dac/double_mode_dma_squarewave/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/dac/double_mode_dma_squarewave/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/dac/double_mode_dma_squarewave/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvoptx b/project/at_start_f435/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvoptx index 9a08980b..e7de7808 100644 --- a/project/at_start_f435/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvoptx +++ b/project/at_start_f435/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvprojx b/project/at_start_f435/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvprojx index 707998bb..1a7e628c 100644 --- a/project/at_start_f435/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvprojx +++ b/project/at_start_f435/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/dac/double_mode_dma_squarewave/src/at32f435_437_clock.c b/project/at_start_f435/examples/dac/double_mode_dma_squarewave/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/dac/double_mode_dma_squarewave/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/dac/double_mode_dma_squarewave/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/dac/one_dac_dma_escalator/inc/at32f435_437_conf.h b/project/at_start_f435/examples/dac/one_dac_dma_escalator/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/dac/one_dac_dma_escalator/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/dac/one_dac_dma_escalator/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvoptx b/project/at_start_f435/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvoptx index 1ab4b9aa..c56d041f 100644 --- a/project/at_start_f435/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvoptx +++ b/project/at_start_f435/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvprojx b/project/at_start_f435/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvprojx index a9a08d32..80b26b28 100644 --- a/project/at_start_f435/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvprojx +++ b/project/at_start_f435/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/dac/one_dac_dma_escalator/src/at32f435_437_clock.c b/project/at_start_f435/examples/dac/one_dac_dma_escalator/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/dac/one_dac_dma_escalator/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/dac/one_dac_dma_escalator/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/dac/one_dac_noisewave/inc/at32f435_437_conf.h b/project/at_start_f435/examples/dac/one_dac_noisewave/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/dac/one_dac_noisewave/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/dac/one_dac_noisewave/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvoptx b/project/at_start_f435/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvoptx index 77cfb1ab..404ca3e7 100644 --- a/project/at_start_f435/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvoptx +++ b/project/at_start_f435/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvprojx b/project/at_start_f435/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvprojx index 6d30644b..0f29c55c 100644 --- a/project/at_start_f435/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvprojx +++ b/project/at_start_f435/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/dac/one_dac_noisewave/src/at32f435_437_clock.c b/project/at_start_f435/examples/dac/one_dac_noisewave/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/dac/one_dac_noisewave/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/dac/one_dac_noisewave/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/dac/two_dac_trianglewave/inc/at32f435_437_conf.h b/project/at_start_f435/examples/dac/two_dac_trianglewave/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/dac/two_dac_trianglewave/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/dac/two_dac_trianglewave/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvoptx b/project/at_start_f435/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvoptx index 56171a5a..4c2c000d 100644 --- a/project/at_start_f435/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvoptx +++ b/project/at_start_f435/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvprojx b/project/at_start_f435/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvprojx index 0f986923..25123b50 100644 --- a/project/at_start_f435/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvprojx +++ b/project/at_start_f435/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/dac/two_dac_trianglewave/src/at32f435_437_clock.c b/project/at_start_f435/examples/dac/two_dac_trianglewave/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/dac/two_dac_trianglewave/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/dac/two_dac_trianglewave/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/debug/tmr1/inc/at32f435_437_conf.h b/project/at_start_f435/examples/debug/tmr1/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/debug/tmr1/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/debug/tmr1/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/debug/tmr1/mdk_v5/tmr1.uvoptx b/project/at_start_f435/examples/debug/tmr1/mdk_v5/tmr1.uvoptx index e7c69390..d89d2de7 100644 --- a/project/at_start_f435/examples/debug/tmr1/mdk_v5/tmr1.uvoptx +++ b/project/at_start_f435/examples/debug/tmr1/mdk_v5/tmr1.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/debug/tmr1/mdk_v5/tmr1.uvprojx b/project/at_start_f435/examples/debug/tmr1/mdk_v5/tmr1.uvprojx index 6c0d7c1e..79e8b970 100644 --- a/project/at_start_f435/examples/debug/tmr1/mdk_v5/tmr1.uvprojx +++ b/project/at_start_f435/examples/debug/tmr1/mdk_v5/tmr1.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/debug/tmr1/src/at32f435_437_clock.c b/project/at_start_f435/examples/debug/tmr1/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/debug/tmr1/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/debug/tmr1/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/dma/dmamux_data_to_gpio/inc/at32f435_437_conf.h b/project/at_start_f435/examples/dma/dmamux_data_to_gpio/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/dma/dmamux_data_to_gpio/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/dma/dmamux_data_to_gpio/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvoptx b/project/at_start_f435/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvoptx index 09cfdb1b..9b5e9ebe 100644 --- a/project/at_start_f435/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvoptx +++ b/project/at_start_f435/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvprojx b/project/at_start_f435/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvprojx index 7b589909..3ceb5ed8 100644 --- a/project/at_start_f435/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvprojx +++ b/project/at_start_f435/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/dma/dmamux_data_to_gpio/src/at32f435_437_clock.c b/project/at_start_f435/examples/dma/dmamux_data_to_gpio/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/dma/dmamux_data_to_gpio/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/dma/dmamux_data_to_gpio/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/dma/dmamux_genertor_exint/inc/at32f435_437_conf.h b/project/at_start_f435/examples/dma/dmamux_genertor_exint/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/dma/dmamux_genertor_exint/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/dma/dmamux_genertor_exint/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx b/project/at_start_f435/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx index d7f66ce9..2e0124c9 100644 --- a/project/at_start_f435/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx +++ b/project/at_start_f435/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx b/project/at_start_f435/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx index 09dee0a7..7940b6e3 100644 --- a/project/at_start_f435/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx +++ b/project/at_start_f435/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/dma/dmamux_genertor_exint/src/at32f435_437_clock.c b/project/at_start_f435/examples/dma/dmamux_genertor_exint/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/dma/dmamux_genertor_exint/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/dma/dmamux_genertor_exint/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/dma/dmamux_synchronization_exint/inc/at32f435_437_conf.h b/project/at_start_f435/examples/dma/dmamux_synchronization_exint/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/dma/dmamux_synchronization_exint/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/dma/dmamux_synchronization_exint/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx b/project/at_start_f435/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx index 4083d76d..3336133f 100644 --- a/project/at_start_f435/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx +++ b/project/at_start_f435/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx b/project/at_start_f435/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx index 5b3e4330..ed3a769d 100644 --- a/project/at_start_f435/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx +++ b/project/at_start_f435/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/dma/dmamux_synchronization_exint/src/at32f435_437_clock.c b/project/at_start_f435/examples/dma/dmamux_synchronization_exint/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/dma/dmamux_synchronization_exint/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/dma/dmamux_synchronization_exint/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/dma/flash_to_sram/inc/at32f435_437_conf.h b/project/at_start_f435/examples/dma/flash_to_sram/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/dma/flash_to_sram/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/dma/flash_to_sram/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx b/project/at_start_f435/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx index 6fffa0c8..033c02d2 100644 --- a/project/at_start_f435/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx +++ b/project/at_start_f435/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx b/project/at_start_f435/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx index 1acf4918..9c374bdf 100644 --- a/project/at_start_f435/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx +++ b/project/at_start_f435/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/dma/flash_to_sram/src/at32f435_437_clock.c b/project/at_start_f435/examples/dma/flash_to_sram/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/dma/flash_to_sram/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/dma/flash_to_sram/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/dvp/ov2640_capture/inc/at32f435_437_conf.h b/project/at_start_f435/examples/dvp/ov2640_capture/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/dvp/ov2640_capture/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/dvp/ov2640_capture/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvoptx b/project/at_start_f435/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvoptx index 38d12c78..aa55cbf0 100644 --- a/project/at_start_f435/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvoptx +++ b/project/at_start_f435/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvprojx b/project/at_start_f435/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvprojx index afa880d4..e7a2b424 100644 --- a/project/at_start_f435/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvprojx +++ b/project/at_start_f435/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -523,6 +523,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/dvp/ov2640_capture/src/at32f435_437_clock.c b/project/at_start_f435/examples/dvp/ov2640_capture/src/at32f435_437_clock.c index 2589036e..0250becc 100644 --- a/project/at_start_f435/examples/dvp/ov2640_capture/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/dvp/ov2640_capture/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/dvp/ov5640_capture/inc/at32f435_437_conf.h b/project/at_start_f435/examples/dvp/ov5640_capture/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/dvp/ov5640_capture/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/dvp/ov5640_capture/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvoptx b/project/at_start_f435/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvoptx index 860733e9..fc3106db 100644 --- a/project/at_start_f435/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvoptx +++ b/project/at_start_f435/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvprojx b/project/at_start_f435/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvprojx index 58d3a724..5854489b 100644 --- a/project/at_start_f435/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvprojx +++ b/project/at_start_f435/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -523,6 +523,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/dvp/ov5640_capture/src/at32f435_437_clock.c b/project/at_start_f435/examples/dvp/ov5640_capture/src/at32f435_437_clock.c index 2589036e..0250becc 100644 --- a/project/at_start_f435/examples/dvp/ov5640_capture/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/dvp/ov5640_capture/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/edma/burst_mode/inc/at32f435_437_conf.h b/project/at_start_f435/examples/edma/burst_mode/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/edma/burst_mode/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/edma/burst_mode/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/edma/burst_mode/mdk_v5/burst_mode.uvoptx b/project/at_start_f435/examples/edma/burst_mode/mdk_v5/burst_mode.uvoptx index 38c6031e..84fba8f4 100644 --- a/project/at_start_f435/examples/edma/burst_mode/mdk_v5/burst_mode.uvoptx +++ b/project/at_start_f435/examples/edma/burst_mode/mdk_v5/burst_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/edma/burst_mode/mdk_v5/burst_mode.uvprojx b/project/at_start_f435/examples/edma/burst_mode/mdk_v5/burst_mode.uvprojx index dda0a59f..360b651a 100644 --- a/project/at_start_f435/examples/edma/burst_mode/mdk_v5/burst_mode.uvprojx +++ b/project/at_start_f435/examples/edma/burst_mode/mdk_v5/burst_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/edma/burst_mode/src/at32f435_437_clock.c b/project/at_start_f435/examples/edma/burst_mode/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/edma/burst_mode/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/edma/burst_mode/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/edma/dmamux_genertor_exint/inc/at32f435_437_conf.h b/project/at_start_f435/examples/edma/dmamux_genertor_exint/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/edma/dmamux_genertor_exint/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/edma/dmamux_genertor_exint/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx b/project/at_start_f435/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx index 56164c1e..315def29 100644 --- a/project/at_start_f435/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx +++ b/project/at_start_f435/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx b/project/at_start_f435/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx index 5c0ecbd0..86825123 100644 --- a/project/at_start_f435/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx +++ b/project/at_start_f435/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/edma/dmamux_genertor_exint/src/at32f435_437_clock.c b/project/at_start_f435/examples/edma/dmamux_genertor_exint/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/edma/dmamux_genertor_exint/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/edma/dmamux_genertor_exint/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/edma/dmamux_synchronization_exint/inc/at32f435_437_conf.h b/project/at_start_f435/examples/edma/dmamux_synchronization_exint/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/edma/dmamux_synchronization_exint/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/edma/dmamux_synchronization_exint/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx b/project/at_start_f435/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx index b21f5871..93d8453f 100644 --- a/project/at_start_f435/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx +++ b/project/at_start_f435/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx b/project/at_start_f435/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx index 6aa6c92f..0263638f 100644 --- a/project/at_start_f435/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx +++ b/project/at_start_f435/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/edma/dmamux_synchronization_exint/src/at32f435_437_clock.c b/project/at_start_f435/examples/edma/dmamux_synchronization_exint/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/edma/dmamux_synchronization_exint/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/edma/dmamux_synchronization_exint/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/edma/flash_to_sram/inc/at32f435_437_conf.h b/project/at_start_f435/examples/edma/flash_to_sram/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/edma/flash_to_sram/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/edma/flash_to_sram/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx b/project/at_start_f435/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx index ea82f21a..7d87f28c 100644 --- a/project/at_start_f435/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx +++ b/project/at_start_f435/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx b/project/at_start_f435/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx index 3f74de4f..55300d3b 100644 --- a/project/at_start_f435/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx +++ b/project/at_start_f435/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/edma/flash_to_sram/src/at32f435_437_clock.c b/project/at_start_f435/examples/edma/flash_to_sram/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/edma/flash_to_sram/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/edma/flash_to_sram/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/inc/at32f435_437_conf.h b/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvoptx b/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvoptx index a8431fe5..e0c31dbe 100644 --- a/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvoptx +++ b/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvprojx b/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvprojx index 18a0459a..c348b7fa 100644 --- a/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvprojx +++ b/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/src/at32f435_437_clock.c b/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/edma/i2s_halfduplex_edma_doublebuffer/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/edma/link_list_mode/inc/at32f435_437_conf.h b/project/at_start_f435/examples/edma/link_list_mode/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/edma/link_list_mode/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/edma/link_list_mode/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvoptx b/project/at_start_f435/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvoptx index c9a6e308..c6f19703 100644 --- a/project/at_start_f435/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvoptx +++ b/project/at_start_f435/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvprojx b/project/at_start_f435/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvprojx index d190a6be..7cdead5f 100644 --- a/project/at_start_f435/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvprojx +++ b/project/at_start_f435/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/edma/link_list_mode/src/at32f435_437_clock.c b/project/at_start_f435/examples/edma/link_list_mode/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/edma/link_list_mode/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/edma/link_list_mode/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/edma/two_dimension_mode/inc/at32f435_437_conf.h b/project/at_start_f435/examples/edma/two_dimension_mode/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/edma/two_dimension_mode/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/edma/two_dimension_mode/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvoptx b/project/at_start_f435/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvoptx index 93925f9c..0dce17b0 100644 --- a/project/at_start_f435/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvoptx +++ b/project/at_start_f435/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvprojx b/project/at_start_f435/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvprojx index 7eb9be08..469b5c3b 100644 --- a/project/at_start_f435/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvprojx +++ b/project/at_start_f435/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/edma/two_dimension_mode/src/at32f435_437_clock.c b/project/at_start_f435/examples/edma/two_dimension_mode/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/edma/two_dimension_mode/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/edma/two_dimension_mode/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/ertc/bpr_domain/inc/at32f435_437_conf.h b/project/at_start_f435/examples/ertc/bpr_domain/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/ertc/bpr_domain/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/ertc/bpr_domain/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvoptx b/project/at_start_f435/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvoptx index 04903fac..517d70a4 100644 --- a/project/at_start_f435/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvoptx +++ b/project/at_start_f435/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvprojx b/project/at_start_f435/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvprojx index 678594cf..99e05454 100644 --- a/project/at_start_f435/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvprojx +++ b/project/at_start_f435/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/ertc/bpr_domain/src/at32f435_437_clock.c b/project/at_start_f435/examples/ertc/bpr_domain/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/ertc/bpr_domain/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/ertc/bpr_domain/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/ertc/calendar/inc/at32f435_437_conf.h b/project/at_start_f435/examples/ertc/calendar/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/ertc/calendar/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/ertc/calendar/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/ertc/calendar/mdk_v5/calendar.uvoptx b/project/at_start_f435/examples/ertc/calendar/mdk_v5/calendar.uvoptx index 094bc50d..dceeeb4f 100644 --- a/project/at_start_f435/examples/ertc/calendar/mdk_v5/calendar.uvoptx +++ b/project/at_start_f435/examples/ertc/calendar/mdk_v5/calendar.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/ertc/calendar/mdk_v5/calendar.uvprojx b/project/at_start_f435/examples/ertc/calendar/mdk_v5/calendar.uvprojx index f8d99bac..2c2e0acd 100644 --- a/project/at_start_f435/examples/ertc/calendar/mdk_v5/calendar.uvprojx +++ b/project/at_start_f435/examples/ertc/calendar/mdk_v5/calendar.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/ertc/calendar/src/at32f435_437_clock.c b/project/at_start_f435/examples/ertc/calendar/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/ertc/calendar/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/ertc/calendar/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/ertc/lick_calibration/inc/at32f435_437_conf.h b/project/at_start_f435/examples/ertc/lick_calibration/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/ertc/lick_calibration/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/ertc/lick_calibration/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvoptx b/project/at_start_f435/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvoptx index 9938a422..ee0bd027 100644 --- a/project/at_start_f435/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvoptx +++ b/project/at_start_f435/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvprojx b/project/at_start_f435/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvprojx index 9daf4bee..778ef871 100644 --- a/project/at_start_f435/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvprojx +++ b/project/at_start_f435/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/ertc/lick_calibration/src/at32f435_437_clock.c b/project/at_start_f435/examples/ertc/lick_calibration/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/ertc/lick_calibration/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/ertc/lick_calibration/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/ertc/tamper/inc/at32f435_437_conf.h b/project/at_start_f435/examples/ertc/tamper/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/ertc/tamper/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/ertc/tamper/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/ertc/tamper/mdk_v5/tamper.uvoptx b/project/at_start_f435/examples/ertc/tamper/mdk_v5/tamper.uvoptx index 85b93cd3..09a5aa4c 100644 --- a/project/at_start_f435/examples/ertc/tamper/mdk_v5/tamper.uvoptx +++ b/project/at_start_f435/examples/ertc/tamper/mdk_v5/tamper.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/ertc/tamper/mdk_v5/tamper.uvprojx b/project/at_start_f435/examples/ertc/tamper/mdk_v5/tamper.uvprojx index 6a877ba2..3eb2f4ce 100644 --- a/project/at_start_f435/examples/ertc/tamper/mdk_v5/tamper.uvprojx +++ b/project/at_start_f435/examples/ertc/tamper/mdk_v5/tamper.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/ertc/tamper/src/at32f435_437_clock.c b/project/at_start_f435/examples/ertc/tamper/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/ertc/tamper/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/ertc/tamper/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/ertc/time_stamp/inc/at32f435_437_conf.h b/project/at_start_f435/examples/ertc/time_stamp/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/ertc/time_stamp/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/ertc/time_stamp/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/ertc/time_stamp/mdk_v5/time_stamp.uvoptx b/project/at_start_f435/examples/ertc/time_stamp/mdk_v5/time_stamp.uvoptx index 38133b13..e2d3752c 100644 --- a/project/at_start_f435/examples/ertc/time_stamp/mdk_v5/time_stamp.uvoptx +++ b/project/at_start_f435/examples/ertc/time_stamp/mdk_v5/time_stamp.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/ertc/time_stamp/mdk_v5/time_stamp.uvprojx b/project/at_start_f435/examples/ertc/time_stamp/mdk_v5/time_stamp.uvprojx index 7b3b714d..e876c147 100644 --- a/project/at_start_f435/examples/ertc/time_stamp/mdk_v5/time_stamp.uvprojx +++ b/project/at_start_f435/examples/ertc/time_stamp/mdk_v5/time_stamp.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/ertc/time_stamp/src/at32f435_437_clock.c b/project/at_start_f435/examples/ertc/time_stamp/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/ertc/time_stamp/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/ertc/time_stamp/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/ertc/wakeup_timer/inc/at32f435_437_conf.h b/project/at_start_f435/examples/ertc/wakeup_timer/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/ertc/wakeup_timer/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/ertc/wakeup_timer/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvoptx b/project/at_start_f435/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvoptx index 06e0af97..6c8e4aeb 100644 --- a/project/at_start_f435/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvoptx +++ b/project/at_start_f435/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvprojx b/project/at_start_f435/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvprojx index bbb3c6e2..b034c009 100644 --- a/project/at_start_f435/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvprojx +++ b/project/at_start_f435/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/ertc/wakeup_timer/src/at32f435_437_clock.c b/project/at_start_f435/examples/ertc/wakeup_timer/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/ertc/wakeup_timer/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/ertc/wakeup_timer/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/exint/exint_config/inc/at32f435_437_conf.h b/project/at_start_f435/examples/exint/exint_config/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/exint/exint_config/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/exint/exint_config/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/exint/exint_config/mdk_v5/exint_config.uvoptx b/project/at_start_f435/examples/exint/exint_config/mdk_v5/exint_config.uvoptx index a9883c86..c5ab60dd 100644 --- a/project/at_start_f435/examples/exint/exint_config/mdk_v5/exint_config.uvoptx +++ b/project/at_start_f435/examples/exint/exint_config/mdk_v5/exint_config.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/exint/exint_config/mdk_v5/exint_config.uvprojx b/project/at_start_f435/examples/exint/exint_config/mdk_v5/exint_config.uvprojx index c995f39b..61973792 100644 --- a/project/at_start_f435/examples/exint/exint_config/mdk_v5/exint_config.uvprojx +++ b/project/at_start_f435/examples/exint/exint_config/mdk_v5/exint_config.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/exint/exint_config/src/at32f435_437_clock.c b/project/at_start_f435/examples/exint/exint_config/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/exint/exint_config/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/exint/exint_config/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/exint/exint_software_trigger/inc/at32f435_437_conf.h b/project/at_start_f435/examples/exint/exint_software_trigger/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/exint/exint_software_trigger/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/exint/exint_software_trigger/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvoptx b/project/at_start_f435/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvoptx index 3ae04b41..14c2c932 100644 --- a/project/at_start_f435/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvoptx +++ b/project/at_start_f435/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvprojx b/project/at_start_f435/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvprojx index c32343e2..30001a0f 100644 --- a/project/at_start_f435/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvprojx +++ b/project/at_start_f435/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/exint/exint_software_trigger/src/at32f435_437_clock.c b/project/at_start_f435/examples/exint/exint_software_trigger/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/exint/exint_software_trigger/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/exint/exint_software_trigger/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/flash/fap_enable/inc/at32f435_437_conf.h b/project/at_start_f435/examples/flash/fap_enable/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/flash/fap_enable/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/flash/fap_enable/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/flash/fap_enable/mdk_v5/fap_enable.uvoptx b/project/at_start_f435/examples/flash/fap_enable/mdk_v5/fap_enable.uvoptx index cb27125e..9cc31ba7 100644 --- a/project/at_start_f435/examples/flash/fap_enable/mdk_v5/fap_enable.uvoptx +++ b/project/at_start_f435/examples/flash/fap_enable/mdk_v5/fap_enable.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/flash/fap_enable/mdk_v5/fap_enable.uvprojx b/project/at_start_f435/examples/flash/fap_enable/mdk_v5/fap_enable.uvprojx index ede84bf1..e10f6301 100644 --- a/project/at_start_f435/examples/flash/fap_enable/mdk_v5/fap_enable.uvprojx +++ b/project/at_start_f435/examples/flash/fap_enable/mdk_v5/fap_enable.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,12 @@ fap_enable + + + + + + 0 1 diff --git a/project/at_start_f435/examples/flash/fap_enable/src/at32f435_437_clock.c b/project/at_start_f435/examples/flash/fap_enable/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/flash/fap_enable/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/flash/fap_enable/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/flash/flash_write_read/inc/at32f435_437_conf.h b/project/at_start_f435/examples/flash/flash_write_read/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/flash/flash_write_read/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/flash/flash_write_read/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvoptx b/project/at_start_f435/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvoptx index 87b3273c..3efbef21 100644 --- a/project/at_start_f435/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvoptx +++ b/project/at_start_f435/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvprojx b/project/at_start_f435/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvprojx index 385c53dc..b8e258e6 100644 --- a/project/at_start_f435/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvprojx +++ b/project/at_start_f435/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -479,4 +479,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/flash/flash_write_read/src/at32f435_437_clock.c b/project/at_start_f435/examples/flash/flash_write_read/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/flash/flash_write_read/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/flash/flash_write_read/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/gpio/io_toggle/inc/at32f435_437_conf.h b/project/at_start_f435/examples/gpio/io_toggle/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/gpio/io_toggle/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/gpio/io_toggle/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/gpio/io_toggle/mdk_v5/io_toggle.uvoptx b/project/at_start_f435/examples/gpio/io_toggle/mdk_v5/io_toggle.uvoptx index 44095bb4..05736774 100644 --- a/project/at_start_f435/examples/gpio/io_toggle/mdk_v5/io_toggle.uvoptx +++ b/project/at_start_f435/examples/gpio/io_toggle/mdk_v5/io_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/gpio/io_toggle/mdk_v5/io_toggle.uvprojx b/project/at_start_f435/examples/gpio/io_toggle/mdk_v5/io_toggle.uvprojx index 5b31f53d..4ea1c7a2 100644 --- a/project/at_start_f435/examples/gpio/io_toggle/mdk_v5/io_toggle.uvprojx +++ b/project/at_start_f435/examples/gpio/io_toggle/mdk_v5/io_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/gpio/io_toggle/src/at32f435_437_clock.c b/project/at_start_f435/examples/gpio/io_toggle/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/gpio/io_toggle/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/gpio/io_toggle/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/gpio/led_toggle/inc/at32f435_437_conf.h b/project/at_start_f435/examples/gpio/led_toggle/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/gpio/led_toggle/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/gpio/led_toggle/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/gpio/led_toggle/mdk_v5/led_toggle.uvoptx b/project/at_start_f435/examples/gpio/led_toggle/mdk_v5/led_toggle.uvoptx index 65947c37..006e5293 100644 --- a/project/at_start_f435/examples/gpio/led_toggle/mdk_v5/led_toggle.uvoptx +++ b/project/at_start_f435/examples/gpio/led_toggle/mdk_v5/led_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/gpio/led_toggle/mdk_v5/led_toggle.uvprojx b/project/at_start_f435/examples/gpio/led_toggle/mdk_v5/led_toggle.uvprojx index b93e262a..f04dfbd8 100644 --- a/project/at_start_f435/examples/gpio/led_toggle/mdk_v5/led_toggle.uvprojx +++ b/project/at_start_f435/examples/gpio/led_toggle/mdk_v5/led_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/gpio/led_toggle/src/at32f435_437_clock.c b/project/at_start_f435/examples/gpio/led_toggle/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/gpio/led_toggle/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/gpio/led_toggle/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/gpio/swjtag_mux/inc/at32f435_437_conf.h b/project/at_start_f435/examples/gpio/swjtag_mux/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/gpio/swjtag_mux/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/gpio/swjtag_mux/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvoptx b/project/at_start_f435/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvoptx index fda91f86..ed010a22 100644 --- a/project/at_start_f435/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvoptx +++ b/project/at_start_f435/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvprojx b/project/at_start_f435/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvprojx index 353ae181..45481f6d 100644 --- a/project/at_start_f435/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvprojx +++ b/project/at_start_f435/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/gpio/swjtag_mux/src/at32f435_437_clock.c b/project/at_start_f435/examples/gpio/swjtag_mux/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/gpio/swjtag_mux/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/gpio/swjtag_mux/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/i2c/communication_dma/inc/at32f435_437_conf.h b/project/at_start_f435/examples/i2c/communication_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/i2c/communication_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/i2c/communication_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/i2c/communication_dma/mdk_v5/communication_dma.uvoptx b/project/at_start_f435/examples/i2c/communication_dma/mdk_v5/communication_dma.uvoptx index 4a9b27a7..36adfc94 100644 --- a/project/at_start_f435/examples/i2c/communication_dma/mdk_v5/communication_dma.uvoptx +++ b/project/at_start_f435/examples/i2c/communication_dma/mdk_v5/communication_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/i2c/communication_dma/mdk_v5/communication_dma.uvprojx b/project/at_start_f435/examples/i2c/communication_dma/mdk_v5/communication_dma.uvprojx index 4b6e0603..cd769a0c 100644 --- a/project/at_start_f435/examples/i2c/communication_dma/mdk_v5/communication_dma.uvprojx +++ b/project/at_start_f435/examples/i2c/communication_dma/mdk_v5/communication_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -489,4 +489,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/i2c/communication_dma/src/at32f435_437_clock.c b/project/at_start_f435/examples/i2c/communication_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/i2c/communication_dma/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/i2c/communication_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/i2c/communication_int/inc/at32f435_437_conf.h b/project/at_start_f435/examples/i2c/communication_int/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/i2c/communication_int/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/i2c/communication_int/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/i2c/communication_int/mdk_v5/communication_int.uvoptx b/project/at_start_f435/examples/i2c/communication_int/mdk_v5/communication_int.uvoptx index dc343d57..46434ff8 100644 --- a/project/at_start_f435/examples/i2c/communication_int/mdk_v5/communication_int.uvoptx +++ b/project/at_start_f435/examples/i2c/communication_int/mdk_v5/communication_int.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/i2c/communication_int/mdk_v5/communication_int.uvprojx b/project/at_start_f435/examples/i2c/communication_int/mdk_v5/communication_int.uvprojx index 5002af0a..2b6d16bb 100644 --- a/project/at_start_f435/examples/i2c/communication_int/mdk_v5/communication_int.uvprojx +++ b/project/at_start_f435/examples/i2c/communication_int/mdk_v5/communication_int.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -489,4 +489,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/i2c/communication_int/src/at32f435_437_clock.c b/project/at_start_f435/examples/i2c/communication_int/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/i2c/communication_int/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/i2c/communication_int/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/i2c/communication_poll/inc/at32f435_437_conf.h b/project/at_start_f435/examples/i2c/communication_poll/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/i2c/communication_poll/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/i2c/communication_poll/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/i2c/communication_poll/mdk_v5/communication_poll.uvoptx b/project/at_start_f435/examples/i2c/communication_poll/mdk_v5/communication_poll.uvoptx index 557f1101..529b10d0 100644 --- a/project/at_start_f435/examples/i2c/communication_poll/mdk_v5/communication_poll.uvoptx +++ b/project/at_start_f435/examples/i2c/communication_poll/mdk_v5/communication_poll.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/i2c/communication_poll/mdk_v5/communication_poll.uvprojx b/project/at_start_f435/examples/i2c/communication_poll/mdk_v5/communication_poll.uvprojx index 837bce48..43edf452 100644 --- a/project/at_start_f435/examples/i2c/communication_poll/mdk_v5/communication_poll.uvprojx +++ b/project/at_start_f435/examples/i2c/communication_poll/mdk_v5/communication_poll.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -489,4 +489,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/i2c/communication_poll/src/at32f435_437_clock.c b/project/at_start_f435/examples/i2c/communication_poll/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/i2c/communication_poll/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/i2c/communication_poll/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/i2c/communication_smbus/inc/at32f435_437_conf.h b/project/at_start_f435/examples/i2c/communication_smbus/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/i2c/communication_smbus/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/i2c/communication_smbus/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvoptx b/project/at_start_f435/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvoptx index 3b69beae..471f06ac 100644 --- a/project/at_start_f435/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvoptx +++ b/project/at_start_f435/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvprojx b/project/at_start_f435/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvprojx index 9707e27e..3f1a9c7a 100644 --- a/project/at_start_f435/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvprojx +++ b/project/at_start_f435/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -489,4 +489,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/i2c/communication_smbus/src/at32f435_437_clock.c b/project/at_start_f435/examples/i2c/communication_smbus/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/i2c/communication_smbus/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/i2c/communication_smbus/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/i2c/eeprom/inc/at32f435_437_conf.h b/project/at_start_f435/examples/i2c/eeprom/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/i2c/eeprom/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/i2c/eeprom/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/i2c/eeprom/mdk_v5/eeprom.uvoptx b/project/at_start_f435/examples/i2c/eeprom/mdk_v5/eeprom.uvoptx index 02a4eab5..1638a4eb 100644 --- a/project/at_start_f435/examples/i2c/eeprom/mdk_v5/eeprom.uvoptx +++ b/project/at_start_f435/examples/i2c/eeprom/mdk_v5/eeprom.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/i2c/eeprom/mdk_v5/eeprom.uvprojx b/project/at_start_f435/examples/i2c/eeprom/mdk_v5/eeprom.uvprojx index 18c70ad8..8a22adb3 100644 --- a/project/at_start_f435/examples/i2c/eeprom/mdk_v5/eeprom.uvprojx +++ b/project/at_start_f435/examples/i2c/eeprom/mdk_v5/eeprom.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -489,4 +489,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/i2c/eeprom/src/at32f435_437_clock.c b/project/at_start_f435/examples/i2c/eeprom/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/i2c/eeprom/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/i2c/eeprom/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/i2s/fullduplex_dma/inc/at32f435_437_conf.h b/project/at_start_f435/examples/i2s/fullduplex_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/i2s/fullduplex_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/i2s/fullduplex_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvoptx b/project/at_start_f435/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvoptx index 59bcc57b..a0cd61dc 100644 --- a/project/at_start_f435/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvoptx +++ b/project/at_start_f435/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvprojx b/project/at_start_f435/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvprojx index ce06d8ed..4cc53c77 100644 --- a/project/at_start_f435/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvprojx +++ b/project/at_start_f435/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/i2s/fullduplex_dma/src/at32f435_437_clock.c b/project/at_start_f435/examples/i2s/fullduplex_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/i2s/fullduplex_dma/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/i2s/fullduplex_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/i2s/halfduplex_dma/inc/at32f435_437_conf.h b/project/at_start_f435/examples/i2s/halfduplex_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/i2s/halfduplex_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/i2s/halfduplex_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvoptx b/project/at_start_f435/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvoptx index 62cf4991..bc08f13f 100644 --- a/project/at_start_f435/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvoptx +++ b/project/at_start_f435/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvprojx b/project/at_start_f435/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvprojx index 593f3cbc..18c57d17 100644 --- a/project/at_start_f435/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvprojx +++ b/project/at_start_f435/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/i2s/halfduplex_dma/src/at32f435_437_clock.c b/project/at_start_f435/examples/i2s/halfduplex_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/i2s/halfduplex_dma/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/i2s/halfduplex_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/i2s/halfduplex_interrupt/inc/at32f435_437_conf.h b/project/at_start_f435/examples/i2s/halfduplex_interrupt/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/i2s/halfduplex_interrupt/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/i2s/halfduplex_interrupt/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx b/project/at_start_f435/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx index e728da4a..d3933b74 100644 --- a/project/at_start_f435/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx +++ b/project/at_start_f435/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx b/project/at_start_f435/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx index 50347371..eaf94d42 100644 --- a/project/at_start_f435/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx +++ b/project/at_start_f435/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/i2s/halfduplex_interrupt/src/at32f435_437_clock.c b/project/at_start_f435/examples/i2s/halfduplex_interrupt/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/i2s/halfduplex_interrupt/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/i2s/halfduplex_interrupt/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/inc/at32f435_437_conf.h b/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvoptx b/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvoptx index c51abdc3..f364ba2e 100644 --- a/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvoptx +++ b/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvprojx b/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvprojx index 59ac159a..9e4f3cc1 100644 --- a/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvprojx +++ b/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f435_437_clock.c b/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/irtmr/irtmr_output/inc/at32f435_437_conf.h b/project/at_start_f435/examples/irtmr/irtmr_output/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/irtmr/irtmr_output/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/irtmr/irtmr_output/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvoptx b/project/at_start_f435/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvoptx index 38ebf8c4..d5b7dc21 100644 --- a/project/at_start_f435/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvoptx +++ b/project/at_start_f435/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvprojx b/project/at_start_f435/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvprojx index 35d6adac..d40cf82b 100644 --- a/project/at_start_f435/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvprojx +++ b/project/at_start_f435/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/irtmr/irtmr_output/src/at32f435_437_clock.c b/project/at_start_f435/examples/irtmr/irtmr_output/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/irtmr/irtmr_output/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/irtmr/irtmr_output/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/inc/at32f435_437_conf.h b/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvoptx b/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvoptx index b4bd027d..e0d03d5b 100644 --- a/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvoptx +++ b/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvprojx b/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvprojx index 6bf9da84..c1e9eb26 100644 --- a/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvprojx +++ b/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/src/at32f435_437_clock.c b/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/pwc/deepsleep_ertc_alarm/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/inc/at32f435_437_conf.h b/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvoptx b/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvoptx index 2e28b32e..458fc5d1 100644 --- a/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvoptx +++ b/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvprojx b/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvprojx index 44108eeb..70eb31c5 100644 --- a/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvprojx +++ b/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/src/at32f435_437_clock.c b/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/pwc/deepsleep_ertc_tamper/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/inc/at32f435_437_conf.h b/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvoptx b/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvoptx index 2ef7e01e..f50eeaff 100644 --- a/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvoptx +++ b/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvprojx b/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvprojx index 6760304c..e6b9336f 100644 --- a/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvprojx +++ b/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/src/at32f435_437_clock.c b/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/pwc/deepsleep_ertc_wakeup/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/pwc/ldo_set/inc/at32f435_437_conf.h b/project/at_start_f435/examples/pwc/ldo_set/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/pwc/ldo_set/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/pwc/ldo_set/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/pwc/ldo_set/mdk_v5/ldo_set.uvoptx b/project/at_start_f435/examples/pwc/ldo_set/mdk_v5/ldo_set.uvoptx index cc77485a..ca0683e5 100644 --- a/project/at_start_f435/examples/pwc/ldo_set/mdk_v5/ldo_set.uvoptx +++ b/project/at_start_f435/examples/pwc/ldo_set/mdk_v5/ldo_set.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/pwc/ldo_set/mdk_v5/ldo_set.uvprojx b/project/at_start_f435/examples/pwc/ldo_set/mdk_v5/ldo_set.uvprojx index f62d0ef2..df81a2ae 100644 --- a/project/at_start_f435/examples/pwc/ldo_set/mdk_v5/ldo_set.uvprojx +++ b/project/at_start_f435/examples/pwc/ldo_set/mdk_v5/ldo_set.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/pwc/ldo_set/src/at32f435_437_clock.c b/project/at_start_f435/examples/pwc/ldo_set/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/pwc/ldo_set/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/pwc/ldo_set/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/pwc/power_voltage_monitor/inc/at32f435_437_conf.h b/project/at_start_f435/examples/pwc/power_voltage_monitor/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/pwc/power_voltage_monitor/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/pwc/power_voltage_monitor/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvoptx b/project/at_start_f435/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvoptx index b65c174b..42a576b3 100644 --- a/project/at_start_f435/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvoptx +++ b/project/at_start_f435/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvprojx b/project/at_start_f435/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvprojx index f98a84da..56985149 100644 --- a/project/at_start_f435/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvprojx +++ b/project/at_start_f435/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/pwc/power_voltage_monitor/src/at32f435_437_clock.c b/project/at_start_f435/examples/pwc/power_voltage_monitor/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/pwc/power_voltage_monitor/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/pwc/power_voltage_monitor/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/pwc/sleep_tmr2/inc/at32f435_437_conf.h b/project/at_start_f435/examples/pwc/sleep_tmr2/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/pwc/sleep_tmr2/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/pwc/sleep_tmr2/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvoptx b/project/at_start_f435/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvoptx index 45b366b6..dea815ad 100644 --- a/project/at_start_f435/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvoptx +++ b/project/at_start_f435/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvprojx b/project/at_start_f435/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvprojx index 70dec9e4..ddda94ef 100644 --- a/project/at_start_f435/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvprojx +++ b/project/at_start_f435/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/pwc/sleep_tmr2/src/at32f435_437_clock.c b/project/at_start_f435/examples/pwc/sleep_tmr2/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/pwc/sleep_tmr2/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/pwc/sleep_tmr2/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/pwc/sleep_usart1/inc/at32f435_437_conf.h b/project/at_start_f435/examples/pwc/sleep_usart1/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/pwc/sleep_usart1/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/pwc/sleep_usart1/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvoptx b/project/at_start_f435/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvoptx index f7f166b3..8e11ad8b 100644 --- a/project/at_start_f435/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvoptx +++ b/project/at_start_f435/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvprojx b/project/at_start_f435/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvprojx index af70fd35..15f6e1c9 100644 --- a/project/at_start_f435/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvprojx +++ b/project/at_start_f435/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/pwc/sleep_usart1/src/at32f435_437_clock.c b/project/at_start_f435/examples/pwc/sleep_usart1/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/pwc/sleep_usart1/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/pwc/sleep_usart1/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/pwc/standby_ertc_alarm/inc/at32f435_437_conf.h b/project/at_start_f435/examples/pwc/standby_ertc_alarm/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/pwc/standby_ertc_alarm/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/pwc/standby_ertc_alarm/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvoptx b/project/at_start_f435/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvoptx index bddfba5f..96ce3395 100644 --- a/project/at_start_f435/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvoptx +++ b/project/at_start_f435/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvprojx b/project/at_start_f435/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvprojx index bb19250d..7614ce4e 100644 --- a/project/at_start_f435/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvprojx +++ b/project/at_start_f435/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/pwc/standby_ertc_alarm/src/at32f435_437_clock.c b/project/at_start_f435/examples/pwc/standby_ertc_alarm/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/pwc/standby_ertc_alarm/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/pwc/standby_ertc_alarm/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/pwc/standby_wakeup_pin/inc/at32f435_437_conf.h b/project/at_start_f435/examples/pwc/standby_wakeup_pin/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/pwc/standby_wakeup_pin/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/pwc/standby_wakeup_pin/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvoptx b/project/at_start_f435/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvoptx index 2559a585..d0c5fdc7 100644 --- a/project/at_start_f435/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvoptx +++ b/project/at_start_f435/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvprojx b/project/at_start_f435/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvprojx index 88c32bef..35d0a42c 100644 --- a/project/at_start_f435/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvprojx +++ b/project/at_start_f435/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvprojx @@ -10,13 +10,13 @@ standby_wakeup_pin 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC + 5060750::V5.06 update 6 (build 750)::.\ARMCC 0 -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/pwc/standby_wakeup_pin/src/at32f435_437_clock.c b/project/at_start_f435/examples/pwc/standby_wakeup_pin/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/pwc/standby_wakeup_pin/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/pwc/standby_wakeup_pin/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/pwc/standby_wakeup_pin/src/main.c b/project/at_start_f435/examples/pwc/standby_wakeup_pin/src/main.c index b9450f05..8f0598d7 100644 --- a/project/at_start_f435/examples/pwc/standby_wakeup_pin/src/main.c +++ b/project/at_start_f435/examples/pwc/standby_wakeup_pin/src/main.c @@ -74,6 +74,8 @@ int main(void) } at32_led_on(LED4); + + /*delay to check led status*/ delay_ms(1000); /* enable wakeup pin1(pa0), pin2(pc13) */ diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma/inc/at32f435_437_conf.h b/project/at_start_f435/examples/qspi/command_port_using_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/qspi/command_port_using_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvoptx b/project/at_start_f435/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvoptx index 71a14ca5..4f4b9ac5 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvoptx +++ b/project/at_start_f435/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvprojx b/project/at_start_f435/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvprojx index 24f88dc4..75d16590 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvprojx +++ b/project/at_start_f435/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma/src/at32f435_437_clock.c b/project/at_start_f435/examples/qspi/command_port_using_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/qspi/command_port_using_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma/src/qspi_cmd_esmt32m.c b/project/at_start_f435/examples/qspi/command_port_using_dma/src/qspi_cmd_esmt32m.c index 38c7e625..38020e31 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma/src/qspi_cmd_esmt32m.c +++ b/project/at_start_f435/examples/qspi/command_port_using_dma/src/qspi_cmd_esmt32m.c @@ -255,15 +255,10 @@ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { uint32_t blk_sz; do - { /* send up to 256 bytes at one time */ - if(total_len > FLASH_PAGE_PROGRAM_SIZE) - { - blk_sz = FLASH_PAGE_PROGRAM_SIZE; - } - else - { + { /* send up to 256 bytes at one time, and only one page */ + blk_sz = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < blk_sz) blk_sz = total_len; - } qspi_data_once_write(addr, blk_sz, buf); addr += blk_sz; buf += blk_sz; diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/inc/at32f435_437_conf.h b/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvoptx b/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvoptx index 0812e07d..1f680dd2 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvoptx +++ b/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvprojx b/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvprojx index 445d38f9..e0799275 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvprojx +++ b/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/src/at32f435_437_clock.c b/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/src/qspi_cmd_esmt32m.c b/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/src/qspi_cmd_esmt32m.c index 9b19d717..64ec086e 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/src/qspi_cmd_esmt32m.c +++ b/project/at_start_f435/examples/qspi/command_port_using_dma_and_pem/src/qspi_cmd_esmt32m.c @@ -347,15 +347,10 @@ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { uint32_t blk_sz; do - { /* send up to 256 bytes at one time */ - if(total_len > FLASH_PAGE_PROGRAM_SIZE) - { - blk_sz = FLASH_PAGE_PROGRAM_SIZE; - } - else - { + { /* send up to 256 bytes at one time, and only one page */ + blk_sz = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < blk_sz) blk_sz = total_len; - } qspi_data_once_write(addr, blk_sz, buf); addr += blk_sz; buf += blk_sz; diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/inc/at32f435_437_conf.h b/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvoptx b/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvoptx index 8ea6cd31..36612096 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvoptx +++ b/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvprojx b/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvprojx index 085388b7..a7c83c44 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvprojx +++ b/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/src/at32f435_437_clock.c b/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/src/qspi_cmd_esmt32m.c b/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/src/qspi_cmd_esmt32m.c index 30b71fcf..c322e685 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/src/qspi_cmd_esmt32m.c +++ b/project/at_start_f435/examples/qspi/command_port_using_dma_qpi_mode/src/qspi_cmd_esmt32m.c @@ -255,15 +255,10 @@ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { uint32_t blk_sz; do - { /* send up to 256 bytes at one time */ - if(total_len > FLASH_PAGE_PROGRAM_SIZE) - { - blk_sz = FLASH_PAGE_PROGRAM_SIZE; - } - else - { + { /* send up to 256 bytes at one time, and only one page */ + blk_sz = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < blk_sz) blk_sz = total_len; - } qspi_data_once_write(addr, blk_sz, buf); addr += blk_sz; buf += blk_sz; diff --git a/project/at_start_f435/examples/qspi/command_port_using_interrupt/inc/at32f435_437_conf.h b/project/at_start_f435/examples/qspi/command_port_using_interrupt/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_interrupt/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/qspi/command_port_using_interrupt/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvoptx b/project/at_start_f435/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvoptx index d530d1a9..f0864563 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvoptx +++ b/project/at_start_f435/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvprojx b/project/at_start_f435/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvprojx index 7bfcd1cd..586aa286 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvprojx +++ b/project/at_start_f435/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -479,4 +479,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/qspi/command_port_using_interrupt/src/at32f435_437_clock.c b/project/at_start_f435/examples/qspi/command_port_using_interrupt/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_interrupt/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/qspi/command_port_using_interrupt/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/qspi/command_port_using_interrupt/src/qspi_cmd_esmt32m.c b/project/at_start_f435/examples/qspi/command_port_using_interrupt/src/qspi_cmd_esmt32m.c index 83c83b9b..aee6abe4 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_interrupt/src/qspi_cmd_esmt32m.c +++ b/project/at_start_f435/examples/qspi/command_port_using_interrupt/src/qspi_cmd_esmt32m.c @@ -244,19 +244,16 @@ void qspi_data_read(uint32_t addr, uint32_t total_len, uint8_t* buf) */ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { - uint32_t i, len = total_len; + uint32_t i, len; do { qspi_write_enable(); - if(total_len >= FLASH_PAGE_PROGRAM_SIZE) - { - len = FLASH_PAGE_PROGRAM_SIZE; - } - else - { + /* send up to 256 bytes at one time, and only one page */ + len = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < len) len = total_len; - } + /* set busy state */ qspi_command_set_busy(); diff --git a/project/at_start_f435/examples/qspi/command_port_using_polling/inc/at32f435_437_conf.h b/project/at_start_f435/examples/qspi/command_port_using_polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_polling/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/qspi/command_port_using_polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvoptx b/project/at_start_f435/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvoptx index 8e0bd7bd..b4e72e5a 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvoptx +++ b/project/at_start_f435/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvprojx b/project/at_start_f435/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvprojx index 16a8f774..b19545fd 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvprojx +++ b/project/at_start_f435/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x400000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -479,4 +479,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/qspi/command_port_using_polling/src/at32f435_437_clock.c b/project/at_start_f435/examples/qspi/command_port_using_polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_polling/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/qspi/command_port_using_polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/qspi/command_port_using_polling/src/qspi_cmd_esmt32m.c b/project/at_start_f435/examples/qspi/command_port_using_polling/src/qspi_cmd_esmt32m.c index 60075c52..d13deeb1 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_polling/src/qspi_cmd_esmt32m.c +++ b/project/at_start_f435/examples/qspi/command_port_using_polling/src/qspi_cmd_esmt32m.c @@ -197,19 +197,16 @@ void qspi_data_read(uint32_t addr, uint32_t total_len, uint8_t* buf) */ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { - uint32_t i, len = total_len; + uint32_t i, len; do { qspi_write_enable(); - if(total_len >= FLASH_PAGE_PROGRAM_SIZE) - { - len = FLASH_PAGE_PROGRAM_SIZE; - } - else - { + /* send up to 256 bytes at one time, and only one page */ + len = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < len) len = total_len; - } + esmt32m_cmd_write_config(&esmt32m_cmd_config, addr, len); qspi_cmd_operation_kick(QSPI1, &esmt32m_cmd_config); diff --git a/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/inc/at32f435_437_conf.h b/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvoptx b/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvoptx index 6be1a4df..343f1815 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvoptx +++ b/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvprojx b/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvprojx index 5bb010ee..fa2f890a 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvprojx +++ b/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -479,4 +479,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/src/at32f435_437_clock.c b/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/src/qspi_cmd_esmt32m.c b/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/src/qspi_cmd_esmt32m.c index 7ff82f68..5a32c37d 100644 --- a/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/src/qspi_cmd_esmt32m.c +++ b/project/at_start_f435/examples/qspi/command_port_using_rdsr_sw/src/qspi_cmd_esmt32m.c @@ -197,19 +197,16 @@ void qspi_data_read(uint32_t addr, uint32_t total_len, uint8_t* buf) */ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { - uint32_t i, len = total_len; + uint32_t i, len; do { qspi_write_enable(); - if(total_len >= FLASH_PAGE_PROGRAM_SIZE) - { - len = FLASH_PAGE_PROGRAM_SIZE; - } - else - { + /* send up to 256 bytes at one time, and only one page */ + len = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < len) len = total_len; - } + esmt32m_cmd_write_config(&esmt32m_cmd_config, addr, len); qspi_cmd_operation_kick(QSPI1, &esmt32m_cmd_config); diff --git a/project/at_start_f435/examples/qspi/xip_port_read_flash/inc/at32f435_437_conf.h b/project/at_start_f435/examples/qspi/xip_port_read_flash/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/qspi/xip_port_read_flash/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/qspi/xip_port_read_flash/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvoptx b/project/at_start_f435/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvoptx index 1c504707..623cfa9a 100644 --- a/project/at_start_f435/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvoptx +++ b/project/at_start_f435/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 @@ -282,18 +282,6 @@ 0 0 0 - ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_dma.c - at32f435_437_dma.c - 0 - 0 - - - 3 - 9 - 1 - 0 - 0 - 0 ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_qspi.c at32f435_437_qspi.c 0 @@ -301,7 +289,7 @@ 3 - 10 + 9 1 0 0 @@ -313,7 +301,7 @@ 3 - 11 + 10 1 0 0 @@ -333,7 +321,7 @@ 0 4 - 12 + 11 1 0 0 @@ -345,7 +333,7 @@ 4 - 13 + 12 2 0 0 @@ -365,7 +353,7 @@ 0 5 - 14 + 13 5 0 0 diff --git a/project/at_start_f435/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvprojx b/project/at_start_f435/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvprojx index 9681055c..f6fbfeb3 100644 --- a/project/at_start_f435/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvprojx +++ b/project/at_start_f435/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -427,11 +427,6 @@ 1 ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_misc.c - - at32f435_437_dma.c - 1 - ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_dma.c - at32f435_437_qspi.c 1 @@ -488,6 +483,12 @@ xip_port_read_flash + + + + + + 0 1 diff --git a/project/at_start_f435/examples/qspi/xip_port_read_flash/src/at32f435_437_clock.c b/project/at_start_f435/examples/qspi/xip_port_read_flash/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/qspi/xip_port_read_flash/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/qspi/xip_port_read_flash/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/qspi/xip_port_read_flash/src/main.c b/project/at_start_f435/examples/qspi/xip_port_read_flash/src/main.c index fac3a75b..d3183050 100644 --- a/project/at_start_f435/examples/qspi/xip_port_read_flash/src/main.c +++ b/project/at_start_f435/examples/qspi/xip_port_read_flash/src/main.c @@ -34,7 +34,6 @@ * @{ */ -extern void qspi_data_read(uint32_t addr, uint32_t total_len, uint8_t* buf); extern void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf); extern void qspi_erase(uint32_t sec_addr); extern void en25qh128a_qspi_xip_init(void); @@ -59,8 +58,6 @@ ALIGNED_HEAD uint8_t rbuf[TEST_SIZE] ALIGNED_TAIL; void qspi_config(void) { gpio_init_type gpio_init_struct; - /* enable the dma clock */ - crm_periph_clock_enable(CRM_DMA2_PERIPH_CLOCK, TRUE); /* enable the qspi clock */ crm_periph_clock_enable(CRM_QSPI1_PERIPH_CLOCK, TRUE); @@ -142,18 +139,6 @@ int main(void) /* erase */ qspi_erase(0); - /* read */ - qspi_data_read(0, TEST_SIZE, rbuf); - - for(i = 0; i < TEST_SIZE; i++) - { - if(rbuf[i] != 0xFF) - { - err = 1; - break; - } - } - /* program */ qspi_data_write(0, TEST_SIZE, wbuf); diff --git a/project/at_start_f435/examples/qspi/xip_port_read_flash/src/qspi_cmd_en25qh128a.c b/project/at_start_f435/examples/qspi/xip_port_read_flash/src/qspi_cmd_en25qh128a.c index 71619e3a..8f11ca1d 100644 --- a/project/at_start_f435/examples/qspi/xip_port_read_flash/src/qspi_cmd_en25qh128a.c +++ b/project/at_start_f435/examples/qspi/xip_port_read_flash/src/qspi_cmd_en25qh128a.c @@ -40,29 +40,6 @@ qspi_xip_type en25qh128a_xip_init; void qspi_busy_check(void); void qspi_write_enable(void); -/** - * @brief en25qh128a cmd read config - * @param qspi_cmd_struct: the pointer for qspi_cmd_type parameter - * @param addr: read start address - * @param counter: read data counter - * @retval none - */ -void en25qh128a_cmd_read_config(qspi_cmd_type *qspi_cmd_struct, uint32_t addr, uint32_t counter) -{ - qspi_cmd_struct->pe_mode_enable = FALSE; - qspi_cmd_struct->pe_mode_operate_code = 0; - qspi_cmd_struct->instruction_code = 0xEB; - qspi_cmd_struct->instruction_length = QSPI_CMD_INSLEN_1_BYTE; - qspi_cmd_struct->address_code = addr; - qspi_cmd_struct->address_length = QSPI_CMD_ADRLEN_3_BYTE; - qspi_cmd_struct->data_counter = counter; - qspi_cmd_struct->second_dummy_cycle_num = 6; - qspi_cmd_struct->operation_mode = QSPI_OPERATE_MODE_144; - qspi_cmd_struct->read_status_config = QSPI_RSTSC_HW_AUTO; - qspi_cmd_struct->read_status_enable = FALSE; - qspi_cmd_struct->write_data_enable = FALSE; -} - /** * @brief en25qh128a cmd write config * @param qspi_cmd_struct: the pointer for qspi_cmd_type parameter @@ -150,102 +127,6 @@ void en25qh128a_cmd_rdsr_config(qspi_cmd_type *qspi_cmd_struct) qspi_cmd_struct->write_data_enable = FALSE; } -/** - * @brief qspi dma set - * @param dir: dma transfer direction - * @param buf: the pointer for dma data - * @param length: data length - * @retval none - */ -void qspi_dma_set(dma_dir_type dir, uint8_t* buf, uint32_t length) -{ - dma_init_type dma_init_struct; - dma_reset(DMA2_CHANNEL1); - dma_default_para_init(&dma_init_struct); - dma_init_struct.buffer_size = length / 4; /* using word unit */ - dma_init_struct.loop_mode_enable = FALSE; - dma_init_struct.direction = dir; - dma_init_struct.memory_base_addr = (uint32_t)buf; - dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_WORD; - dma_init_struct.memory_inc_enable = TRUE; - dma_init_struct.peripheral_base_addr = (uint32_t)(&(QSPI1->dt)); - dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_WORD; - dma_init_struct.peripheral_inc_enable = FALSE; - dma_init_struct.priority = DMA_PRIORITY_HIGH; - - dma_init(DMA2_CHANNEL1, &dma_init_struct); - - dmamux_init(DMA2MUX_CHANNEL1, DMAMUX_DMAREQ_ID_QSPI1); - dmamux_enable(DMA2, TRUE); - - dma_channel_enable(DMA2_CHANNEL1, TRUE); -} - -/** - * @brief qspi read data - * @param addr: the address for read - * @param total_len: the length for read - * @param buf: the pointer for read data - * @retval none - */ -void qspi_data_read(uint32_t addr, uint32_t total_len, uint8_t* buf) -{ - /* config qspi's dma mode */ - qspi_dma_enable(QSPI1, TRUE); - qspi_dma_rx_threshold_set(QSPI1, QSPI_DMA_FIFO_THOD_WORD08); - - /* config and enable dma */ - qspi_dma_set(DMA_DIR_PERIPHERAL_TO_MEMORY, buf, total_len); - - /* kick command */ - en25qh128a_cmd_read_config(&en25qh128a_cmd_config, addr, total_len); - qspi_cmd_operation_kick(QSPI1, &en25qh128a_cmd_config); - - /* wait command completed */ - while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET); - qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG); - - /* wait dma completed */ - while(dma_flag_get(DMA2_FDT1_FLAG) == RESET); - dma_flag_clear(DMA2_FDT1_FLAG); - qspi_dma_enable(QSPI1, FALSE); -} - -/** - * @brief qspi write data for one time - * @param addr: the address for write - * @param sz: the length for write - * @param buf: the pointer for write data - * @retval none - */ -static void qspi_data_once_write(uint32_t addr, uint32_t sz, uint8_t* buf) -{ - qspi_write_enable(); - - /* config qspi's dma mode */ - qspi_dma_enable(QSPI1, TRUE); - qspi_dma_tx_threshold_set(QSPI1, QSPI_DMA_FIFO_THOD_WORD08); - - /* config and enable dma */ - qspi_dma_set(DMA_DIR_MEMORY_TO_PERIPHERAL, buf, sz); - - /* kick command */ - en25qh128a_cmd_write_config(&en25qh128a_cmd_config, addr, sz); - qspi_cmd_operation_kick(QSPI1, &en25qh128a_cmd_config); - - - /* wait command completed */ - while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET); - qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG); - - /* wait dma completed */ - while(dma_flag_get(DMA2_FDT1_FLAG) == RESET); - dma_flag_clear(DMA2_FDT1_FLAG); - qspi_dma_enable(QSPI1, FALSE); - - qspi_busy_check(); -} - /** * @brief qspi write data * @param addr: the address for write @@ -255,22 +136,33 @@ static void qspi_data_once_write(uint32_t addr, uint32_t sz, uint8_t* buf) */ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { - uint32_t blk_sz; - do - { /* send up to 256 bytes at one time */ - if(total_len > FLASH_PAGE_PROGRAM_SIZE) - { - blk_sz = FLASH_PAGE_PROGRAM_SIZE; - } - else - { - blk_sz = total_len; - } - qspi_data_once_write(addr, blk_sz, buf); - addr += blk_sz; - buf += blk_sz; - total_len -= blk_sz; - }while(total_len > 0); + uint32_t i, len; + do + { + qspi_write_enable(); + /* send up to 256 bytes at one time, and only one page */ + len = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < len) + len = total_len; + + en25qh128a_cmd_write_config(&en25qh128a_cmd_config, addr, len); + qspi_cmd_operation_kick(QSPI1, &en25qh128a_cmd_config); + + for(i = 0; i < len; ++i) + { + while(qspi_flag_get(QSPI1, QSPI_TXFIFORDY_FLAG) == RESET); + qspi_byte_write(QSPI1, *buf++); + } + total_len -= len; + addr += len; + + /* wait command completed */ + while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET); + qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG); + + qspi_busy_check(); + + }while(total_len); } /** diff --git a/project/at_start_f435/examples/qspi/xip_port_read_write_sram/inc/at32f435_437_conf.h b/project/at_start_f435/examples/qspi/xip_port_read_write_sram/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/qspi/xip_port_read_write_sram/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/qspi/xip_port_read_write_sram/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvoptx b/project/at_start_f435/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvoptx index c7fe741b..63e11a9f 100644 --- a/project/at_start_f435/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvoptx +++ b/project/at_start_f435/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvprojx b/project/at_start_f435/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvprojx index a301fd14..08aa5323 100644 --- a/project/at_start_f435/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvprojx +++ b/project/at_start_f435/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,12 @@ xip_port_read_write_sram + + + + + + 0 1 diff --git a/project/at_start_f435/examples/qspi/xip_port_read_write_sram/src/at32f435_437_clock.c b/project/at_start_f435/examples/qspi/xip_port_read_write_sram/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/qspi/xip_port_read_write_sram/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/qspi/xip_port_read_write_sram/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/scfg/mem_map_sel/inc/at32f435_437_conf.h b/project/at_start_f435/examples/scfg/mem_map_sel/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/scfg/mem_map_sel/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/scfg/mem_map_sel/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvoptx b/project/at_start_f435/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvoptx index 7ff73399..e60f406e 100644 --- a/project/at_start_f435/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvoptx +++ b/project/at_start_f435/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvprojx b/project/at_start_f435/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvprojx index 42044095..d683165d 100644 --- a/project/at_start_f435/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvprojx +++ b/project/at_start_f435/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/scfg/mem_map_sel/src/at32f435_437_clock.c b/project/at_start_f435/examples/scfg/mem_map_sel/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/scfg/mem_map_sel/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/scfg/mem_map_sel/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/sdio/sd_mmc_card/inc/at32f435_437_conf.h b/project/at_start_f435/examples/sdio/sd_mmc_card/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/sdio/sd_mmc_card/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/sdio/sd_mmc_card/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvoptx b/project/at_start_f435/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvoptx index e000d295..5b917e5e 100644 --- a/project/at_start_f435/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvoptx +++ b/project/at_start_f435/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvprojx b/project/at_start_f435/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvprojx index e17d45dd..d0bf660c 100644 --- a/project/at_start_f435/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvprojx +++ b/project/at_start_f435/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/sdio/sd_mmc_card/src/at32f435_437_clock.c b/project/at_start_f435/examples/sdio/sd_mmc_card/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/sdio/sd_mmc_card/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/sdio/sd_mmc_card/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/sdio/sdio_fatfs/inc/at32f435_437_conf.h b/project/at_start_f435/examples/sdio/sdio_fatfs/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/sdio/sdio_fatfs/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/sdio/sdio_fatfs/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvoptx b/project/at_start_f435/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvoptx index 2f7a1e1a..01ba4f75 100644 --- a/project/at_start_f435/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvoptx +++ b/project/at_start_f435/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvprojx b/project/at_start_f435/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvprojx index 14720dc0..ebd13fbe 100644 --- a/project/at_start_f435/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvprojx +++ b/project/at_start_f435/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -620,6 +620,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/sdio/sdio_fatfs/src/at32f435_437_clock.c b/project/at_start_f435/examples/sdio/sdio_fatfs/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/sdio/sdio_fatfs/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/sdio/sdio_fatfs/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/sdio/sdio_fatfs/src/diskio.c b/project/at_start_f435/examples/sdio/sdio_fatfs/src/diskio.c index 6edee5d2..f8f0e5f3 100644 --- a/project/at_start_f435/examples/sdio/sdio_fatfs/src/diskio.c +++ b/project/at_start_f435/examples/sdio/sdio_fatfs/src/diskio.c @@ -19,7 +19,10 @@ #define DEV_MMC 1 /* Example: Map MMC/SD card to physical drive 1 */ #define DEV_USB 2 /* Example: Map USB MSD to physical drive 2 */ -uint8_t sdio_data_buffer[512]; /* buf for sd_read_disk/sd_write_disk function used. */ +#if defined ( __ICCARM__ ) /* iar compiler */ + #pragma data_alignment=4 +#endif +ALIGNED_HEAD uint8_t sdio_data_buffer[512] ALIGNED_TAIL; /* buf for sd_read_disk/sd_write_disk function used. */ sd_error_status_type sd_read_disk(uint8_t *buf, uint32_t sector, uint8_t cnt); sd_error_status_type sd_write_disk(const uint8_t *buf, uint32_t sector, uint8_t cnt); diff --git a/project/at_start_f435/examples/spi/crc_transfer_polling/inc/at32f435_437_conf.h b/project/at_start_f435/examples/spi/crc_transfer_polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/spi/crc_transfer_polling/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/spi/crc_transfer_polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvoptx b/project/at_start_f435/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvoptx index 993e4ecc..612a6aae 100644 --- a/project/at_start_f435/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvoptx +++ b/project/at_start_f435/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvprojx b/project/at_start_f435/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvprojx index 3b9441e6..14b8a845 100644 --- a/project/at_start_f435/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvprojx +++ b/project/at_start_f435/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/spi/crc_transfer_polling/src/at32f435_437_clock.c b/project/at_start_f435/examples/spi/crc_transfer_polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/spi/crc_transfer_polling/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/spi/crc_transfer_polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/spi/fullduplex_polling/inc/at32f435_437_conf.h b/project/at_start_f435/examples/spi/fullduplex_polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/spi/fullduplex_polling/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/spi/fullduplex_polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvoptx b/project/at_start_f435/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvoptx index 88a9dcd7..eb2103ef 100644 --- a/project/at_start_f435/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvoptx +++ b/project/at_start_f435/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvprojx b/project/at_start_f435/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvprojx index aff597a2..e58d93f3 100644 --- a/project/at_start_f435/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvprojx +++ b/project/at_start_f435/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/spi/fullduplex_polling/src/at32f435_437_clock.c b/project/at_start_f435/examples/spi/fullduplex_polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/spi/fullduplex_polling/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/spi/fullduplex_polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/spi/halfduplex_interrupt/inc/at32f435_437_conf.h b/project/at_start_f435/examples/spi/halfduplex_interrupt/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/spi/halfduplex_interrupt/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/spi/halfduplex_interrupt/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx b/project/at_start_f435/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx index e728da4a..d3933b74 100644 --- a/project/at_start_f435/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx +++ b/project/at_start_f435/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx b/project/at_start_f435/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx index 50347371..eaf94d42 100644 --- a/project/at_start_f435/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx +++ b/project/at_start_f435/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/spi/halfduplex_interrupt/src/at32f435_437_clock.c b/project/at_start_f435/examples/spi/halfduplex_interrupt/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/spi/halfduplex_interrupt/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/spi/halfduplex_interrupt/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/inc/at32f435_437_conf.h b/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvoptx b/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvoptx index ca126d6a..897697e9 100644 --- a/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvoptx +++ b/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvprojx b/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvprojx index b8953a41..5eaa3aec 100644 --- a/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvprojx +++ b/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/src/at32f435_437_clock.c b/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/spi/halfduplex_transceiver_switch/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/spi/only_receive_mode_polling/inc/at32f435_437_conf.h b/project/at_start_f435/examples/spi/only_receive_mode_polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/spi/only_receive_mode_polling/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/spi/only_receive_mode_polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvoptx b/project/at_start_f435/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvoptx index 9906b63f..b0588dd5 100644 --- a/project/at_start_f435/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvoptx +++ b/project/at_start_f435/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvprojx b/project/at_start_f435/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvprojx index c369f8c8..2f39387f 100644 --- a/project/at_start_f435/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvprojx +++ b/project/at_start_f435/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/spi/only_receive_mode_polling/src/at32f435_437_clock.c b/project/at_start_f435/examples/spi/only_receive_mode_polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/spi/only_receive_mode_polling/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/spi/only_receive_mode_polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/spi/ti_fullduplex_dma/inc/at32f435_437_conf.h b/project/at_start_f435/examples/spi/ti_fullduplex_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/spi/ti_fullduplex_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/spi/ti_fullduplex_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvoptx b/project/at_start_f435/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvoptx index f283477e..94e862e0 100644 --- a/project/at_start_f435/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvoptx +++ b/project/at_start_f435/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvprojx b/project/at_start_f435/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvprojx index eef07356..daa19fcd 100644 --- a/project/at_start_f435/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvprojx +++ b/project/at_start_f435/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/spi/ti_fullduplex_dma/src/at32f435_437_clock.c b/project/at_start_f435/examples/spi/ti_fullduplex_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/spi/ti_fullduplex_dma/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/spi/ti_fullduplex_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/inc/at32f435_437_conf.h b/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvoptx b/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvoptx index 4904f3b2..011145f2 100644 --- a/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvoptx +++ b/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvprojx b/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvprojx index 3882caa4..7e28bbaf 100644 --- a/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvprojx +++ b/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/src/at32f435_437_clock.c b/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/spi/use_jtagpin_hardwarecs_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/spi/w25q_flash/inc/at32f435_437_conf.h b/project/at_start_f435/examples/spi/w25q_flash/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/spi/w25q_flash/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/spi/w25q_flash/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvoptx b/project/at_start_f435/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvoptx index d9bf897d..ec9dd06b 100644 --- a/project/at_start_f435/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvoptx +++ b/project/at_start_f435/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvprojx b/project/at_start_f435/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvprojx index 8531041a..ac203db7 100644 --- a/project/at_start_f435/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvprojx +++ b/project/at_start_f435/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/spi/w25q_flash/src/at32f435_437_clock.c b/project/at_start_f435/examples/spi/w25q_flash/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/spi/w25q_flash/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/spi/w25q_flash/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/sram/extend_sram/inc/at32f435_437_conf.h b/project/at_start_f435/examples/sram/extend_sram/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/sram/extend_sram/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/sram/extend_sram/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/sram/extend_sram/mdk_v5/extend_sram.uvoptx b/project/at_start_f435/examples/sram/extend_sram/mdk_v5/extend_sram.uvoptx index 2ba12cc4..b29135ff 100644 --- a/project/at_start_f435/examples/sram/extend_sram/mdk_v5/extend_sram.uvoptx +++ b/project/at_start_f435/examples/sram/extend_sram/mdk_v5/extend_sram.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/sram/extend_sram/mdk_v5/extend_sram.uvprojx b/project/at_start_f435/examples/sram/extend_sram/mdk_v5/extend_sram.uvprojx index cdc2e4cc..215b3a1c 100644 --- a/project/at_start_f435/examples/sram/extend_sram/mdk_v5/extend_sram.uvprojx +++ b/project/at_start_f435/examples/sram/extend_sram/mdk_v5/extend_sram.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -3234,4 +3234,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/sram/extend_sram/src/at32f435_437_clock.c b/project/at_start_f435/examples/sram/extend_sram/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/sram/extend_sram/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/sram/extend_sram/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/6_steps/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/6_steps/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/6_steps/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/6_steps/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/6_steps/mdk_v5/6_steps.uvoptx b/project/at_start_f435/examples/tmr/6_steps/mdk_v5/6_steps.uvoptx index d9f4906b..551b4a56 100644 --- a/project/at_start_f435/examples/tmr/6_steps/mdk_v5/6_steps.uvoptx +++ b/project/at_start_f435/examples/tmr/6_steps/mdk_v5/6_steps.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/6_steps/mdk_v5/6_steps.uvprojx b/project/at_start_f435/examples/tmr/6_steps/mdk_v5/6_steps.uvprojx index 3b0de91f..898a9b2f 100644 --- a/project/at_start_f435/examples/tmr/6_steps/mdk_v5/6_steps.uvprojx +++ b/project/at_start_f435/examples/tmr/6_steps/mdk_v5/6_steps.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/6_steps/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/6_steps/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/6_steps/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/6_steps/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/7_pwm_output/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/7_pwm_output/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/7_pwm_output/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/7_pwm_output/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvoptx b/project/at_start_f435/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvoptx index 08dfb7cb..3abe1d27 100644 --- a/project/at_start_f435/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvoptx +++ b/project/at_start_f435/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvprojx b/project/at_start_f435/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvprojx index fb5a342a..5ecbf145 100644 --- a/project/at_start_f435/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvprojx +++ b/project/at_start_f435/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/7_pwm_output/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/7_pwm_output/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/7_pwm_output/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/7_pwm_output/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/cascade_synchro/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/cascade_synchro/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/cascade_synchro/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/cascade_synchro/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvoptx b/project/at_start_f435/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvoptx index ba6a092f..4dd0336d 100644 --- a/project/at_start_f435/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvoptx +++ b/project/at_start_f435/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvprojx b/project/at_start_f435/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvprojx index f9423b77..c16f84de 100644 --- a/project/at_start_f435/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvprojx +++ b/project/at_start_f435/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/cascade_synchro/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/cascade_synchro/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/cascade_synchro/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/cascade_synchro/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/complementary_signals/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/complementary_signals/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/complementary_signals/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/complementary_signals/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvoptx b/project/at_start_f435/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvoptx index 33eac946..f160c0c1 100644 --- a/project/at_start_f435/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvoptx +++ b/project/at_start_f435/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvprojx b/project/at_start_f435/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvprojx index 74bdff63..55b2f4cf 100644 --- a/project/at_start_f435/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvprojx +++ b/project/at_start_f435/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/complementary_signals/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/complementary_signals/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/complementary_signals/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/complementary_signals/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/dma/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/dma/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/dma/mdk_v5/dma.uvoptx b/project/at_start_f435/examples/tmr/dma/mdk_v5/dma.uvoptx index 40eb04ce..e44936d2 100644 --- a/project/at_start_f435/examples/tmr/dma/mdk_v5/dma.uvoptx +++ b/project/at_start_f435/examples/tmr/dma/mdk_v5/dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/dma/mdk_v5/dma.uvprojx b/project/at_start_f435/examples/tmr/dma/mdk_v5/dma.uvprojx index dc139c08..05ee50b0b 100644 --- a/project/at_start_f435/examples/tmr/dma/mdk_v5/dma.uvprojx +++ b/project/at_start_f435/examples/tmr/dma/mdk_v5/dma.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/dma/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/dma/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/dma_burst/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/dma_burst/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/dma_burst/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/dma_burst/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/dma_burst/mdk_v5/dma_burst.uvoptx b/project/at_start_f435/examples/tmr/dma_burst/mdk_v5/dma_burst.uvoptx index e93598d2..bc5f030f 100644 --- a/project/at_start_f435/examples/tmr/dma_burst/mdk_v5/dma_burst.uvoptx +++ b/project/at_start_f435/examples/tmr/dma_burst/mdk_v5/dma_burst.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/dma_burst/mdk_v5/dma_burst.uvprojx b/project/at_start_f435/examples/tmr/dma_burst/mdk_v5/dma_burst.uvprojx index 67bc7f16..fef5ad4c 100644 --- a/project/at_start_f435/examples/tmr/dma_burst/mdk_v5/dma_burst.uvprojx +++ b/project/at_start_f435/examples/tmr/dma_burst/mdk_v5/dma_burst.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/dma_burst/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/dma_burst/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/dma_burst/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/dma_burst/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/encoder_tmr2/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/encoder_tmr2/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/encoder_tmr2/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/encoder_tmr2/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvoptx b/project/at_start_f435/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvoptx index 17280e20..355a3001 100644 --- a/project/at_start_f435/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvoptx +++ b/project/at_start_f435/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvprojx b/project/at_start_f435/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvprojx index 1194e042..7efc4c49 100644 --- a/project/at_start_f435/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvprojx +++ b/project/at_start_f435/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/encoder_tmr2/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/encoder_tmr2/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/encoder_tmr2/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/encoder_tmr2/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/external_clock/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/external_clock/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/external_clock/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/external_clock/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/external_clock/mdk_v5/external_clock.uvoptx b/project/at_start_f435/examples/tmr/external_clock/mdk_v5/external_clock.uvoptx index df7a9b5c..a58029f1 100644 --- a/project/at_start_f435/examples/tmr/external_clock/mdk_v5/external_clock.uvoptx +++ b/project/at_start_f435/examples/tmr/external_clock/mdk_v5/external_clock.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/external_clock/mdk_v5/external_clock.uvprojx b/project/at_start_f435/examples/tmr/external_clock/mdk_v5/external_clock.uvprojx index f9a17d11..d28e7905 100644 --- a/project/at_start_f435/examples/tmr/external_clock/mdk_v5/external_clock.uvprojx +++ b/project/at_start_f435/examples/tmr/external_clock/mdk_v5/external_clock.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/external_clock/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/external_clock/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/external_clock/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/external_clock/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/hall_xor_tmr2/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/hall_xor_tmr2/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/hall_xor_tmr2/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/hall_xor_tmr2/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvoptx b/project/at_start_f435/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvoptx index 264a40fe..05b1e1df 100644 --- a/project/at_start_f435/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvoptx +++ b/project/at_start_f435/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvprojx b/project/at_start_f435/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvprojx index 9c9bd092..c3b92b67 100644 --- a/project/at_start_f435/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvprojx +++ b/project/at_start_f435/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/hall_xor_tmr2/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/hall_xor_tmr2/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/hall_xor_tmr2/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/hall_xor_tmr2/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/hang_mode/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/hang_mode/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/hang_mode/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/hang_mode/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/hang_mode/mdk_v5/hang_mode.uvoptx b/project/at_start_f435/examples/tmr/hang_mode/mdk_v5/hang_mode.uvoptx index b4e03ec1..3feefb5b 100644 --- a/project/at_start_f435/examples/tmr/hang_mode/mdk_v5/hang_mode.uvoptx +++ b/project/at_start_f435/examples/tmr/hang_mode/mdk_v5/hang_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/hang_mode/mdk_v5/hang_mode.uvprojx b/project/at_start_f435/examples/tmr/hang_mode/mdk_v5/hang_mode.uvprojx index 1464eb09..a42ee5ae 100644 --- a/project/at_start_f435/examples/tmr/hang_mode/mdk_v5/hang_mode.uvprojx +++ b/project/at_start_f435/examples/tmr/hang_mode/mdk_v5/hang_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/hang_mode/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/hang_mode/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/hang_mode/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/hang_mode/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/input_capture/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/input_capture/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/input_capture/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/input_capture/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/input_capture/mdk_v5/input_capture.uvoptx b/project/at_start_f435/examples/tmr/input_capture/mdk_v5/input_capture.uvoptx index 1f057d8c..433becac 100644 --- a/project/at_start_f435/examples/tmr/input_capture/mdk_v5/input_capture.uvoptx +++ b/project/at_start_f435/examples/tmr/input_capture/mdk_v5/input_capture.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/input_capture/mdk_v5/input_capture.uvprojx b/project/at_start_f435/examples/tmr/input_capture/mdk_v5/input_capture.uvprojx index 4c8bf986..6ded1c79 100644 --- a/project/at_start_f435/examples/tmr/input_capture/mdk_v5/input_capture.uvprojx +++ b/project/at_start_f435/examples/tmr/input_capture/mdk_v5/input_capture.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/input_capture/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/input_capture/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/input_capture/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/input_capture/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/oc_high/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/oc_high/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/oc_high/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/oc_high/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/oc_high/mdk_v5/oc_high.uvoptx b/project/at_start_f435/examples/tmr/oc_high/mdk_v5/oc_high.uvoptx index 00e32b39..1c4575d8 100644 --- a/project/at_start_f435/examples/tmr/oc_high/mdk_v5/oc_high.uvoptx +++ b/project/at_start_f435/examples/tmr/oc_high/mdk_v5/oc_high.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/oc_high/mdk_v5/oc_high.uvprojx b/project/at_start_f435/examples/tmr/oc_high/mdk_v5/oc_high.uvprojx index 1d946761..7825df9e 100644 --- a/project/at_start_f435/examples/tmr/oc_high/mdk_v5/oc_high.uvprojx +++ b/project/at_start_f435/examples/tmr/oc_high/mdk_v5/oc_high.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/oc_high/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/oc_high/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/oc_high/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/oc_high/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/oc_low/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/oc_low/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/oc_low/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/oc_low/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/oc_low/mdk_v5/oc_low.uvoptx b/project/at_start_f435/examples/tmr/oc_low/mdk_v5/oc_low.uvoptx index e2dcf7f0..aab45bfa 100644 --- a/project/at_start_f435/examples/tmr/oc_low/mdk_v5/oc_low.uvoptx +++ b/project/at_start_f435/examples/tmr/oc_low/mdk_v5/oc_low.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/oc_low/mdk_v5/oc_low.uvprojx b/project/at_start_f435/examples/tmr/oc_low/mdk_v5/oc_low.uvprojx index 8547a74f..6fd1a5a2 100644 --- a/project/at_start_f435/examples/tmr/oc_low/mdk_v5/oc_low.uvprojx +++ b/project/at_start_f435/examples/tmr/oc_low/mdk_v5/oc_low.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/oc_low/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/oc_low/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/oc_low/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/oc_low/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/oc_toggle_tmr3/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/oc_toggle_tmr3/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/oc_toggle_tmr3/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/oc_toggle_tmr3/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvoptx b/project/at_start_f435/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvoptx index 5d5e5bcb..5abcd13c 100644 --- a/project/at_start_f435/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvoptx +++ b/project/at_start_f435/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvprojx b/project/at_start_f435/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvprojx index 1499ef1d..d71c1f62 100644 --- a/project/at_start_f435/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvprojx +++ b/project/at_start_f435/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/oc_toggle_tmr3/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/oc_toggle_tmr3/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/oc_toggle_tmr3/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/oc_toggle_tmr3/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/oc_toggle_tmr9/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/oc_toggle_tmr9/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/oc_toggle_tmr9/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/oc_toggle_tmr9/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvoptx b/project/at_start_f435/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvoptx index fae3fe2d..48610b51 100644 --- a/project/at_start_f435/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvoptx +++ b/project/at_start_f435/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvprojx b/project/at_start_f435/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvprojx index 1128e65d..99df1426 100644 --- a/project/at_start_f435/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvprojx +++ b/project/at_start_f435/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/oc_toggle_tmr9/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/oc_toggle_tmr9/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/oc_toggle_tmr9/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/oc_toggle_tmr9/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/one_cycle/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/one_cycle/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/one_cycle/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/one_cycle/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/one_cycle/mdk_v5/one_cycle.uvoptx b/project/at_start_f435/examples/tmr/one_cycle/mdk_v5/one_cycle.uvoptx index b72b7df3..6d323fd9 100644 --- a/project/at_start_f435/examples/tmr/one_cycle/mdk_v5/one_cycle.uvoptx +++ b/project/at_start_f435/examples/tmr/one_cycle/mdk_v5/one_cycle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/one_cycle/mdk_v5/one_cycle.uvprojx b/project/at_start_f435/examples/tmr/one_cycle/mdk_v5/one_cycle.uvprojx index 164c5e38..a5d2c44d 100644 --- a/project/at_start_f435/examples/tmr/one_cycle/mdk_v5/one_cycle.uvprojx +++ b/project/at_start_f435/examples/tmr/one_cycle/mdk_v5/one_cycle.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/one_cycle/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/one_cycle/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/one_cycle/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/one_cycle/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/parallel_synchro/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/parallel_synchro/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/parallel_synchro/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/parallel_synchro/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvoptx b/project/at_start_f435/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvoptx index 5157b593..e9945bf0 100644 --- a/project/at_start_f435/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvoptx +++ b/project/at_start_f435/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvprojx b/project/at_start_f435/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvprojx index 5f2fb00b..9bfc7443 100644 --- a/project/at_start_f435/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvprojx +++ b/project/at_start_f435/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/parallel_synchro/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/parallel_synchro/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/parallel_synchro/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/parallel_synchro/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/pwm_input/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/pwm_input/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/pwm_input/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/pwm_input/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/pwm_input/mdk_v5/pwm_input.uvoptx b/project/at_start_f435/examples/tmr/pwm_input/mdk_v5/pwm_input.uvoptx index 675d64f4..eac0585b 100644 --- a/project/at_start_f435/examples/tmr/pwm_input/mdk_v5/pwm_input.uvoptx +++ b/project/at_start_f435/examples/tmr/pwm_input/mdk_v5/pwm_input.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/pwm_input/mdk_v5/pwm_input.uvprojx b/project/at_start_f435/examples/tmr/pwm_input/mdk_v5/pwm_input.uvprojx index 1ed018a1..49e62e09 100644 --- a/project/at_start_f435/examples/tmr/pwm_input/mdk_v5/pwm_input.uvprojx +++ b/project/at_start_f435/examples/tmr/pwm_input/mdk_v5/pwm_input.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/pwm_input/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/pwm_input/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/pwm_input/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/pwm_input/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/pwm_input_dma/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/pwm_input_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/pwm_input_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/pwm_input_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvoptx b/project/at_start_f435/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvoptx index 5b196c73..230cd348 100644 --- a/project/at_start_f435/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvoptx +++ b/project/at_start_f435/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvprojx b/project/at_start_f435/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvprojx index 64b28e3e..0dca5f0e 100644 --- a/project/at_start_f435/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvprojx +++ b/project/at_start_f435/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/pwm_input_dma/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/pwm_input_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/pwm_input_dma/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/pwm_input_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/pwm_output_simulate/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/pwm_output_simulate/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/pwm_output_simulate/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/pwm_output_simulate/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvoptx b/project/at_start_f435/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvoptx index 0165baab..3f43c967 100644 --- a/project/at_start_f435/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvoptx +++ b/project/at_start_f435/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvprojx b/project/at_start_f435/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvprojx index 2898ba7e..72f7b8c0 100644 --- a/project/at_start_f435/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvprojx +++ b/project/at_start_f435/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/pwm_output_simulate/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/pwm_output_simulate/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/pwm_output_simulate/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/pwm_output_simulate/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/pwm_output_tmr10/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/pwm_output_tmr10/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/pwm_output_tmr10/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/pwm_output_tmr10/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvoptx b/project/at_start_f435/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvoptx index fa48c0b2..adcb4d9d 100644 --- a/project/at_start_f435/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvoptx +++ b/project/at_start_f435/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvprojx b/project/at_start_f435/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvprojx index c46e5cb7..551c0d9f 100644 --- a/project/at_start_f435/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvprojx +++ b/project/at_start_f435/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/pwm_output_tmr10/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/pwm_output_tmr10/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/pwm_output_tmr10/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/pwm_output_tmr10/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/pwm_output_tmr3/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/pwm_output_tmr3/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/pwm_output_tmr3/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/pwm_output_tmr3/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvoptx b/project/at_start_f435/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvoptx index 022ccc1e..b0ea0e33 100644 --- a/project/at_start_f435/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvoptx +++ b/project/at_start_f435/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvprojx b/project/at_start_f435/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvprojx index 82fa3f84..9aade926 100644 --- a/project/at_start_f435/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvprojx +++ b/project/at_start_f435/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/pwm_output_tmr3/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/pwm_output_tmr3/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/pwm_output_tmr3/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/pwm_output_tmr3/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/timer_base/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/timer_base/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/timer_base/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/timer_base/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/timer_base/mdk_v5/timer_base.uvoptx b/project/at_start_f435/examples/tmr/timer_base/mdk_v5/timer_base.uvoptx index 9a0d399c..ca3d87a4 100644 --- a/project/at_start_f435/examples/tmr/timer_base/mdk_v5/timer_base.uvoptx +++ b/project/at_start_f435/examples/tmr/timer_base/mdk_v5/timer_base.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/timer_base/mdk_v5/timer_base.uvprojx b/project/at_start_f435/examples/tmr/timer_base/mdk_v5/timer_base.uvprojx index 55ece9a3..d23e4a79 100644 --- a/project/at_start_f435/examples/tmr/timer_base/mdk_v5/timer_base.uvprojx +++ b/project/at_start_f435/examples/tmr/timer_base/mdk_v5/timer_base.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/timer_base/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/timer_base/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/timer_base/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/timer_base/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/tmr1_synchro/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/tmr1_synchro/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/tmr1_synchro/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/tmr1_synchro/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvoptx b/project/at_start_f435/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvoptx index aeb9571b..f60a13dc 100644 --- a/project/at_start_f435/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvoptx +++ b/project/at_start_f435/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvprojx b/project/at_start_f435/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvprojx index 89623199..8da118ea 100644 --- a/project/at_start_f435/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvprojx +++ b/project/at_start_f435/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/tmr1_synchro/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/tmr1_synchro/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/tmr1_synchro/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/tmr1_synchro/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/tmr/tmr2_32bit/inc/at32f435_437_conf.h b/project/at_start_f435/examples/tmr/tmr2_32bit/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/tmr/tmr2_32bit/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/tmr/tmr2_32bit/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvoptx b/project/at_start_f435/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvoptx index ff63af5c..11ceeec5 100644 --- a/project/at_start_f435/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvoptx +++ b/project/at_start_f435/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvprojx b/project/at_start_f435/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvprojx index 2f656cba..6d0952ad 100644 --- a/project/at_start_f435/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvprojx +++ b/project/at_start_f435/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/tmr/tmr2_32bit/src/at32f435_437_clock.c b/project/at_start_f435/examples/tmr/tmr2_32bit/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/tmr/tmr2_32bit/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/tmr/tmr2_32bit/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usart/half_duplex/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/half_duplex/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usart/half_duplex/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/half_duplex/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/half_duplex/mdk_v5/half_duplex.uvoptx b/project/at_start_f435/examples/usart/half_duplex/mdk_v5/half_duplex.uvoptx index f5682311..3ff5a21d 100644 --- a/project/at_start_f435/examples/usart/half_duplex/mdk_v5/half_duplex.uvoptx +++ b/project/at_start_f435/examples/usart/half_duplex/mdk_v5/half_duplex.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/half_duplex/mdk_v5/half_duplex.uvprojx b/project/at_start_f435/examples/usart/half_duplex/mdk_v5/half_duplex.uvprojx index 38428225..80bb3add 100644 --- a/project/at_start_f435/examples/usart/half_duplex/mdk_v5/half_duplex.uvprojx +++ b/project/at_start_f435/examples/usart/half_duplex/mdk_v5/half_duplex.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usart/half_duplex/src/at32f435_437_clock.c b/project/at_start_f435/examples/usart/half_duplex/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usart/half_duplex/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usart/half_duplex/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usart/hw_flow_control/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/hw_flow_control/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usart/hw_flow_control/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/hw_flow_control/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvoptx b/project/at_start_f435/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvoptx index 1eeaf972..ce3c0d35 100644 --- a/project/at_start_f435/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvoptx +++ b/project/at_start_f435/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvprojx b/project/at_start_f435/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvprojx index 137f1eac..1cd6d26a 100644 --- a/project/at_start_f435/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvprojx +++ b/project/at_start_f435/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usart/hw_flow_control/src/at32f435_437_clock.c b/project/at_start_f435/examples/usart/hw_flow_control/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usart/hw_flow_control/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usart/hw_flow_control/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usart/idle_detection/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/idle_detection/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usart/idle_detection/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/idle_detection/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/idle_detection/mdk_v5/idle_detection.uvoptx b/project/at_start_f435/examples/usart/idle_detection/mdk_v5/idle_detection.uvoptx index 127d7876..3b09ddab 100644 --- a/project/at_start_f435/examples/usart/idle_detection/mdk_v5/idle_detection.uvoptx +++ b/project/at_start_f435/examples/usart/idle_detection/mdk_v5/idle_detection.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/idle_detection/mdk_v5/idle_detection.uvprojx b/project/at_start_f435/examples/usart/idle_detection/mdk_v5/idle_detection.uvprojx index bd8bc735..375cd138 100644 --- a/project/at_start_f435/examples/usart/idle_detection/mdk_v5/idle_detection.uvprojx +++ b/project/at_start_f435/examples/usart/idle_detection/mdk_v5/idle_detection.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usart/idle_detection/src/at32f435_437_clock.c b/project/at_start_f435/examples/usart/idle_detection/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usart/idle_detection/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usart/idle_detection/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usart/interrupt/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/interrupt/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usart/interrupt/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/interrupt/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/interrupt/mdk_v5/interrupt.uvoptx b/project/at_start_f435/examples/usart/interrupt/mdk_v5/interrupt.uvoptx index 8a575da0..40738c2b 100644 --- a/project/at_start_f435/examples/usart/interrupt/mdk_v5/interrupt.uvoptx +++ b/project/at_start_f435/examples/usart/interrupt/mdk_v5/interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/interrupt/mdk_v5/interrupt.uvprojx b/project/at_start_f435/examples/usart/interrupt/mdk_v5/interrupt.uvprojx index a0c6ce87..f6f05559 100644 --- a/project/at_start_f435/examples/usart/interrupt/mdk_v5/interrupt.uvprojx +++ b/project/at_start_f435/examples/usart/interrupt/mdk_v5/interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/usart/interrupt/src/at32f435_437_clock.c b/project/at_start_f435/examples/usart/interrupt/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usart/interrupt/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usart/interrupt/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usart/irda/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/irda/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usart/irda/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/irda/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/irda/mdk_v5/irda.uvoptx b/project/at_start_f435/examples/usart/irda/mdk_v5/irda.uvoptx index a176bcaa..f365ebdc 100644 --- a/project/at_start_f435/examples/usart/irda/mdk_v5/irda.uvoptx +++ b/project/at_start_f435/examples/usart/irda/mdk_v5/irda.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/irda/mdk_v5/irda.uvprojx b/project/at_start_f435/examples/usart/irda/mdk_v5/irda.uvprojx index 3eb286cf..ca847be8 100644 --- a/project/at_start_f435/examples/usart/irda/mdk_v5/irda.uvprojx +++ b/project/at_start_f435/examples/usart/irda/mdk_v5/irda.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -924,4 +924,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usart/irda/src/at32f435_437_clock.c b/project/at_start_f435/examples/usart/irda/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usart/irda/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usart/irda/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usart/polling/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usart/polling/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/polling/mdk_v5/polling.uvoptx b/project/at_start_f435/examples/usart/polling/mdk_v5/polling.uvoptx index 304729b7..b9793478 100644 --- a/project/at_start_f435/examples/usart/polling/mdk_v5/polling.uvoptx +++ b/project/at_start_f435/examples/usart/polling/mdk_v5/polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/polling/mdk_v5/polling.uvprojx b/project/at_start_f435/examples/usart/polling/mdk_v5/polling.uvprojx index ff58549a..0d2742b8 100644 --- a/project/at_start_f435/examples/usart/polling/mdk_v5/polling.uvprojx +++ b/project/at_start_f435/examples/usart/polling/mdk_v5/polling.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usart/polling/src/at32f435_437_clock.c b/project/at_start_f435/examples/usart/polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usart/polling/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usart/polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usart/printf/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/printf/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usart/printf/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/printf/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/printf/mdk_v5/printf.uvoptx b/project/at_start_f435/examples/usart/printf/mdk_v5/printf.uvoptx index d4a4e43f..59bd24eb 100644 --- a/project/at_start_f435/examples/usart/printf/mdk_v5/printf.uvoptx +++ b/project/at_start_f435/examples/usart/printf/mdk_v5/printf.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/printf/mdk_v5/printf.uvprojx b/project/at_start_f435/examples/usart/printf/mdk_v5/printf.uvprojx index 59a07976..049bd9e1 100644 --- a/project/at_start_f435/examples/usart/printf/mdk_v5/printf.uvprojx +++ b/project/at_start_f435/examples/usart/printf/mdk_v5/printf.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/usart/printf/src/at32f435_437_clock.c b/project/at_start_f435/examples/usart/printf/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usart/printf/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usart/printf/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usart/receiver_mute/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/receiver_mute/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usart/receiver_mute/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/receiver_mute/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvoptx b/project/at_start_f435/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvoptx index bf99bf8d..b0c3a066 100644 --- a/project/at_start_f435/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvoptx +++ b/project/at_start_f435/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvprojx b/project/at_start_f435/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvprojx index f5c45a1d..b3c2a243 100644 --- a/project/at_start_f435/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvprojx +++ b/project/at_start_f435/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usart/receiver_mute/src/at32f435_437_clock.c b/project/at_start_f435/examples/usart/receiver_mute/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usart/receiver_mute/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usart/receiver_mute/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usart/rs485/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/rs485/inc/at32f435_437_conf.h index 8645761d..4b9d618f 100644 --- a/project/at_start_f435/examples/usart/rs485/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/rs485/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/rs485/mdk_v5/rs485.uvoptx b/project/at_start_f435/examples/usart/rs485/mdk_v5/rs485.uvoptx index 5b5fe22b..28bb34c1 100644 --- a/project/at_start_f435/examples/usart/rs485/mdk_v5/rs485.uvoptx +++ b/project/at_start_f435/examples/usart/rs485/mdk_v5/rs485.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/rs485/mdk_v5/rs485.uvprojx b/project/at_start_f435/examples/usart/rs485/mdk_v5/rs485.uvprojx index ca7cd9c2..6a59ecef 100644 --- a/project/at_start_f435/examples/usart/rs485/mdk_v5/rs485.uvprojx +++ b/project/at_start_f435/examples/usart/rs485/mdk_v5/rs485.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usart/smartcard/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/smartcard/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usart/smartcard/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/smartcard/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/smartcard/mdk_v5/smartcard.uvoptx b/project/at_start_f435/examples/usart/smartcard/mdk_v5/smartcard.uvoptx index 496ac3d8..7fc80646 100644 --- a/project/at_start_f435/examples/usart/smartcard/mdk_v5/smartcard.uvoptx +++ b/project/at_start_f435/examples/usart/smartcard/mdk_v5/smartcard.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/smartcard/mdk_v5/smartcard.uvprojx b/project/at_start_f435/examples/usart/smartcard/mdk_v5/smartcard.uvprojx index 15da615e..f0291bee 100644 --- a/project/at_start_f435/examples/usart/smartcard/mdk_v5/smartcard.uvprojx +++ b/project/at_start_f435/examples/usart/smartcard/mdk_v5/smartcard.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -479,4 +479,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usart/smartcard/src/at32f435_437_clock.c b/project/at_start_f435/examples/usart/smartcard/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usart/smartcard/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usart/smartcard/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usart/synchronous/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/synchronous/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usart/synchronous/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/synchronous/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/synchronous/mdk_v5/synchronous.uvoptx b/project/at_start_f435/examples/usart/synchronous/mdk_v5/synchronous.uvoptx index 1c17ad63..02cebbe9 100644 --- a/project/at_start_f435/examples/usart/synchronous/mdk_v5/synchronous.uvoptx +++ b/project/at_start_f435/examples/usart/synchronous/mdk_v5/synchronous.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/synchronous/mdk_v5/synchronous.uvprojx b/project/at_start_f435/examples/usart/synchronous/mdk_v5/synchronous.uvprojx index 6ff53798..dfef7edb 100644 --- a/project/at_start_f435/examples/usart/synchronous/mdk_v5/synchronous.uvprojx +++ b/project/at_start_f435/examples/usart/synchronous/mdk_v5/synchronous.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usart/synchronous/src/at32f435_437_clock.c b/project/at_start_f435/examples/usart/synchronous/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usart/synchronous/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usart/synchronous/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvoptx b/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvoptx index b28613b5..c1bc3150 100644 --- a/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvoptx +++ b/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvprojx b/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvprojx index c6ea7283..6b11264d 100644 --- a/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvprojx +++ b/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/src/at32f435_437_clock.c b/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usart/transfer_by_dma_interrupt/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usart/transfer_by_dma_polling/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/transfer_by_dma_polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usart/transfer_by_dma_polling/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/transfer_by_dma_polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvoptx b/project/at_start_f435/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvoptx index a5f90475..89f0d495 100644 --- a/project/at_start_f435/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvoptx +++ b/project/at_start_f435/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvprojx b/project/at_start_f435/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvprojx index 216d44f9..28be991e 100644 --- a/project/at_start_f435/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvprojx +++ b/project/at_start_f435/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usart/transfer_by_dma_polling/src/at32f435_437_clock.c b/project/at_start_f435/examples/usart/transfer_by_dma_polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usart/transfer_by_dma_polling/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usart/transfer_by_dma_polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usart/tx_rx_swap/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usart/tx_rx_swap/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usart/tx_rx_swap/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usart/tx_rx_swap/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvoptx b/project/at_start_f435/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvoptx index 793486eb..a7363061 100644 --- a/project/at_start_f435/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvoptx +++ b/project/at_start_f435/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvprojx b/project/at_start_f435/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvprojx index 531e2375..d183338e 100644 --- a/project/at_start_f435/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvprojx +++ b/project/at_start_f435/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usart/tx_rx_swap/src/at32f435_437_clock.c b/project/at_start_f435/examples/usart/tx_rx_swap/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usart/tx_rx_swap/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usart/tx_rx_swap/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/audio/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/audio/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/audio/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/audio/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/audio/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/audio/inc/usb_conf.h index a0c5081a..9c5f183e 100644 --- a/project/at_start_f435/examples/usb_device/audio/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/audio/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/audio/mdk_v5/audio.uvoptx b/project/at_start_f435/examples/usb_device/audio/mdk_v5/audio.uvoptx index 478ea43e..67defa3a 100644 --- a/project/at_start_f435/examples/usb_device/audio/mdk_v5/audio.uvoptx +++ b/project/at_start_f435/examples/usb_device/audio/mdk_v5/audio.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/audio/mdk_v5/audio.uvprojx b/project/at_start_f435/examples/usb_device/audio/mdk_v5/audio.uvprojx index e0a09c5b..b03d120c 100644 --- a/project/at_start_f435/examples/usb_device/audio/mdk_v5/audio.uvprojx +++ b/project/at_start_f435/examples/usb_device/audio/mdk_v5/audio.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -639,4 +639,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_device/audio/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/audio/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/audio/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/audio/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/audio/src/main.c b/project/at_start_f435/examples/usb_device/audio/src/main.c index b159a5b9..6950edef 100644 --- a/project/at_start_f435/examples/usb_device/audio/src/main.c +++ b/project/at_start_f435/examples/usb_device/audio/src/main.c @@ -211,7 +211,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_device/composite_audio_hid/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/composite_audio_hid/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/composite_audio_hid/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/composite_audio_hid/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/composite_audio_hid/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/composite_audio_hid/inc/usb_conf.h index dc84e60c..697f7426 100644 --- a/project/at_start_f435/examples/usb_device/composite_audio_hid/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/composite_audio_hid/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvoptx b/project/at_start_f435/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvoptx index f33f21e5..059dcb31 100644 --- a/project/at_start_f435/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvoptx +++ b/project/at_start_f435/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvprojx b/project/at_start_f435/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvprojx index e03864d5..d2deb185 100644 --- a/project/at_start_f435/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvprojx +++ b/project/at_start_f435/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -549,4 +549,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_device/composite_audio_hid/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/composite_audio_hid/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/composite_audio_hid/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/composite_audio_hid/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/composite_audio_hid/src/main.c b/project/at_start_f435/examples/usb_device/composite_audio_hid/src/main.c index 199504ff..2d2a0c91 100644 --- a/project/at_start_f435/examples/usb_device/composite_audio_hid/src/main.c +++ b/project/at_start_f435/examples/usb_device/composite_audio_hid/src/main.c @@ -218,7 +218,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/inc/usb_conf.h index ec6505be..3737d3fc 100644 --- a/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/inc/usb_conf.h @@ -118,7 +118,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvoptx b/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvoptx index 864ea720..5492148f 100644 --- a/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvoptx +++ b/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvprojx b/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvprojx index c9021b6b..2acdb61e 100644 --- a/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvprojx +++ b/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -629,4 +629,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/src/main.c b/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/src/main.c index a94b94d3..79bac076 100644 --- a/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/src/main.c +++ b/project/at_start_f435/examples/usb_device/composite_vcp_keyboard/src/main.c @@ -339,7 +339,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_device/composite_vcp_msc/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/composite_vcp_msc/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/composite_vcp_msc/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/composite_vcp_msc/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/composite_vcp_msc/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/composite_vcp_msc/inc/usb_conf.h index 899012c9..dce87d36 100644 --- a/project/at_start_f435/examples/usb_device/composite_vcp_msc/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/composite_vcp_msc/inc/usb_conf.h @@ -118,7 +118,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvoptx b/project/at_start_f435/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvoptx index 4dc13ebc..9fe93ce3 100644 --- a/project/at_start_f435/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvoptx +++ b/project/at_start_f435/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvprojx b/project/at_start_f435/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvprojx index 9d3c43de..bcd3926f 100644 --- a/project/at_start_f435/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvprojx +++ b/project/at_start_f435/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -639,4 +639,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_device/composite_vcp_msc/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/composite_vcp_msc/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/composite_vcp_msc/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/composite_vcp_msc/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/composite_vcp_msc/src/main.c b/project/at_start_f435/examples/usb_device/composite_vcp_msc/src/main.c index 0d83b59f..13a1165a 100644 --- a/project/at_start_f435/examples/usb_device/composite_vcp_msc/src/main.c +++ b/project/at_start_f435/examples/usb_device/composite_vcp_msc/src/main.c @@ -295,7 +295,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_device/custom_hid/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/custom_hid/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/custom_hid/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/custom_hid/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/custom_hid/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/custom_hid/inc/usb_conf.h index 3d9c3161..297c92de 100644 --- a/project/at_start_f435/examples/usb_device/custom_hid/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/custom_hid/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvoptx b/project/at_start_f435/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvoptx index f14ce191..760d46bb 100644 --- a/project/at_start_f435/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvoptx +++ b/project/at_start_f435/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvprojx b/project/at_start_f435/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvprojx index cc8f59ab..87e22331 100644 --- a/project/at_start_f435/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvprojx +++ b/project/at_start_f435/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -629,4 +629,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_device/custom_hid/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/custom_hid/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/custom_hid/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/custom_hid/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/custom_hid/src/main.c b/project/at_start_f435/examples/usb_device/custom_hid/src/main.c index 1c1e8fbe..46eecc4b 100644 --- a/project/at_start_f435/examples/usb_device/custom_hid/src/main.c +++ b/project/at_start_f435/examples/usb_device/custom_hid/src/main.c @@ -212,7 +212,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_device/keyboard/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/keyboard/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/keyboard/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/keyboard/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/keyboard/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/keyboard/inc/usb_conf.h index 6b39804e..3a2eba1e 100644 --- a/project/at_start_f435/examples/usb_device/keyboard/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/keyboard/inc/usb_conf.h @@ -117,7 +117,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/keyboard/mdk_v5/keyboard.uvoptx b/project/at_start_f435/examples/usb_device/keyboard/mdk_v5/keyboard.uvoptx index 5814e53d..1d973c05 100644 --- a/project/at_start_f435/examples/usb_device/keyboard/mdk_v5/keyboard.uvoptx +++ b/project/at_start_f435/examples/usb_device/keyboard/mdk_v5/keyboard.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/keyboard/mdk_v5/keyboard.uvprojx b/project/at_start_f435/examples/usb_device/keyboard/mdk_v5/keyboard.uvprojx index 4950978c..8030c13c 100644 --- a/project/at_start_f435/examples/usb_device/keyboard/mdk_v5/keyboard.uvprojx +++ b/project/at_start_f435/examples/usb_device/keyboard/mdk_v5/keyboard.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -629,4 +629,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_device/keyboard/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/keyboard/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/keyboard/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/keyboard/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/keyboard/src/main.c b/project/at_start_f435/examples/usb_device/keyboard/src/main.c index 27ec1de8..f6ebb8f8 100644 --- a/project/at_start_f435/examples/usb_device/keyboard/src/main.c +++ b/project/at_start_f435/examples/usb_device/keyboard/src/main.c @@ -292,7 +292,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_device/mouse/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/mouse/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/mouse/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/mouse/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/mouse/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/mouse/inc/usb_conf.h index 63f4ced7..c917a328 100644 --- a/project/at_start_f435/examples/usb_device/mouse/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/mouse/inc/usb_conf.h @@ -118,7 +118,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/mouse/mdk_v5/mouse.uvoptx b/project/at_start_f435/examples/usb_device/mouse/mdk_v5/mouse.uvoptx index c88c4151..fd39eb41 100644 --- a/project/at_start_f435/examples/usb_device/mouse/mdk_v5/mouse.uvoptx +++ b/project/at_start_f435/examples/usb_device/mouse/mdk_v5/mouse.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/mouse/mdk_v5/mouse.uvprojx b/project/at_start_f435/examples/usb_device/mouse/mdk_v5/mouse.uvprojx index 9ec68da5..d7ed4d68 100644 --- a/project/at_start_f435/examples/usb_device/mouse/mdk_v5/mouse.uvprojx +++ b/project/at_start_f435/examples/usb_device/mouse/mdk_v5/mouse.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -629,4 +629,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_device/mouse/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/mouse/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/mouse/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/mouse/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/mouse/src/main.c b/project/at_start_f435/examples/usb_device/mouse/src/main.c index 632a2a7d..5fdc9d89 100644 --- a/project/at_start_f435/examples/usb_device/mouse/src/main.c +++ b/project/at_start_f435/examples/usb_device/mouse/src/main.c @@ -262,7 +262,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_device/msc/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/msc/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/msc/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/msc/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/msc/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/msc/inc/usb_conf.h index 170fe09f..28c6ec89 100644 --- a/project/at_start_f435/examples/usb_device/msc/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/msc/inc/usb_conf.h @@ -86,7 +86,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 #define OTG_PIN_ID GPIO_PINS_10 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/msc/mdk_v5/msc.uvoptx b/project/at_start_f435/examples/usb_device/msc/mdk_v5/msc.uvoptx index 69af9c07..23f7b406 100644 --- a/project/at_start_f435/examples/usb_device/msc/mdk_v5/msc.uvoptx +++ b/project/at_start_f435/examples/usb_device/msc/mdk_v5/msc.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/msc/mdk_v5/msc.uvprojx b/project/at_start_f435/examples/usb_device/msc/mdk_v5/msc.uvprojx index 6982965b..4567567d 100644 --- a/project/at_start_f435/examples/usb_device/msc/mdk_v5/msc.uvprojx +++ b/project/at_start_f435/examples/usb_device/msc/mdk_v5/msc.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -639,4 +639,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_device/msc/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/msc/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/msc/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/msc/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/msc/src/main.c b/project/at_start_f435/examples/usb_device/msc/src/main.c index 9829e417..5182939d 100644 --- a/project/at_start_f435/examples/usb_device/msc/src/main.c +++ b/project/at_start_f435/examples/usb_device/msc/src/main.c @@ -208,7 +208,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/inc/usb_conf.h index 1978024f..19ee210a 100644 --- a/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/inc/usb_conf.h @@ -112,7 +112,7 @@ extern "C" { #define OTG2_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG2_PIN_ID GPIO_PINS_12 -#define OTG2_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG2_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG2_PIN_SOF_GPIO GPIOA #define OTG2_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvoptx b/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvoptx index a459b861..62615236 100644 --- a/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvoptx +++ b/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvprojx b/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvprojx index 736cc43f..0136e5a8 100644 --- a/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvprojx +++ b/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -674,4 +674,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/src/main.c b/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/src/main.c index 8e0fc094..47c78b34 100644 --- a/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/src/main.c +++ b/project/at_start_f435/examples/usb_device/otg1_host_otg2_device_demo/src/main.c @@ -283,7 +283,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_device/printer/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/printer/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/printer/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/printer/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/printer/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/printer/inc/usb_conf.h index 206cdfc2..eb151a70 100644 --- a/project/at_start_f435/examples/usb_device/printer/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/printer/inc/usb_conf.h @@ -117,7 +117,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/printer/mdk_v5/printer.uvoptx b/project/at_start_f435/examples/usb_device/printer/mdk_v5/printer.uvoptx index 09487472..0f579741 100644 --- a/project/at_start_f435/examples/usb_device/printer/mdk_v5/printer.uvoptx +++ b/project/at_start_f435/examples/usb_device/printer/mdk_v5/printer.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/printer/mdk_v5/printer.uvprojx b/project/at_start_f435/examples/usb_device/printer/mdk_v5/printer.uvprojx index b1bfc92d..b0f0015f 100644 --- a/project/at_start_f435/examples/usb_device/printer/mdk_v5/printer.uvprojx +++ b/project/at_start_f435/examples/usb_device/printer/mdk_v5/printer.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -629,4 +629,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_device/printer/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/printer/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/printer/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/printer/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/printer/src/main.c b/project/at_start_f435/examples/usb_device/printer/src/main.c index 036e6b9d..789f3954 100644 --- a/project/at_start_f435/examples/usb_device/printer/src/main.c +++ b/project/at_start_f435/examples/usb_device/printer/src/main.c @@ -210,7 +210,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_device/two_otg_device_demo/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/two_otg_device_demo/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/two_otg_device_demo/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/two_otg_device_demo/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/two_otg_device_demo/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/two_otg_device_demo/inc/usb_conf.h index 3cc3b3df..fdb91420 100644 --- a/project/at_start_f435/examples/usb_device/two_otg_device_demo/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/two_otg_device_demo/inc/usb_conf.h @@ -109,7 +109,7 @@ extern "C" { #define OTG2_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG2_PIN_ID GPIO_PINS_12 -#define OTG2_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG2_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG2_PIN_SOF_GPIO GPIOA #define OTG2_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvoptx b/project/at_start_f435/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvoptx index 8abd7b09..6ecacd51 100644 --- a/project/at_start_f435/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvoptx +++ b/project/at_start_f435/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvprojx b/project/at_start_f435/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvprojx index 1a621d21..7cc66960 100644 --- a/project/at_start_f435/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvprojx +++ b/project/at_start_f435/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -639,4 +639,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_device/two_otg_device_demo/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/two_otg_device_demo/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/two_otg_device_demo/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/two_otg_device_demo/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/two_otg_device_demo/src/main.c b/project/at_start_f435/examples/usb_device/two_otg_device_demo/src/main.c index 7ba2becf..932af359 100644 --- a/project/at_start_f435/examples/usb_device/two_otg_device_demo/src/main.c +++ b/project/at_start_f435/examples/usb_device/two_otg_device_demo/src/main.c @@ -315,7 +315,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ @@ -346,7 +346,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG2_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG2_PIN_SOF; gpio_init(OTG2_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG2_PIN_GPIO, OTG2_PIN_SOF_SOURCE, OTG2_PIN_MUX); + gpio_pin_mux_config(OTG2_PIN_SOF_GPIO, OTG2_PIN_SOF_SOURCE, OTG2_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_device/vcp_loopback/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/vcp_loopback/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/vcp_loopback/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/vcp_loopback/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/vcp_loopback/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/vcp_loopback/inc/usb_conf.h index 176f5316..2029043b 100644 --- a/project/at_start_f435/examples/usb_device/vcp_loopback/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/vcp_loopback/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvoptx b/project/at_start_f435/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvoptx index 0ae30264..651f8e8c 100644 --- a/project/at_start_f435/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvoptx +++ b/project/at_start_f435/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvprojx b/project/at_start_f435/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvprojx index 474c54ea..215fa612 100644 --- a/project/at_start_f435/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvprojx +++ b/project/at_start_f435/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -629,4 +629,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_device/vcp_loopback/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/vcp_loopback/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/vcp_loopback/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/vcp_loopback/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/vcp_loopback/src/main.c b/project/at_start_f435/examples/usb_device/vcp_loopback/src/main.c index 9153e3f9..40b01b1a 100644 --- a/project/at_start_f435/examples/usb_device/vcp_loopback/src/main.c +++ b/project/at_start_f435/examples/usb_device/vcp_loopback/src/main.c @@ -237,7 +237,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_device/virtual_comport/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/virtual_comport/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/virtual_comport/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/virtual_comport/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/virtual_comport/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/virtual_comport/inc/usb_conf.h index 2f51d4c1..8c50021e 100644 --- a/project/at_start_f435/examples/usb_device/virtual_comport/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/virtual_comport/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvoptx b/project/at_start_f435/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvoptx index d59d9641..f74b4a86 100644 --- a/project/at_start_f435/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvoptx +++ b/project/at_start_f435/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvprojx b/project/at_start_f435/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvprojx index b208c7f1..88071dfe 100644 --- a/project/at_start_f435/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvprojx +++ b/project/at_start_f435/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -633,6 +633,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/usb_device/virtual_comport/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/virtual_comport/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/virtual_comport/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/virtual_comport/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/virtual_comport/src/main.c b/project/at_start_f435/examples/usb_device/virtual_comport/src/main.c index 1e46ef8b..80d9c3af 100644 --- a/project/at_start_f435/examples/usb_device/virtual_comport/src/main.c +++ b/project/at_start_f435/examples/usb_device/virtual_comport/src/main.c @@ -455,7 +455,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_device/virtual_msc_iap/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_device/virtual_msc_iap/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_device/virtual_msc_iap/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_device/virtual_msc_iap/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_device/virtual_msc_iap/inc/usb_conf.h b/project/at_start_f435/examples/usb_device/virtual_msc_iap/inc/usb_conf.h index 500fba94..559c592f 100644 --- a/project/at_start_f435/examples/usb_device/virtual_msc_iap/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_device/virtual_msc_iap/inc/usb_conf.h @@ -118,7 +118,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvoptx b/project/at_start_f435/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvoptx index 28c9eae1..58384394 100644 --- a/project/at_start_f435/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvoptx +++ b/project/at_start_f435/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvprojx b/project/at_start_f435/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvprojx index 033fdc67..3ba28adc 100644 --- a/project/at_start_f435/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvprojx +++ b/project/at_start_f435/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -644,4 +644,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_device/virtual_msc_iap/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_device/virtual_msc_iap/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_device/virtual_msc_iap/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_device/virtual_msc_iap/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_device/virtual_msc_iap/src/main.c b/project/at_start_f435/examples/usb_device/virtual_msc_iap/src/main.c index b2dec873..039014f8 100644 --- a/project/at_start_f435/examples/usb_device/virtual_msc_iap/src/main.c +++ b/project/at_start_f435/examples/usb_device/virtual_msc_iap/src/main.c @@ -223,7 +223,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_host/cdc_demo/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_host/cdc_demo/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_host/cdc_demo/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_host/cdc_demo/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_host/cdc_demo/inc/usb_conf.h b/project/at_start_f435/examples/usb_host/cdc_demo/inc/usb_conf.h index b96a1d59..91f16af9 100644 --- a/project/at_start_f435/examples/usb_host/cdc_demo/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_host/cdc_demo/inc/usb_conf.h @@ -119,7 +119,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_host/cdc_demo/mdk_v5/cdc.uvoptx b/project/at_start_f435/examples/usb_host/cdc_demo/mdk_v5/cdc.uvoptx index 88c97069..ac3720a9 100644 --- a/project/at_start_f435/examples/usb_host/cdc_demo/mdk_v5/cdc.uvoptx +++ b/project/at_start_f435/examples/usb_host/cdc_demo/mdk_v5/cdc.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_host/cdc_demo/mdk_v5/cdc.uvprojx b/project/at_start_f435/examples/usb_host/cdc_demo/mdk_v5/cdc.uvprojx index 20762929..844a6dff 100644 --- a/project/at_start_f435/examples/usb_host/cdc_demo/mdk_v5/cdc.uvprojx +++ b/project/at_start_f435/examples/usb_host/cdc_demo/mdk_v5/cdc.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -633,6 +633,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/usb_host/cdc_demo/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_host/cdc_demo/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_host/cdc_demo/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_host/cdc_demo/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_host/cdc_demo/src/main.c b/project/at_start_f435/examples/usb_host/cdc_demo/src/main.c index 4cd3d9ba..621814d8 100644 --- a/project/at_start_f435/examples/usb_host/cdc_demo/src/main.c +++ b/project/at_start_f435/examples/usb_host/cdc_demo/src/main.c @@ -239,7 +239,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_host/hid_demo/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_host/hid_demo/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_host/hid_demo/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_host/hid_demo/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_host/hid_demo/inc/usb_conf.h b/project/at_start_f435/examples/usb_host/hid_demo/inc/usb_conf.h index a6c28a0d..ee456569 100644 --- a/project/at_start_f435/examples/usb_host/hid_demo/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_host/hid_demo/inc/usb_conf.h @@ -120,7 +120,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvoptx b/project/at_start_f435/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvoptx index 4c2ccb12..d2245911 100644 --- a/project/at_start_f435/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvoptx +++ b/project/at_start_f435/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvprojx b/project/at_start_f435/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvprojx index 2701b51f..191a19f7 100644 --- a/project/at_start_f435/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvprojx +++ b/project/at_start_f435/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -639,4 +639,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_host/hid_demo/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_host/hid_demo/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_host/hid_demo/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_host/hid_demo/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_host/hid_demo/src/main.c b/project/at_start_f435/examples/usb_host/hid_demo/src/main.c index d34e992f..fa744676 100644 --- a/project/at_start_f435/examples/usb_host/hid_demo/src/main.c +++ b/project/at_start_f435/examples/usb_host/hid_demo/src/main.c @@ -250,7 +250,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_host/msc_only_fat32/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_host/msc_only_fat32/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_host/msc_only_fat32/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_host/msc_only_fat32/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_host/msc_only_fat32/inc/usb_conf.h b/project/at_start_f435/examples/usb_host/msc_only_fat32/inc/usb_conf.h index 43bbef4a..3fb6d06a 100644 --- a/project/at_start_f435/examples/usb_host/msc_only_fat32/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_host/msc_only_fat32/inc/usb_conf.h @@ -119,7 +119,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvoptx b/project/at_start_f435/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvoptx index dc92882a..2fba1cc4 100644 --- a/project/at_start_f435/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvoptx +++ b/project/at_start_f435/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvprojx b/project/at_start_f435/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvprojx index ebbabc63..4fdd6ec5 100644 --- a/project/at_start_f435/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvprojx +++ b/project/at_start_f435/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -649,4 +649,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_host/msc_only_fat32/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_host/msc_only_fat32/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_host/msc_only_fat32/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_host/msc_only_fat32/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_host/msc_only_fat32/src/main.c b/project/at_start_f435/examples/usb_host/msc_only_fat32/src/main.c index 69c25c7c..da0ead5b 100644 --- a/project/at_start_f435/examples/usb_host/msc_only_fat32/src/main.c +++ b/project/at_start_f435/examples/usb_host/msc_only_fat32/src/main.c @@ -204,7 +204,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/usb_host/two_otg_host_demo/inc/at32f435_437_conf.h b/project/at_start_f435/examples/usb_host/two_otg_host_demo/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/usb_host/two_otg_host_demo/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/usb_host/two_otg_host_demo/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/usb_host/two_otg_host_demo/inc/usb_conf.h b/project/at_start_f435/examples/usb_host/two_otg_host_demo/inc/usb_conf.h index c8bfaf9c..5ab07752 100644 --- a/project/at_start_f435/examples/usb_host/two_otg_host_demo/inc/usb_conf.h +++ b/project/at_start_f435/examples/usb_host/two_otg_host_demo/inc/usb_conf.h @@ -112,7 +112,7 @@ extern "C" { #define OTG2_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG2_PIN_ID GPIO_PINS_12 -#define OTG2_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG2_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG2_PIN_SOF_GPIO GPIOA #define OTG2_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f435/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvoptx b/project/at_start_f435/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvoptx index 4f203804..2dbc54d9 100644 --- a/project/at_start_f435/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvoptx +++ b/project/at_start_f435/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvprojx b/project/at_start_f435/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvprojx index a81ae0a8..216861b7 100644 --- a/project/at_start_f435/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvprojx +++ b/project/at_start_f435/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -664,4 +664,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/usb_host/two_otg_host_demo/src/at32f435_437_clock.c b/project/at_start_f435/examples/usb_host/two_otg_host_demo/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/usb_host/two_otg_host_demo/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/usb_host/two_otg_host_demo/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/usb_host/two_otg_host_demo/src/main.c b/project/at_start_f435/examples/usb_host/two_otg_host_demo/src/main.c index b8408b28..2e9a9c55 100644 --- a/project/at_start_f435/examples/usb_host/two_otg_host_demo/src/main.c +++ b/project/at_start_f435/examples/usb_host/two_otg_host_demo/src/main.c @@ -215,7 +215,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f435/examples/wdt/wdt_reset/inc/at32f435_437_conf.h b/project/at_start_f435/examples/wdt/wdt_reset/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/wdt/wdt_reset/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/wdt/wdt_reset/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvoptx b/project/at_start_f435/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvoptx index a7faeb81..fc2c7ed7 100644 --- a/project/at_start_f435/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvoptx +++ b/project/at_start_f435/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvprojx b/project/at_start_f435/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvprojx index 9570a5a7..3d0766c8 100644 --- a/project/at_start_f435/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvprojx +++ b/project/at_start_f435/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/wdt/wdt_reset/src/at32f435_437_clock.c b/project/at_start_f435/examples/wdt/wdt_reset/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/wdt/wdt_reset/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/wdt/wdt_reset/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/wdt/wdt_standby/inc/at32f435_437_conf.h b/project/at_start_f435/examples/wdt/wdt_standby/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/wdt/wdt_standby/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/wdt/wdt_standby/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvoptx b/project/at_start_f435/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvoptx index 12effefa..3ba4a730 100644 --- a/project/at_start_f435/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvoptx +++ b/project/at_start_f435/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvprojx b/project/at_start_f435/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvprojx index 2282f97e..1303d653 100644 --- a/project/at_start_f435/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvprojx +++ b/project/at_start_f435/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/wdt/wdt_standby/src/at32f435_437_clock.c b/project/at_start_f435/examples/wdt/wdt_standby/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/wdt/wdt_standby/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/wdt/wdt_standby/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/wwdt/wwdt_reset/inc/at32f435_437_conf.h b/project/at_start_f435/examples/wwdt/wwdt_reset/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/wwdt/wwdt_reset/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/wwdt/wwdt_reset/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvoptx b/project/at_start_f435/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvoptx index 3d6682df..b413050e 100644 --- a/project/at_start_f435/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvoptx +++ b/project/at_start_f435/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvprojx b/project/at_start_f435/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvprojx index c862da12..8056dd0e 100644 --- a/project/at_start_f435/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvprojx +++ b/project/at_start_f435/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/wwdt/wwdt_reset/src/at32f435_437_clock.c b/project/at_start_f435/examples/wwdt/wwdt_reset/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/wwdt/wwdt_reset/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/wwdt/wwdt_reset/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/xmc/lcd_8bit/inc/at32f435_437_conf.h b/project/at_start_f435/examples/xmc/lcd_8bit/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/xmc/lcd_8bit/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/xmc/lcd_8bit/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvoptx b/project/at_start_f435/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvoptx index e8fea463..8634e8c6 100644 --- a/project/at_start_f435/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvoptx +++ b/project/at_start_f435/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvprojx b/project/at_start_f435/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvprojx index fd51141f..21c5dfa0 100644 --- a/project/at_start_f435/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvprojx +++ b/project/at_start_f435/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/xmc/lcd_8bit/src/at32f435_437_clock.c b/project/at_start_f435/examples/xmc/lcd_8bit/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/xmc/lcd_8bit/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/xmc/lcd_8bit/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/xmc/lcd_touch_16bit/inc/at32f435_437_conf.h b/project/at_start_f435/examples/xmc/lcd_touch_16bit/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/xmc/lcd_touch_16bit/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/xmc/lcd_touch_16bit/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvoptx b/project/at_start_f435/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvoptx index c91ca9b4..a2f4056e 100644 --- a/project/at_start_f435/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvoptx +++ b/project/at_start_f435/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvprojx b/project/at_start_f435/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvprojx index 94cb8b2a..13ddaa13 100644 --- a/project/at_start_f435/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvprojx +++ b/project/at_start_f435/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/xmc/lcd_touch_16bit/src/at32f435_437_clock.c b/project/at_start_f435/examples/xmc/lcd_touch_16bit/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/xmc/lcd_touch_16bit/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/xmc/lcd_touch_16bit/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/xmc/nand_flash/ecc/inc/at32f435_437_conf.h b/project/at_start_f435/examples/xmc/nand_flash/ecc/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/xmc/nand_flash/ecc/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/xmc/nand_flash/ecc/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvoptx b/project/at_start_f435/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvoptx index 477ea580..28e95535 100644 --- a/project/at_start_f435/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvoptx +++ b/project/at_start_f435/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvprojx b/project/at_start_f435/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvprojx index 199d4717..a2e3324b 100644 --- a/project/at_start_f435/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvprojx +++ b/project/at_start_f435/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -948,6 +948,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/xmc/nand_flash/ecc/src/at32f435_437_clock.c b/project/at_start_f435/examples/xmc/nand_flash/ecc/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/xmc/nand_flash/ecc/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/xmc/nand_flash/ecc/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/xmc/nand_flash/nand/inc/at32f435_437_conf.h b/project/at_start_f435/examples/xmc/nand_flash/nand/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/xmc/nand_flash/nand/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/xmc/nand_flash/nand/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/xmc/nand_flash/nand/mdk_v5/nand.uvoptx b/project/at_start_f435/examples/xmc/nand_flash/nand/mdk_v5/nand.uvoptx index cef00126..dc3204b3 100644 --- a/project/at_start_f435/examples/xmc/nand_flash/nand/mdk_v5/nand.uvoptx +++ b/project/at_start_f435/examples/xmc/nand_flash/nand/mdk_v5/nand.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/xmc/nand_flash/nand/mdk_v5/nand.uvprojx b/project/at_start_f435/examples/xmc/nand_flash/nand/mdk_v5/nand.uvprojx index 841d981c..b8a969e7 100644 --- a/project/at_start_f435/examples/xmc/nand_flash/nand/mdk_v5/nand.uvprojx +++ b/project/at_start_f435/examples/xmc/nand_flash/nand/mdk_v5/nand.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -948,6 +948,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/xmc/nand_flash/nand/src/at32f435_437_clock.c b/project/at_start_f435/examples/xmc/nand_flash/nand/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/xmc/nand_flash/nand/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/xmc/nand_flash/nand/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/xmc/nor_flash/inc/at32f435_437_conf.h b/project/at_start_f435/examples/xmc/nor_flash/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/xmc/nor_flash/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/xmc/nor_flash/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/xmc/nor_flash/mdk_v5/nor_flash.uvoptx b/project/at_start_f435/examples/xmc/nor_flash/mdk_v5/nor_flash.uvoptx index 9d44c540..eaf5c5f1 100644 --- a/project/at_start_f435/examples/xmc/nor_flash/mdk_v5/nor_flash.uvoptx +++ b/project/at_start_f435/examples/xmc/nor_flash/mdk_v5/nor_flash.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/xmc/nor_flash/mdk_v5/nor_flash.uvprojx b/project/at_start_f435/examples/xmc/nor_flash/mdk_v5/nor_flash.uvprojx index 0802dff3..2c410536 100644 --- a/project/at_start_f435/examples/xmc/nor_flash/mdk_v5/nor_flash.uvprojx +++ b/project/at_start_f435/examples/xmc/nor_flash/mdk_v5/nor_flash.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/xmc/nor_flash/src/at32f435_437_clock.c b/project/at_start_f435/examples/xmc/nor_flash/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/xmc/nor_flash/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/xmc/nor_flash/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/xmc/pc_card/inc/at32f435_437_clock.h b/project/at_start_f435/examples/xmc/pc_card/inc/at32f435_437_clock.h new file mode 100644 index 00000000..9a636f09 --- /dev/null +++ b/project/at_start_f435/examples/xmc/pc_card/inc/at32f435_437_clock.h @@ -0,0 +1,44 @@ +/** + ************************************************************************** + * @file at32f435_437_clock.h + * @brief header file of clock program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AT32F435_437_CLOCK_H +#define __AT32F435_437_CLOCK_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437.h" + +/* exported functions ------------------------------------------------------- */ +void system_clock_config(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/project/at_start_f435/examples/xmc/pc_card/inc/at32f435_437_conf.h b/project/at_start_f435/examples/xmc/pc_card/inc/at32f435_437_conf.h new file mode 100644 index 00000000..12638db0 --- /dev/null +++ b/project/at_start_f435/examples/xmc/pc_card/inc/at32f435_437_conf.h @@ -0,0 +1,173 @@ +/** + ************************************************************************** + * @file at32f435_437_conf.h + * @brief at32f435_437 config header file + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AT32F435_437_CONF_H +#define __AT32F435_437_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief in the following line adjust the value of high speed exernal crystal (hext) + * used in your application + * + * tip: to avoid modifying this file each time you need to use different hext, you + * can define the hext value in your toolchain compiler preprocessor. + * + */ +#if !defined HEXT_VALUE +#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed exernal crystal in hz */ +#endif + +/** + * @brief in the following line adjust the high speed exernal crystal (hext) startup + * timeout value + */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ + +/* module define -------------------------------------------------------------*/ +#define CRM_MODULE_ENABLED +#define TMR_MODULE_ENABLED +#define ERTC_MODULE_ENABLED +#define GPIO_MODULE_ENABLED +#define I2C_MODULE_ENABLED +#define USART_MODULE_ENABLED +#define PWC_MODULE_ENABLED +#define CAN_MODULE_ENABLED +#define ADC_MODULE_ENABLED +#define DAC_MODULE_ENABLED +#define SPI_MODULE_ENABLED +#define EDMA_MODULE_ENABLED +#define DMA_MODULE_ENABLED +#define DEBUG_MODULE_ENABLED +#define FLASH_MODULE_ENABLED +#define CRC_MODULE_ENABLED +#define WWDT_MODULE_ENABLED +#define WDT_MODULE_ENABLED +#define EXINT_MODULE_ENABLED +#define SDIO_MODULE_ENABLED +#define XMC_MODULE_ENABLED +#define USB_MODULE_ENABLED +#define ACC_MODULE_ENABLED +#define MISC_MODULE_ENABLED +#define QSPI_MODULE_ENABLED +#define DVP_MODULE_ENABLED +#define SCFG_MODULE_ENABLED +#define EMAC_MODULE_ENABLED + +/* includes ------------------------------------------------------------------*/ +#ifdef CRM_MODULE_ENABLED +#include "at32f435_437_crm.h" +#endif +#ifdef TMR_MODULE_ENABLED +#include "at32f435_437_tmr.h" +#endif +#ifdef ERTC_MODULE_ENABLED +#include "at32f435_437_ertc.h" +#endif +#ifdef GPIO_MODULE_ENABLED +#include "at32f435_437_gpio.h" +#endif +#ifdef I2C_MODULE_ENABLED +#include "at32f435_437_i2c.h" +#endif +#ifdef USART_MODULE_ENABLED +#include "at32f435_437_usart.h" +#endif +#ifdef PWC_MODULE_ENABLED +#include "at32f435_437_pwc.h" +#endif +#ifdef CAN_MODULE_ENABLED +#include "at32f435_437_can.h" +#endif +#ifdef ADC_MODULE_ENABLED +#include "at32f435_437_adc.h" +#endif +#ifdef DAC_MODULE_ENABLED +#include "at32f435_437_dac.h" +#endif +#ifdef SPI_MODULE_ENABLED +#include "at32f435_437_spi.h" +#endif +#ifdef DMA_MODULE_ENABLED +#include "at32f435_437_dma.h" +#endif +#ifdef DEBUG_MODULE_ENABLED +#include "at32f435_437_debug.h" +#endif +#ifdef FLASH_MODULE_ENABLED +#include "at32f435_437_flash.h" +#endif +#ifdef CRC_MODULE_ENABLED +#include "at32f435_437_crc.h" +#endif +#ifdef WWDT_MODULE_ENABLED +#include "at32f435_437_wwdt.h" +#endif +#ifdef WDT_MODULE_ENABLED +#include "at32f435_437_wdt.h" +#endif +#ifdef EXINT_MODULE_ENABLED +#include "at32f435_437_exint.h" +#endif +#ifdef SDIO_MODULE_ENABLED +#include "at32f435_437_sdio.h" +#endif +#ifdef XMC_MODULE_ENABLED +#include "at32f435_437_xmc.h" +#endif +#ifdef ACC_MODULE_ENABLED +#include "at32f435_437_acc.h" +#endif +#ifdef MISC_MODULE_ENABLED +#include "at32f435_437_misc.h" +#endif +#ifdef EDMA_MODULE_ENABLED +#include "at32f435_437_edma.h" +#endif +#ifdef QSPI_MODULE_ENABLED +#include "at32f435_437_qspi.h" +#endif +#ifdef SCFG_MODULE_ENABLED +#include "at32f435_437_scfg.h" +#endif +#ifdef EMAC_MODULE_ENABLED +#include "at32f435_437_emac.h" +#endif +#ifdef DVP_MODULE_ENABLED +#include "at32f435_437_dvp.h" +#endif +#ifdef USB_MODULE_ENABLED +#include "at32f435_437_usb.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/project/at_start_f435/examples/xmc/pc_card/inc/at32f435_437_int.h b/project/at_start_f435/examples/xmc/pc_card/inc/at32f435_437_int.h new file mode 100644 index 00000000..bc319dcd --- /dev/null +++ b/project/at_start_f435/examples/xmc/pc_card/inc/at32f435_437_int.h @@ -0,0 +1,56 @@ +/** + ************************************************************************** + * @file at32f435_437_int.h + * @brief header file of main interrupt service routines. + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AT32F435_437_INT_H +#define __AT32F435_437_INT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437.h" + +/* exported types ------------------------------------------------------------*/ +/* exported constants --------------------------------------------------------*/ +/* exported macro ------------------------------------------------------------*/ +/* exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/project/at_start_f435/examples/xmc/pc_card/mdk_v5/pc_card.uvoptx b/project/at_start_f435/examples/xmc/pc_card/mdk_v5/pc_card.uvoptx new file mode 100644 index 00000000..32f01221 --- /dev/null +++ b/project/at_start_f435/examples/xmc/pc_card/mdk_v5/pc_card.uvoptx @@ -0,0 +1,380 @@ + + + + 1.0 + +

                    ### uVision Project, (C) Keil Software
                    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + pc_card + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0AT32F435_4032 -FS08000000 -FL03F0000 -FP0($$Device:-AT32F435ZMT7$Flash\AT32F435_4032.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + user + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\src\at32f435_437_clock.c + at32f435_437_clock.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\src\at32f435_437_int.c + at32f435_437_int.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\src\main.c + main.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\PC_card\cf.c + cf.c + 0 + 0 + + + + + bsp + 0 + 0 + 0 + 0 + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\at32f435_437_board\at32f435_437_board.c + at32f435_437_board.c + 0 + 0 + + + + + firmware + 0 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_crm.c + at32f435_437_crm.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_gpio.c + at32f435_437_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_misc.c + at32f435_437_misc.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_xmc.c + at32f435_437_xmc.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_usart.c + at32f435_437_usart.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_edma.c + at32f435_437_edma.c + 0 + 0 + + + + + cmsis + 0 + 0 + 0 + 0 + + 4 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\system_at32f435_437.c + system_at32f435_437.c + 0 + 0 + + + 4 + 13 + 2 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\startup\mdk\startup_at32f435_437.s + startup_at32f435_437.s + 0 + 0 + + + + + readme + 0 + 0 + 0 + 0 + + 5 + 14 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + diff --git a/project/at_start_f435/examples/xmc/pc_card/mdk_v5/pc_card.uvprojx b/project/at_start_f435/examples/xmc/pc_card/mdk_v5/pc_card.uvprojx new file mode 100644 index 00000000..1f8a7fac --- /dev/null +++ b/project/at_start_f435/examples/xmc/pc_card/mdk_v5/pc_card.uvprojx @@ -0,0 +1,502 @@ + + + + 2.1 + +
                    ### uVision Project, (C) Keil Software
                    + + + + pc_card + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + -AT32F435ZMT7 + ArteryTek + ArteryTek.AT32F435_437_DFP.2.0.1 + IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0AT32F435_4032 -FS08000000 -FL03F0000 -FP0($$Device:-AT32F435ZMT7$Flash\AT32F435_4032.FLM)) + 0 + $$Device:- + + + + + + + + + + $$Device:-AT32F435ZMT7$SVD\AT32F435xx_v2.svd + 0 + 0 + + + + AT32F435ZMT7$Device\Include\at32f435_437.h\ + AT32F435ZMT7$Device\Include\at32f435_437.h\ + + 0 + 0 + 0 + 0 + 1 + + .\objects\ + pc_card + 1 + 0 + 1 + 1 + 1 + .\listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x8000000 + 0x3f0000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x3f0000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + AT32F435ZMT7,USE_STDPERIPH_DRIVER,AT_START_F435_V1 + + ..\..\..\..\..\..\libraries\drivers\inc;..\..\..\..\..\..\libraries\cmsis\cm4\core_support;..\..\..\..\..\..\libraries\cmsis\cm4\device_support;..\inc;..\..\..\..\..\at32f435_437_board;..\pc_card + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + user + + + at32f435_437_clock.c + 1 + ..\src\at32f435_437_clock.c + + + at32f435_437_int.c + 1 + ..\src\at32f435_437_int.c + + + main.c + 1 + ..\src\main.c + + + cf.c + 1 + ..\PC_card\cf.c + + + + + bsp + + + at32f435_437_board.c + 1 + ..\..\..\..\..\at32f435_437_board\at32f435_437_board.c + + + + + firmware + + + at32f435_437_crm.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_crm.c + + + at32f435_437_gpio.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_gpio.c + + + at32f435_437_misc.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_misc.c + + + at32f435_437_xmc.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_xmc.c + + + at32f435_437_usart.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_usart.c + + + at32f435_437_edma.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_edma.c + + + + + cmsis + + + system_at32f435_437.c + 1 + ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\system_at32f435_437.c + + + startup_at32f435_437.s + 2 + ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\startup\mdk\startup_at32f435_437.s + + + + + readme + + + readme.txt + 5 + ..\readme.txt + + + + + + + + + + + + + + + + + sram + + + + + + 0 + 1 + + + + +                     diff --git a/project/at_start_f435/examples/xmc/pc_card/pc_card/cf.c b/project/at_start_f435/examples/xmc/pc_card/pc_card/cf.c new file mode 100644 index 00000000..b7f520ad --- /dev/null +++ b/project/at_start_f435/examples/xmc/pc_card/pc_card/cf.c @@ -0,0 +1,2592 @@ +/** + ************************************************************************** + * @file cf.c + * @brief xmc pc card program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "cf.h" +#include "at32f435_437.h" +#include "at32f435_437_board.h" +#include +#include +#include + +/** @addtogroup AT32F435_periph_examples + * @{ + */ + +/** @addtogroup XMC_CF_CARD + * @{ + */ + +edma_init_type EDMA_InitStructure; +u16 DMA1_MEM_LEN; +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PCCARD_Private_Constants PCCARD Private Constants + * @{ + */ + +#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFF +#define PCCARD_TIMEOUT_SECTOR (uint32_t)0x0000FFFF +#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000 + +#define PCCARD_STATUS_OK (uint8_t)0x58 +#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions + * @{ + */ + +/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### PCCARD Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize + the PCCARD memory + +@endverbatim + * @{ + */ + /** + * @brief DMA configuration + * @param EDMA_CHx: pointer to a EDMA_Channel_Type structure + * @param cpar_src: the Memory 1 addr + * @param cmar_dst: the Memory 2 addr + * @param cndtr: transfer size + * @param Transfer_Type: + * @arg Read_Transfer: from Memory 1 to Memory 2 + * @arg Write_Transfer: from Memory 2 to Memory 1 + * @param Transfer_Width: BYTE or HALFWORD + * @retval None + */ +void MYDMA_Config(edma_stream_type* DMAy_Streamx, uint32_t cpar_src, uint32_t cmar_dst, uint32_t cndtr, uint8_t Transfer_Type, uint8_t Transfer_Width) +{ + edma_init_type EDMA_InitStruct; + crm_periph_clock_enable(CRM_EDMA_PERIPH_CLOCK, TRUE); + + edma_reset(DMAy_Streamx); + + if(Transfer_Type == Read_Transfer) + { + EDMA_InitStruct.peripheral_inc_enable = FALSE; + EDMA_InitStruct.memory_inc_enable = TRUE; + } + else + { + EDMA_InitStruct.peripheral_inc_enable = TRUE; + EDMA_InitStruct.memory_inc_enable = FALSE; + } + + if(Transfer_Width == Enable_8_bit_Transfer) + { + EDMA_InitStruct.peripheral_data_width = EDMA_PERIPHERAL_DATA_WIDTH_BYTE; + EDMA_InitStruct.memory_data_width = EDMA_MEMORY_DATA_WIDTH_BYTE; + } + else + { + EDMA_InitStruct.peripheral_data_width = EDMA_PERIPHERAL_DATA_WIDTH_HALFWORD; + EDMA_InitStruct.memory_data_width = EDMA_MEMORY_DATA_WIDTH_HALFWORD; + } + + EDMA_InitStruct.direction = EDMA_DIR_MEMORY_TO_MEMORY; + EDMA_InitStruct.buffer_size = cndtr; + EDMA_InitStruct.peripheral_base_addr = cpar_src; + + EDMA_InitStruct.peripheral_burst_mode = EDMA_PERIPHERAL_SINGLE; + EDMA_InitStruct.memory0_base_addr = cmar_dst; + + EDMA_InitStruct.memory_burst_mode = EDMA_MEMORY_SINGLE; + EDMA_InitStruct.loop_mode_enable = FALSE; + EDMA_InitStruct.fifo_mode_enable = TRUE; + EDMA_InitStruct.fifo_threshold = EDMA_FIFO_THRESHOLD_FULL; + EDMA_InitStruct.priority = EDMA_PRIORITY_MEDIUM; + edma_init(DMAy_Streamx,&EDMA_InitStruct); + + + edma_stream_enable(DMAy_Streamx, TRUE); +} +/** + * @brief XMC InitCtrl + * @param Device: pointer to a XMC_Bank4_Type structure + * @param Init: pointer to a XMC_PCCARDInitType structure + * @param Set_reg_8_bit: choose 8/16bit + * @retval STATUS_OK or STATUS_ERROR + */ +StatusType XMC_PCCARD_InitCtrl(xmc_bank4_type *Device, xmc_pccard_init_type *Init, uint8_t Set_reg_8_bit) +{ + if(Set_reg_8_bit == 1) + { + Device->bk4ctrl_bit.extmdbw = XMC_MEM_WIDTH_8; + } + else + { + Device->bk4ctrl_bit.extmdbw = XMC_MEM_WIDTH_16; + } + + Device->bk4ctrl_bit.tar = Init->delay_time_ar; + Device->bk4ctrl_bit.tcr = Init->delay_time_cr; + + return STATUS_OK; + +} +/** + * @brief XMC Enable Wait Feature + * @param Device: pointer to a XMC_Bank4_Type structure + * @param Init: pointer to a XMC_PCCARDInitType structure + * @retval STATUS_OK or STATUS_ERROR + */ +StatusType XMC_Enable_Wait_Feature(xmc_bank4_type *Device, xmc_pccard_init_type *Init) +{ + + Device->bk4ctrl_bit.nwen = Init->enable_wait; + + return STATUS_OK; +} +/** + * @brief Set 16bit_Feature + * @param Device: pointer to a XMC_Bank4_Type structure + * @param Init: pointer to a XMC_PCCARDInitType structure + * @param Set_reg_8_bit: choose 8/16bit + * @retval HAL status + */ +StatusType XMC_Enable_16bit_Feature(xmc_bank4_type *Device, xmc_pccard_init_type *Init, uint8_t Set_reg_8_bit) +{ + if(Set_reg_8_bit == 1) + { + Device->bk4ctrl_bit.extmdbw = XMC_MEM_WIDTH_8; + } + else + { + Device->bk4ctrl_bit.extmdbw = XMC_MEM_WIDTH_16; + } + + return STATUS_OK; +} +/** + * @brief Init CommonSpace Timing + * @param Device: pointer to a XMC_Bank4_Type structure + * @param Timing: pointer to a Common space timing structure + * @retval HAL status + */ +StatusType XMC_PCCARD_InitCommonSpaceTiming(xmc_bank4_type *Device, xmc_nand_pccard_timinginit_type *Timing) +{ + Device->bk4tmgmem_bit.cmdhizt = Timing->mem_hiz_time; + Device->bk4tmgmem_bit.cmht = Timing->mem_hold_time; + Device->bk4tmgmem_bit.cmst = Timing->mem_setup_time; + Device->bk4tmgmem_bit.cmwt = Timing->mem_waite_time; + + return STATUS_OK; +} +/** + * @brief Init AttributeSpace Timing + * @param Device: pointer to a XMC_Bank4_Type structure + * @param Timing: pointer to a Attribute space timing structure + * @retval HAL status + */ +StatusType XMC_PCCARD_InitAttributeSpaceTiming(xmc_bank4_type *Device, xmc_nand_pccard_timinginit_type *Timing) +{ + Device->bk4tmgatt_bit.amdhizt = Timing->mem_hiz_time; + Device->bk4tmgatt_bit.amht = Timing->mem_hold_time; + Device->bk4tmgatt_bit.amst = Timing->mem_setup_time; + Device->bk4tmgatt_bit.amwt = Timing->mem_waite_time; + return STATUS_OK; +} +/*****************************************************************/ +/** + * @brief Init IOSpace Timing + * @param Device: pointer to a XMC_Bank4_Type structure + * @param Timing: pointer to a IO space timing structure + * @retval HAL status + */ +StatusType XMC_PCCARD_InitIOSpaceTiming(xmc_bank4_type *Device, xmc_nand_pccard_timinginit_type *Timing) +{ + + Device->bk4tmgio_bit.iohizt = Timing->mem_hiz_time; + Device->bk4tmgio_bit.ioht = Timing->mem_hold_time; + Device->bk4tmgio_bit.iost = Timing->mem_setup_time; + Device->bk4tmgio_bit.iowt = Timing->mem_waite_time; + + return STATUS_OK; +} +/*****************************************************************/ +/** + * @brief Perform the PCCARD memory Initialization sequence + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param ComSpaceTiming: Common space timing structure + * @param AttSpaceTiming: Attribute space timing structure + * @param IOSpaceTiming: IO space timing structure + * @retval HAL status + */ +StatusType PCCARD_Init(PCCARD_HandleType *hpccard, xmc_nand_pccard_timinginit_type *ComSpaceTiming, xmc_nand_pccard_timinginit_type *AttSpaceTiming, xmc_nand_pccard_timinginit_type *IOSpaceTiming) +{ + gpio_init_type GPIO_InitStructure; + uint8_t Set_reg_8_bit; + + /* Check the PCCARD controller state */ + if(hpccard == NULL) + { + return STATUS_ERROR; + } + + if(hpccard->CF.Enable_8_bit_mode == TRUE) + Set_reg_8_bit = 1; + else + Set_reg_8_bit = 0; + + + if(hpccard->State == PCCARD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpccard->Lock = UNLOCKED; + + } + + /* Initialize the PCCARD state */ + hpccard->State = PCCARD_STATE_BUSY; + + + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK,TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK,TRUE); + crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK,TRUE); + crm_periph_clock_enable(CRM_GPIOE_PERIPH_CLOCK,TRUE); + crm_periph_clock_enable(CRM_GPIOF_PERIPH_CLOCK,TRUE); + crm_periph_clock_enable(CRM_GPIOG_PERIPH_CLOCK,TRUE); + /* address line:PF0 PF1 PF2 PF3 PF4 PF5 PF12 PF13 PF14 PF15 PD5 PG1 PG2 PG3 PG4 PG5 PD11 PD12 PD13 PE3 PE4 PE5 PE6 PE2 PG13 PG14 */ + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE0, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE1, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE2, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE3, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE4, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE5, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE12, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE13, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE14, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE15, GPIO_MUX_12); + + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_0|GPIO_PINS_1|GPIO_PINS_2|GPIO_PINS_3|GPIO_PINS_4|GPIO_PINS_5|GPIO_PINS_12|GPIO_PINS_13|GPIO_PINS_14|GPIO_PINS_15; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOF, &GPIO_InitStructure); + + gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE5, GPIO_MUX_10); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_11|GPIO_PINS_12|GPIO_PINS_13|GPIO_PINS_5; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOD, &GPIO_InitStructure); + + /* data line: PB14 PC6 PC11 PC12 PE7 PA3 PA4 PA5 PE11 PE12 PE13 PE14 PE15 PB12 PD9 PD10 */ + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE14, GPIO_MUX_14); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE12, GPIO_MUX_14); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_14|GPIO_PINS_12; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOB, &GPIO_InitStructure); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE6, GPIO_MUX_14); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE11, GPIO_MUX_14); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE12, GPIO_MUX_14); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_6|GPIO_PINS_11|GPIO_PINS_12; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOC, &GPIO_InitStructure); + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE3, GPIO_MUX_14); + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE4, GPIO_MUX_14); + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE5, GPIO_MUX_14); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_2|GPIO_PINS_3|GPIO_PINS_4|GPIO_PINS_5; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOA, &GPIO_InitStructure); + gpio_pin_mux_config(GPIOE, GPIO_PINS_SOURCE7, GPIO_MUX_12); + gpio_pin_mux_config(GPIOE, GPIO_PINS_SOURCE11, GPIO_MUX_12); + gpio_pin_mux_config(GPIOE, GPIO_PINS_SOURCE12, GPIO_MUX_12); + gpio_pin_mux_config(GPIOE, GPIO_PINS_SOURCE13, GPIO_MUX_12); + gpio_pin_mux_config(GPIOE, GPIO_PINS_SOURCE14, GPIO_MUX_12); + gpio_pin_mux_config(GPIOE, GPIO_PINS_SOURCE15, GPIO_MUX_12); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_11|GPIO_PINS_12|GPIO_PINS_13|GPIO_PINS_14|GPIO_PINS_15|GPIO_PINS_7; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOE, &GPIO_InitStructure); + gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE9, GPIO_MUX_12); + gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE10, GPIO_MUX_12); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_9|GPIO_PINS_10; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOD, &GPIO_InitStructure); + /* XMC_NCE4_1/XMC_NCE4_2:PG10/PG11 XMC_NOE:PD4 XMC_NWE:PC2 XMC_NBL0:PE0 XMC_NBL1:PE1 XMC_NADV:PB7 XMC_NWAIT:PD6 */ + /* XMC_NIORD:PF6 XMC_NIOWR:PF8 XMC_NREG:PF7 XMC_INTR:PF10 XMC_CD:PF9 */ + gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE4, GPIO_MUX_12); + gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE6, GPIO_MUX_12); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_4|GPIO_PINS_6; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_UP; + gpio_init(GPIOD, &GPIO_InitStructure); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE2, GPIO_MUX_14); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_2; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_UP; + gpio_init(GPIOC, &GPIO_InitStructure); + + gpio_pin_mux_config(GPIOG, GPIO_PINS_SOURCE10, GPIO_MUX_12); + gpio_pin_mux_config(GPIOG, GPIO_PINS_SOURCE11, GPIO_MUX_12); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_10|GPIO_PINS_11; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOG, &GPIO_InitStructure); + + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE9, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE6, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE7, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE8, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE10, GPIO_MUX_12); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_9|GPIO_PINS_6|GPIO_PINS_7|GPIO_PINS_8|GPIO_PINS_10; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOF, &GPIO_InitStructure); + + /* Initialize PCCARD control Interface */ + XMC_PCCARD_InitCtrl(hpccard->Instance, &(hpccard->Init), Set_reg_8_bit); + + /* Init PCCARD common space timing Interface */ + XMC_PCCARD_InitCommonSpaceTiming(hpccard->Instance, ComSpaceTiming); + + /* Init PCCARD attribute space timing Interface */ + XMC_PCCARD_InitAttributeSpaceTiming(hpccard->Instance, AttSpaceTiming); + + /* Init PCCARD IO space timing Interface */ + XMC_PCCARD_InitIOSpaceTiming(hpccard->Instance, IOSpaceTiming); + + /* Enable the PCCARD device */ + xmc_pccard_enable(TRUE); + + /* Update the PCCARD state */ + hpccard->State = PCCARD_STATE_READY; + + return STATUS_OK; + +} +/** + * @brief Enable Wait Feature + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval STATUS_OK or STATUS_ERROR + */ +StatusType Enable_Wait_Feature(PCCARD_HandleType *hpccard) +{ + /* Check the PCCARD controller state */ + if(hpccard == NULL) + { + return STATUS_ERROR; + } + + if(hpccard->State == PCCARD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpccard->Lock = UNLOCKED; + } + + /* Initialize the PCCARD state */ + hpccard->State = PCCARD_STATE_BUSY; + + XMC_Enable_Wait_Feature(hpccard->Instance, &(hpccard->Init)); + + hpccard->State = PCCARD_STATE_READY; + + return STATUS_OK; +} + +/** + * @brief Perform the PCCARD memory De-initialization sequence + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval HAL status + */ +StatusType PCCARD_DeInit(PCCARD_HandleType *hpccard) +{ + + /* Configure the PCCARD registers with their reset values */ + xmc_pccard_reset(); + + /* Update the PCCARD controller state */ + hpccard->State = PCCARD_STATE_RESET; + return STATUS_OK; +} + + +/** + * @} + */ + +/** @defgroup PCCARD_Exported_Functions_Group2 Input Output and memory functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### PCCARD Input Output and memory functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the PCCARD memory + +@endverbatim + * @{ + */ +/** + * @brief Identify + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Identify(PCCARD_HandleType *hpccard) +{ + uint8_t Reg; + + Reg = hpccard->CF.CFAddr.Drv; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + if(!CF_SendCommand(hpccard, ATA_IDENTIFY_DRIVE_CMD)) + { + return FALSE; + } + + return TRUE; +} + + +/** + * @brief Read Compact Flash's ID. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param CompactFlash_ID: Compact flash ID structure. + * @retval HAL status + * + */ +BOOL PCCARD_Read_ID(PCCARD_HandleType *hpccard) +{ + uint8_t CardInfo[PCCARD_SECTOR_SIZE * sizeof(uint8_t)] = {0}; + + memset(CardInfo, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + PCCARD_Read_STATUS_REG(hpccard); + + if(PCCARD_Identify(hpccard)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + /* Read CF ID bytes */ + + Read_Sector(hpccard, CardInfo, PCCARD_SECTOR_SIZE); + + break; + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + printf("\r\nCommand Pass, but ERR bit is high"); + printf("\r\nCF Status Reg=%#x", PCCARD_Read_STATUS_REG(hpccard)); + printf("\r\nCF Error Reg=%#x", PCCARD_Read_ERROR_REG(hpccard)); + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + printf("\r\nSend Command Failed"); + printf("\r\nCF Status Reg=%#x", PCCARD_Read_STATUS_REG(hpccard)); + printf("\r\nCF Error Reg=%#x", PCCARD_Read_ERROR_REG(hpccard)); + return FALSE; + } + } + } + +#if 1 + + printf("\r\n===============================================================\n"); + printf("\r\n\nIdentify Drive Information : "); + printf("\r\n%s%#x", "Signature : ", ((uint16_t)CardInfo[0] | (uint16_t)CardInfo[1] << 8)); + printf("\r\n%s%u", "Default number of cylinders : ", ((uint16_t)CardInfo[2] | (uint16_t)CardInfo[3] << 8)); + printf("\r\n%s%u", "Default number of heads : ", ((uint16_t)CardInfo[6] | (uint16_t)CardInfo[7] << 8)); + printf("\r\n%s%u", "Number of unformatted bytes per tract : ", ((uint16_t)CardInfo[8] | (uint16_t)CardInfo[9] << 8)); + printf("\r\n%s%u", "Number of unformatted bytes per sector : ", ((uint16_t)CardInfo[10] | (uint16_t)CardInfo[11] << 8)); + printf("\r\n%s%u", "Default number of sectors per track : ", ((uint16_t)CardInfo[12] | (uint16_t)CardInfo[13] << 8)); + printf("\r\n%s%u", "Number of sectors per card : ", (uint32_t)((uint16_t)CardInfo[16] | (uint16_t)CardInfo[17] << 8) | ((uint32_t)((uint16_t)CardInfo[14] | (uint16_t)CardInfo[15] << 8) << 16)); + printf("\r\n%s%u", "Vendor Unique : ", ((uint16_t)CardInfo[18] | (uint16_t)CardInfo[19] << 8)); + printf("\r\n%s%#x", "Buffer type : ", ((uint16_t)CardInfo[40] | (uint16_t)CardInfo[41] << 8)); + printf("\r\n%s%u", "Buffer size in 512 byte increments : ", ((uint16_t)CardInfo[42] | (uint16_t)CardInfo[43] << 8)); + printf("\r\n%s%u", "#of ECC bytes passed on Read/Write Long Commands : ", ((uint16_t)CardInfo[44] | (uint16_t)CardInfo[45] << 8)); + printf("\r\n%s%u", "Maximum number of sectors on Read/Write Multiple command : ", ((uint16_t)CardInfo[94] | (uint16_t)CardInfo[95] << 8)); + printf("\r\n%s%u", "Double Word not supported : ", ((uint16_t)CardInfo[96] | (uint16_t)CardInfo[97] << 8)); + printf("\r\n%s%u", "Capabilities : ", ((uint16_t)CardInfo[98] | (uint16_t)CardInfo[99] << 8)); + printf("\r\n%s%u", "PIO data transfer cycle timing mode : ", ((uint16_t)CardInfo[102] | (uint16_t)CardInfo[103] << 8)); + printf("\r\n%s%u", "DMA data transfer cycle timing mode: ", ((uint16_t)CardInfo[104] | (uint16_t)CardInfo[105] << 8)); + printf("\r\n%s%u", "Translation parameters are valid : ", ((uint16_t)CardInfo[106] | (uint16_t)CardInfo[107] << 8)); + printf("\r\n%s%u", "Current numbers of cylinders : ", ((uint16_t)CardInfo[108] | (uint16_t)CardInfo[109] << 8)); + printf("\r\n%s%u", "Current numbers of heads : ", ((uint16_t)CardInfo[110] | (uint16_t)CardInfo[111] << 8)); + printf("\r\n%s%u", "Current sectors per track : ", ((uint16_t)CardInfo[112] | (uint16_t)CardInfo[113] << 8)); + printf("\r\n%s%u", "Current capacity in sectors : ", (uint32_t)((uint16_t)CardInfo[116] | (uint16_t)CardInfo[117] << 8) | ((uint32_t)((uint16_t)CardInfo[114] | (uint16_t)CardInfo[115] << 8) << 16)); + printf("\r\n%s%#x", "Multiple sector setting : ", ((uint16_t)CardInfo[118] | (uint16_t)CardInfo[119] << 8)); + printf("\r\n%s%u", "Total number of sectors addressable in LBA Mode : ", (uint32_t)((uint16_t)CardInfo[120] | (uint16_t)CardInfo[121] << 8) | ((uint32_t)((uint16_t)CardInfo[122] | (uint16_t)CardInfo[123] << 8) << 16)); + printf("\r\n%s%#x", "Security status : ", ((uint16_t)CardInfo[256] | (uint16_t)CardInfo[257] << 8)); + printf("\r\n%s%#x", "Power requirement description : ", ((uint16_t)CardInfo[320] | (uint16_t)CardInfo[321] << 8)); + printf("\r\n==============================================================="); + +#endif + + /* signature of CF storage */ + if(((uint16_t)CardInfo[0] | (uint16_t)CardInfo[1] << 8) == 0x848A) + { + hpccard->CF.CFCardInfo.Default_Cylinder = ((uint16_t)CardInfo[2] | (uint16_t)CardInfo[3] << 8); + hpccard->CF.CFCardInfo.Default_Head = ((uint16_t)CardInfo[6] | (uint16_t)CardInfo[7] << 8); + hpccard->CF.CFCardInfo.Default_Sector = ((uint16_t)CardInfo[12] | (uint16_t)CardInfo[13] << 8); + hpccard->CF.CFCardInfo.Current_Cylinder = ((uint16_t)CardInfo[108] | (uint16_t)CardInfo[109] << 8); + hpccard->CF.CFCardInfo.Current_Head = ((uint16_t)CardInfo[110] | (uint16_t)CardInfo[111] << 8); + hpccard->CF.CFCardInfo.Current_Sector = ((uint16_t)CardInfo[112] | (uint16_t)CardInfo[113] << 8); + + hpccard->CF.CFCardInfo.Total_Sector = (uint32_t)((uint16_t)CardInfo[16] | (uint16_t)CardInfo[17] << 8) | ((uint32_t)((uint16_t)CardInfo[14] | (uint16_t)CardInfo[15] << 8) << 16); + hpccard->CF.CFCardInfo.Total_LBA_Sector = (uint32_t)((uint16_t)CardInfo[120] | (uint16_t)CardInfo[121] << 8) | ((uint32_t)((uint16_t)CardInfo[122] | (uint16_t)CardInfo[123] << 8) << 16); + hpccard->CF.CFCardInfo.Max_Mutiple_Sector = ((uint16_t)CardInfo[94] | (uint16_t)CardInfo[95] << 8); + hpccard->CF.CFCardInfo.Mutiple_Sector_Setting = ((uint16_t)CardInfo[118] | (uint16_t)CardInfo[119] << 8); + } + else + { + + return FALSE; + } + + return TRUE; +} + +/** + * @brief Read sector from PCCARD memory + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to destination read buffer + * @param Sector_Address: Sector address to read + * @retval HAL status + */ +BOOL PCCARD_Read_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = (uint8_t)hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_READ_SECTOR_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + pBuffer = Read_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + printf("Error Code=%X\n", PCCARD_Read_STATUS_REG(hpccard)); + return FALSE; + } + } + } + } + + return TRUE; +} + + +/** + * @brief Write sector to PCCARD memory + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to source write buffer + * @param Sector_Address: Sector address to write + * @retval HAL status + */ +BOOL PCCARD_Write_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + // Set the parameters to write a sector // + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + //*(__IO uint16_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = hpccard->CF.CFAddr.Cylinder; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = (uint8_t)hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_WRITE_SECTOR_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + pBuffer = Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if (PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + printf("Error Code=%X\n", PCCARD_Read_STATUS_REG(hpccard)); + return FALSE; + } + } + } + } + + return TRUE; +} + + +/** + * @brief Erase sector from PCCARD memory + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Address: Sector address to erase + * @retval HAL status + */ +BOOL PCCARD_Erase_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint8_t Reg; + uint16_t Count = 0; + + while (Count < Sector_Count) + { + + Translate_CHSAddr(hpccard, Sector_Address, 0, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_ERASE_SECTOR_CMD)) + { + Count += hpccard->CF.CFAddr.Sector_Count; + Sector_Address += hpccard->CF.CFAddr.Sector_Count; + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief Diagnostic + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Diagnostic(PCCARD_HandleType *hpccard) +{ + uint8_t ERROR_REG; + + /* Set the parameters */ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_EXECUTE_DRIVE_DIAG_CMD)) + { + return FALSE; + } + + ERROR_REG = PCCARD_Read_ERROR_REG(hpccard); + + if((ERROR_REG == 0x01) || (ERROR_REG == 0x02) || (ERROR_REG == 0x03) || (ERROR_REG == 0x04) || (ERROR_REG == 0x05) || (ERROR_REG == 0x80)) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Check Power Mode + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Check_Power_Mode(PCCARD_HandleType *hpccard) +{ + uint8_t SECTOR_COUNT_REG; + /* set sector_count register 0x80, after check_power_mode */ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = 0x80; + /* the register will be change to 0x00 or 0xFF */ + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_CHECK_POWER_MODE_CMD)) + { + return FALSE; + } + + SECTOR_COUNT_REG = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT); + + if(SECTOR_COUNT_REG == 0xFF || SECTOR_COUNT_REG == 0x00) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Set idle + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Idle(PCCARD_HandleType *hpccard, uint32_t Sector_Count) +{ + uint8_t SECTOR_COUNT_REG; + + hpccard->CF.CFAddr.Sector_Count = Sector_Count; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_IDLE_CMD)) + { + return FALSE; + } + + + /* Check Power Mode */ + if(!PCCARD_Check_Power_Mode(hpccard)) + { + printf("Compact Flash Check Power Mode Failed \n"); + return FALSE; + } + + SECTOR_COUNT_REG = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT); + + if(SECTOR_COUNT_REG == 0xFF) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Idle immediate + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Idle_Immediate(PCCARD_HandleType *hpccard) +{ + uint8_t SECTOR_COUNT_REG; + /* set sector_count register 0x80, after check_power_mode */ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = 0x80; + /* the register will be change to 0x00 or 0xFF */ + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_IDLE_IMMEDIATE_CMD)) + { + return FALSE; + } + + /* Check Power Mode */ + if(!PCCARD_Check_Power_Mode(hpccard)) + { + printf("Compact Flash Check Power Mode Failed \n"); + return FALSE; + } + + SECTOR_COUNT_REG = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT); + + if(SECTOR_COUNT_REG == 0xFF) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Set sleep mode + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Set_Sleep_Mode(PCCARD_HandleType *hpccard) +{ + uint8_t SECTOR_COUNT_REG; + /* set sector_count register 0x80, after check_power_mode */ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = 0x80; + /* the register will be change to 0x00 or 0xFF */ + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_SET_SLEEP_MODE_CMD)) + { + return FALSE; + } + + /* Check Power Mode */ + if(!PCCARD_Check_Power_Mode(hpccard)) + { + printf("Compact Flash Check Power Mode Failed \n"); + return FALSE; + } + + SECTOR_COUNT_REG = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT); + + if(SECTOR_COUNT_REG == 0x00) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Set Standby + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Standby(PCCARD_HandleType *hpccard) +{ + uint8_t SECTOR_COUNT_REG; + /* set sector_count register 0x80, after check_power_mode */ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = 0x80; + /* the register will be change to 0x00 or 0xFF */ + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_STANDBY_CMD)) + { + return FALSE; + } + + /* Check Power Mode */ + if(!PCCARD_Check_Power_Mode(hpccard)) + { + printf("Compact Flash Check Power Mode Failed \n"); + return FALSE; + } + + SECTOR_COUNT_REG = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT); + + if(SECTOR_COUNT_REG == 0x00) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Standby Immediate + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Standby_Immediate(PCCARD_HandleType *hpccard) +{ + uint8_t SECTOR_COUNT_REG; + /* set sector_count register 0x80, after check_power_mode */ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = 0x80; + /* the register will be change to 0x00 or 0xFF */ + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_STANDBY_IMMEDIATE_CMD)) + { + return FALSE; + } + + /* Check Power Mode */ + if(!PCCARD_Check_Power_Mode(hpccard)) + { + printf("Compact Flash Check Power Mode Failed \n"); + return FALSE; + } + + SECTOR_COUNT_REG = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT); + + if(SECTOR_COUNT_REG == 0x00) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Reuqest Sense the pccard + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Reuqest_Sense(PCCARD_HandleType *hpccard) +{ + uint8_t Reg, ERROR_REG; + + Reg = hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(!CF_SendCommand(hpccard, ATA_REQUEST_SENSE_CMD)) + { + return FALSE; + } + + ERROR_REG = PCCARD_Read_ERROR_REG(hpccard); + + if((ERROR_REG == 0x2F) || (ERROR_REG == 0x21)) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Recalibrate the pccard + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Recalibrate(PCCARD_HandleType *hpccard) +{ + uint8_t Reg, ERROR_REG; + + Reg = hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(!CF_SendCommand(hpccard, ATA_RECALIBRATE_CMD)) + { + return FALSE; + } + + ERROR_REG = PCCARD_Read_ERROR_REG(hpccard); + + if((0x00 == ERROR_REG)) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Init drive para + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Count: the sector count + * @param Head_Count: the head count. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Init_Drive_Para(PCCARD_HandleType *hpccard, uint16_t Sector_Count, uint8_t Head_Count) +{ + uint8_t Reg; + + hpccard->CF.CFAddr.Head = (uint8_t)Head_Count; + hpccard->CF.CFAddr.Sector_Count = (uint8_t)Sector_Count; + + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(!CF_SendCommand(hpccard, ATA_INIT_DRIVE_PARA_CMD)) + { + return FALSE; + } + + return TRUE; +} +/** + * @brief seek pccard + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Head_Count: the head count. + * @param Cylinder_Count: the cylinder count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Seek(PCCARD_HandleType *hpccard, uint8_t Head_Count, uint16_t Cylinder_Count) +{ + uint8_t Reg, ERROR_REG; + + hpccard->CF.CFAddr.Head = (uint8_t)Head_Count; + hpccard->CF.CFAddr.Cylinder = (uint16_t)Cylinder_Count; + + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + + /* This command should return false */ + if(CF_SendCommand(hpccard, ATA_SEEK_CMD)) + { + return FALSE; + } + + ERROR_REG = PCCARD_Read_ERROR_REG(hpccard); + + if((ERROR_REG != 0x00)) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief format track + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Format_Track(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + /* Set the parameters to write a sector */ + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_FORMAT_TRACK_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + // Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if (PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief read Verify Sector + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Read_Verify_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint16_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_READ_VERIFY_SECTOR_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == DRQ_BIT) // DRQ_BIT should not be assert in this command + { + return FALSE; + } + else + { + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief write Verify + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Write_Verify(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + // Set the parameters to write a sector // + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_WRITE_VERIFY_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if (PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief set multiple mode + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Set_Multiple_Mode(PCCARD_HandleType *hpccard, uint32_t Sector_Count) +{ + hpccard->CF.CFAddr.Sector_Count = Sector_Count; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_SET_MULTIPLE_MODE_CMD)) + { + return FALSE; + } + + return TRUE; +} +/** + * @brief set features + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Count: the sector count + * @param Feature: Feature val + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Set_Features(PCCARD_HandleType *hpccard, uint32_t Sector_Count, uint8_t Feature) +{ + hpccard->CF.CFAddr.Sector_Count = Sector_Count; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_FEATURE_REG) = Feature; + + if(!CF_SendCommand(hpccard, ATA_SET_FEATURE_CMD)) + { + return FALSE; + } + + return TRUE; +} +/** + * @brief read buffer + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Read_Buffer(PCCARD_HandleType *hpccard, uint8_t *pBuffer) +{ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(CF_SendCommand(hpccard, ATA_READ_BUFFER_CMD)) + { + if (TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Read_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + + return TRUE; +} +/** + * @brief write buffer + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Write_Buffer(PCCARD_HandleType *hpccard, uint8_t *pBuffer) +{ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(CF_SendCommand(hpccard, ATA_WRITE_BUFFER_CMD)) + { + if (TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + + return TRUE; +} +/** + * @brief Translate sector + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Address: the sector addr + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Translate_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address) +{ + uint32_t Total_Cylinder; + uint8_t Reg; + + Total_Cylinder = (uint32_t)(hpccard->CF.CFCardInfo.Default_Head * hpccard->CF.CFCardInfo.Default_Sector); // The total sectors in one cylinder + + hpccard->CF.CFAddr.Cylinder = (uint16_t)(Sector_Address / Total_Cylinder); + hpccard->CF.CFAddr.Head = (uint8_t)((Sector_Address % Total_Cylinder) / hpccard->CF.CFCardInfo.Default_Sector); + hpccard->CF.CFAddr.Sector = (uint8_t)((Sector_Address % Total_Cylinder) % hpccard->CF.CFCardInfo.Default_Sector) + 1; + + /* Set the parameters to write a sector */ + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(!CF_SendCommand(hpccard, ATA_TRANSLATE_SECTOR_CMD)) + { + return FALSE; + } + + return TRUE; +} +/** + * @brief write sector WO_ERASE + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Write_Sector_WO_ERASE(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + /* Set the parameters to write a sector */ + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_WRITE_SECTOR_WO_ERASE_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if (PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief write Multiple + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Write_Multiple(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + /* Set the parameters to write a sector */ + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_WRITE_MULTIPLE_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if (PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief read Multiple + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Read_Multiple(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_READ_MULTIPLE_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Read_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief write Multiple WO_ERASE + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Write_Multiple_WO_ERASE(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + /* Set the parameters to write a sector */ + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_WRITE_MULTIPLE_WO_ERASE_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if (PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief read long sector + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Address: the sector addr + * @param pBuffer: pointer to the data buffer. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Read_Long_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint8_t *pBuffer) +{ + uint32_t index = 0, Total_Cylinder; + uint8_t Reg; + BOOL command_vaild = TRUE; + + Total_Cylinder = (uint32_t)(hpccard->CF.CFCardInfo.Default_Head * hpccard->CF.CFCardInfo.Default_Sector); // The total sectors in one cylinder + + hpccard->CF.CFAddr.Cylinder = (uint16_t)(Sector_Address / Total_Cylinder); + hpccard->CF.CFAddr.Head = (uint8_t)((Sector_Address % Total_Cylinder) / hpccard->CF.CFCardInfo.Default_Sector); + hpccard->CF.CFAddr.Sector = (uint8_t)((Sector_Address % Total_Cylinder) % hpccard->CF.CFCardInfo.Default_Sector) + 1; + hpccard->CF.CFAddr.Sector_Count = 1; // some CF storage card implement the read long sector command as read sector commend + // set sector count to 1, after read 512 byte data, if the DRQ_BIT still high, means the + // read long sector command work well, because it shoult return 516 byte data (ECC). + + + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_READ_LONG_SECTOR_CMD)) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Read_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + if(PCCARD_Read_STATUS_REG(hpccard) & DRQ_BIT) + { + for(index = 0; index < 4; index++) + { + *(uint8_t *)pBuffer++ = *(uint8_t *)(hpccard->CF.IOAddr); + } + } + else + { + command_vaild = FALSE; + } + + if(PCCARD_Read_STATUS_REG(hpccard) & DRQ_BIT) + { + command_vaild = FALSE; + } + + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + + if(command_vaild == TRUE) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief write long sector + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Address: the sector addr + * @param pBuffer: pointer to the data buffer. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Write_Long_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint8_t *pBuffer) +{ + uint32_t index = 0, Total_Cylinder; + uint8_t Reg; + BOOL command_vaild = TRUE; + + Total_Cylinder = (uint32_t)(hpccard->CF.CFCardInfo.Default_Head * hpccard->CF.CFCardInfo.Default_Sector); // The total sectors in one cylinder + + hpccard->CF.CFAddr.Cylinder = (uint16_t)(Sector_Address / Total_Cylinder); + hpccard->CF.CFAddr.Head = (uint8_t)((Sector_Address % Total_Cylinder) / hpccard->CF.CFCardInfo.Default_Sector); + hpccard->CF.CFAddr.Sector = (uint8_t)((Sector_Address % Total_Cylinder) % hpccard->CF.CFCardInfo.Default_Sector) + 1; + hpccard->CF.CFAddr.Sector_Count = 1; // some CF storage card implement the read long sector command as read sector commend + // set sector count to 1, after read 512 byte data, if the DRQ_BIT still high, means the + // read long sector command is work well, because it shoult return 516 byte data (ECC). + + + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_WRITE_LONG_SECTOR_CMD)) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + if(PCCARD_Read_STATUS_REG(hpccard) & DRQ_BIT) + { + for(index = 0; index < 4; index++) + { + *(uint8_t *)(hpccard->CF.IOAddr) = *(uint8_t *)pBuffer++; + } + } + else + { + command_vaild = FALSE; + } + + if(PCCARD_Read_STATUS_REG(hpccard) & DRQ_BIT) + { + command_vaild = FALSE; + } + + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + + if(command_vaild == TRUE) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief read sector + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Transfer_Size: the data length. + * @retval pointer to the data buffer after read. + */ +uint8_t *Read_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Transfer_Size) +{ + uint32_t index = 0; + + XMC_Enable_16bit_Feature(hpccard->Instance, &(hpccard->Init), hpccard->CF.Enable_8_bit_mode); + + if(hpccard->CF.DMAEnable == TRUE) + { + if(hpccard->CF.Enable_8_bit_mode) + { + MYDMA_Config(EDMA_STREAM1, (uint32_t)hpccard->CF.IOAddr, (uint32_t)pBuffer, Transfer_Size, Read_Transfer, Enable_8_bit_Transfer); + } + else + { + MYDMA_Config(EDMA_STREAM1, (uint32_t)hpccard->CF.IOAddr, (uint32_t)pBuffer, (Transfer_Size / 2), Read_Transfer, Enable_16_bit_Transfer); + } + + while(1) + { + if(edma_flag_get(EDMA_FDT1_FLAG) != RESET) + { + edma_flag_clear(EDMA_FDT1_FLAG); + break; + } + } + + pBuffer += 512; + } + else + { + if(hpccard->CF.Enable_8_bit_mode) + { + for(; index < (Transfer_Size) ; index++) + { + *(uint8_t *)pBuffer++ = *(uint8_t *)(hpccard->CF.IOAddr); + } + } + else + { + for(; index < (Transfer_Size / 2); index++) + { + *(uint16_t *)pBuffer = *(uint16_t *)(hpccard->CF.IOAddr); + /* offset to next 16 bit */ + pBuffer += 2; + } + } + } + + XMC_Enable_16bit_Feature(hpccard->Instance, &(hpccard->Init), 1); + return pBuffer; +} +/** + * @brief write sector + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Transfer_Size: the data length. + * @retval pointer to the data buffer after write. + */ +uint8_t *Write_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Transfer_Size) +{ + uint32_t index = 0; + + XMC_Enable_16bit_Feature(hpccard->Instance, &(hpccard->Init), hpccard->CF.Enable_8_bit_mode); + + if(hpccard->CF.DMAEnable == TRUE) + { + if(hpccard->CF.Enable_8_bit_mode) + { + MYDMA_Config(EDMA_STREAM1, (uint32_t)pBuffer, (uint32_t)hpccard->CF.IOAddr, Transfer_Size, Write_Transfer, Enable_8_bit_Transfer); + } + else + { + MYDMA_Config(EDMA_STREAM1, (uint32_t)pBuffer, (uint32_t)hpccard->CF.IOAddr, (Transfer_Size / 2), Write_Transfer, Enable_16_bit_Transfer); + } + + while(1) + { + if(edma_flag_get(EDMA_FDT1_FLAG) != RESET) + { + edma_flag_clear(EDMA_FDT1_FLAG); + break; + } + } + + pBuffer += 512; + } + else + { + if(hpccard->CF.Enable_8_bit_mode) + { + for(; index < (Transfer_Size); index++) + { + *(uint8_t *)(hpccard->CF.IOAddr) = *(uint8_t *)pBuffer++; + } + } + else + { + for(; index < (Transfer_Size / 2); index++) + { + *(uint16_t *)(hpccard->CF.IOAddr) = *(uint16_t *)pBuffer; + /* offset to next 16 bit */ + pBuffer += 2; // offset to next 16 bit + } + } + } + + XMC_Enable_16bit_Feature(hpccard->Instance, &(hpccard->Init), 1); + return pBuffer; +} + +/** + * @brief Reset the PCCARD memory + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval HAL status + */ +BOOL PCCARD_Reset(PCCARD_HandleType *hpccard) +{ + /* Provide an SW reset and Read and verify the: + - CF Configuration Option Register at address 0x98000200 --> 0x80 + - Card Configuration and Status Register at address 0x98000202 --> 0x00 + - Pin Replacement Register at address 0x98000204 --> 0x0C + - Socket and Copy Register at address 0x98000206 --> 0x00 + */ + + uint8_t config_option_reg; + + /* Set up the Reset bit in config option register */ + *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | CONFIG_OPTION_REG) = 0x80; + delay_ms(100); + /* Clear the Reset bit in config option register */ + *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | CONFIG_OPTION_REG) = 0x00; + delay_ms(100); + /* Set the PC card I/O configurations */ + *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | CONFIG_OPTION_REG) = hpccard->CF.Protocol; + delay_ms(100); + + config_option_reg = *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | CONFIG_OPTION_REG); + + if(config_option_reg == hpccard->CF.Protocol) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + * Translate_CHSAddr: + * translate DISK sector number to C.H.S address. + * input : CFCard + * Start (Start sector number) + * Sector_Count (sector count which read from CF card) + * Sector_Limit (maximum sector number) + * output : None + */ +void Translate_CHSAddr(PCCARD_HandleType *hpccard, uint32_t Start, uint16_t Sector_Count, uint16_t Sector_Limit) +{ + uint32_t Total_Cylinder; + uint16_t Prev_Count; + + Prev_Count = (Sector_Limit / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector; + + Total_Cylinder = (uint32_t)(hpccard->CF.CFCardInfo.Default_Head * hpccard->CF.CFCardInfo.Default_Sector); // The total sectors in one cylinder + + hpccard->CF.CFAddr.Cylinder = (uint16_t)(Start / Total_Cylinder); + hpccard->CF.CFAddr.Head = (uint8_t)((Start % Total_Cylinder) / hpccard->CF.CFCardInfo.Default_Sector); + hpccard->CF.CFAddr.Sector = (uint8_t)((Start % Total_Cylinder) % hpccard->CF.CFCardInfo.Default_Sector) + 1; + + if ((Prev_Count <= Sector_Count) && (Sector_Count <= Sector_Limit)) + { + hpccard->CF.CFAddr.Sector_Count = (uint8_t)(Sector_Limit % hpccard->CF.CFCardInfo.Default_Sector); + } + else + { + hpccard->CF.CFAddr.Sector_Count = (uint8_t)hpccard->CF.CFCardInfo.Default_Sector; + } +} + +/** + * @brief Read CIS Information. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL ReadCFCardCISInformation(PCCARD_HandleType *hpccard) +{ + uint8_t CIS_1, CIS_2, CIS_3; + + CIS_1 = *(uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | 0x0); + CIS_2 = *(uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | 0x2); + CIS_3 = *(uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | 0x4); + + if(CIS_1 == 0x1 && CIS_2 == 0x4 && CIS_3 == 0xdf) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + * @brief Send command. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Cmd: the command value + * @retval TRUE or FALSE. + */ +BOOL CF_SendCommand(PCCARD_HandleType *hpccard, uint8_t Cmd) +{ + uint8_t Reg; + + do + { + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_STATUS_CMD) = Cmd; + + while(!TaskFileRegIsValid(hpccard)) ; + + Reg = PCCARD_Read_STATUS_REG(hpccard); + + if ((Reg & ERR_BIT) != 0) + { + return FALSE; + } + } + while((Reg & RDY_BIT) == 0); + + return TRUE; +} +/** + * @brief Check the PCCARD TaskFileReg valid. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL TaskFileRegIsValid(PCCARD_HandleType *hpccard) +{ + uint8_t status = 0; + + status = PCCARD_Read_STATUS_REG(hpccard); + + if(status & BUSY_BIT) + { + return FALSE; + } + + return TRUE; +} +/** + * @brief Check the PCCARD info valid. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Count: sector count + * @param Head_Count:head count + * @retval TRUE or FALSE. + */ +BOOL Vaild_Init_Drive_Para(PCCARD_HandleType *hpccard, uint16_t Sector_Count, uint8_t Head_Count) +{ + uint8_t CardInfo[PCCARD_SECTOR_SIZE * sizeof(uint8_t)] = {0}; + + memset(CardInfo, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(PCCARD_Identify(hpccard)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Read_Sector(hpccard, CardInfo, PCCARD_SECTOR_SIZE); + break; + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + printf("\r\nCommand Pass, but ERR bit is high"); + printf("\r\nCF Status Reg=%#x", PCCARD_Read_STATUS_REG(hpccard)); + printf("\r\nCF Error Reg=%#x", PCCARD_Read_ERROR_REG(hpccard)); + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + printf("\r\nSend Command Failed"); + printf("\r\nCF Status Reg=%#x", PCCARD_Read_STATUS_REG(hpccard)); + printf("\r\nCF Error Reg=%#x", PCCARD_Read_ERROR_REG(hpccard)); + return FALSE; + } + } + } + + if (((uint16_t)CardInfo[0] | (uint16_t)CardInfo[1] << 8) == 0x848A && ((uint16_t)CardInfo[110] | \ + (uint16_t)CardInfo[111] << 8) == Head_Count && ((uint16_t)CardInfo[112] | (uint16_t)CardInfo[113] << 8) == Sector_Count ) + { + return TRUE; + } + else + { + return FALSE; + } + +} +/** + * @brief printf the verification result. + * @param result: pointer to a verification_result structure that contains + * various kinds of verification. + * @retval None. + */ +void show_verification_result(verification_result_struct *result) +{ + printf("\r\n"); + printf("\r\n----------------------------------------------------------------------"); + printf("\r\n%s %-6s ", "ATTRIBUTE_RW_PASS ", ((result->ATTRIBUTE_RW_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n%s %-6s ", "READ_ATTRIBUTE_CIS ", ((result->CIS_READ_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n%s %-6s ", "IDENTIFY_DRIVE ", ((result->ATA_IDENTIFY_DRIVE_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n%s %-6s ", "EXECUTE_DRIVE_DIAG ", ((result->ATA_EXECUTE_DRIVE_DIAG_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n%s %-6s ", "WRITE_SECTOR ", ((result->ATA_WRITE_SECTOR_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n%s %-6s ", "READ_SECTOR ", ((result->ATA_READ_SECTOR_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n%s %-6s ", "ACESS_25_SECTORS ", ((result->ACESS_25_SECTORS_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n----------------------------------------------------------------------"); + printf("\r\n\r\n"); +} + + +/** + * @brief This function handles PCCARD device interrupt request. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval HAL status + */ +void PCCARD_IRQHandler(PCCARD_HandleType *hpccard) +{ +} + + +/** + * @} + */ + +/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### PCCARD Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the PCCARD controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief return the PCCARD controller state + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval HAL state + */ +PCCARD_StateType PCCARD_GetState(PCCARD_HandleType *hpccard) +{ + return hpccard->State; +} +/** + * @brief Get the PCCARD error reg value. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval reg: error reg value. + */ +uint8_t PCCARD_Read_ERROR_REG(PCCARD_HandleType *hpccard) +{ + uint8_t Reg = 0; + + /* Read ERROR Reg operation */ + Reg = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_ERROR_REG); + CF_print(ERR_REG_INFO, ("\r\nCF card ERROR Register value is %#x", Reg)); + return Reg; +} +/** + * @brief Get the PCCARD status reg value. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval reg: status reg value. + */ +uint8_t PCCARD_Read_STATUS_REG(PCCARD_HandleType *hpccard) +{ + uint8_t Reg = 0; + + /* Read STATUS Reg operation */ + Reg = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_STATUS_CMD); + CF_print(STS_REG_INFO, ("\r\nCF card STATUS Register value is %#x", Reg)); + + return Reg; +} + + +void XMC_IRQHandler(void) +{ + __nop(); +} + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + + + + + + + + + + + + diff --git a/project/at_start_f435/examples/xmc/pc_card/pc_card/cf.h b/project/at_start_f435/examples/xmc/pc_card/pc_card/cf.h new file mode 100644 index 00000000..d2cacb99 --- /dev/null +++ b/project/at_start_f435/examples/xmc/pc_card/pc_card/cf.h @@ -0,0 +1,491 @@ +/** + ****************************************************************************** + * @file cf.h + * @brief header file for the cf configuration. + ****************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ +#ifndef __CF_H +#define __CF_H + +/* Includes ------------------------------------------------------------------*/ +#include "stdint.h" +#include "at32f435_437.h" +/** @addtogroup AT32F435_periph_examples + * @{ + */ + +/** @addtogroup XMC_CF_CARD + * @{ + */ +#ifdef __cplusplus +extern "C" { +#endif + + + /* Exported typedef ----------------------------------------------------------*/ + /** @defgroup PCCARD_Exported_Constant PCCARD Exported Constant + * @{ + */ +#define FALSE 0 +#define TRUE 1 +#define XMC_BASE ((uint32_t)0xA8000000) /*!< XMC base address */ +#define XMC_BANK4_ (XMC_BASE + 0x0000000) /*!< XMC Bank4 base address */ +#define PCCARD_DEVICE_ADDRESS XMC_BANK4_ /* 0x9000 0000 */ +#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */ +#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(XMC_BANK4_ + 0x4000000)) /* Attribute space size to @0x9BFF FFFF */ +#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(XMC_BANK4_ + 0x6000000)) /* IO space size to @0x9FFF FFFF */ + +// In XMC document page 545/1128, the XMC is not supported True IDE mode. // +#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(XMC_BANK4_ + PCCARD_IO_SPACE_ADDRESS + 0x1F0)) /* IO space size to @0x9FFF FFFF */ +#define PCCARD_IO_SPACE_SECONDARY_ADDR ((uint32_t)(XMC_BANK4_ + PCCARD_IO_SPACE_ADDRESS + 0x170)) /* IO space size to @0x9FFF FFFF */ + + /* Compact Flash-ATA registers description */ +#define ATA_DATA ((uint8_t)0x00) /* Data register */ +#define ATA_ERROR_REG ((uint8_t)0x01) /* Error register */ +#define ATA_FEATURE_REG ((uint8_t)0x01) /* Feature register */ +#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */ +#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */ +#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */ +#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */ +#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */ +#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */ +#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */ +#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */ + +// CFA spec. page 19 +// The configuration of the CompactFlash Card will be controlled using the standard +// PCMCIA configuration registers starting at address 200h in the Attribute Memory space + /* attribute memory space register description */ +#define ATTRIBUTE_MEM_BASE 0 +#define ATTRIBUTE_MEM_CONFIG_BASE 0x200 +#define CONFIG_OPTION_REG ATTRIBUTE_MEM_CONFIG_BASE + 0x00 +#define CARD_CONFIG_STATUS_REG ATTRIBUTE_MEM_CONFIG_BASE + 0x02 +#define PIN_REPLACE_REG ATTRIBUTE_MEM_CONFIG_BASE + 0x04 +#define SOCKET_COPY_REG ATTRIBUTE_MEM_CONFIG_BASE + 0x06 +// #define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */ + + /* configuration option register */ +#define CONF0_BIT 0x01 +#define CONF1_BIT 0x02 +#define CONF2_BIT 0x04 +#define CONF3_BIT 0x08 +#define CONF4_BIT 0x10 +#define CONF5_BIT 0x20 +#define LEVLREQ_BIT 0x40 +#define SRESET_BIT 0x80 + +#define CF_MEM_MAP_MODE 0x00 +#define CF_IO_16_MODE 0x01 +#define CF_IO_PRICH_MODE 0x02 // the XMC is not supported True IDE mode. +#define CF_IO_SECCH_MODE 0x03 // the XMC is not supported True IDE mode. + + /* Compact Flash-ATA commands */ +#define ATA_CHECK_POWER_MODE_CMD ((uint8_t)0xE5) +#define ATA_EXECUTE_DRIVE_DIAG_CMD ((uint8_t)0x90) +#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0) +#define ATA_FORMAT_TRACK_CMD ((uint8_t)0x50) +#define ATA_IDENTIFY_DRIVE_CMD ((uint8_t)0xEC) +#define ATA_IDLE_CMD ((uint8_t)0xE3) +#define ATA_IDLE_IMMEDIATE_CMD ((uint8_t)0xE1) +#define ATA_INIT_DRIVE_PARA_CMD ((uint8_t)0x91) +#define ATA_READ_BUFFER_CMD ((uint8_t)0xE4) +#define ATA_READ_LONG_SECTOR_CMD ((uint8_t)0x22) +#define ATA_READ_MULTIPLE_CMD ((uint8_t)0xC4) +#define ATA_READ_SECTOR_CMD ((uint8_t)0x20) +#define ATA_READ_VERIFY_SECTOR_CMD ((uint8_t)0x40) +#define ATA_RECALIBRATE_CMD ((uint8_t)0x10) +#define ATA_REQUEST_SENSE_CMD ((uint8_t)0x03) +#define ATA_SECURITY_DISABLE_PASSWORD_CMD ((uint8_t)0xF6) +#define ATA_SECURITY_EREASE_PREPARE_CMD ((uint8_t)0xF3) +#define ATA_SECURITY_ERASE_UNIT_CMD ((uint8_t)0xF4) +#define ATA_SECURITY_FREEZE_LOCK_CMD ((uint8_t)0xF5) +#define ATA_SECURITY_SET_PASSWORD_CMD ((uint8_t)0xF1) +#define ATA_SECURITY_UNLOCK_CMD ((uint8_t)0xF2) +#define ATA_SEEK_CMD ((uint8_t)0x70) +#define ATA_SET_FEATURE_CMD ((uint8_t)0xEF) +#define ATA_SET_MULTIPLE_MODE_CMD ((uint8_t)0xC6) +#define ATA_SET_SLEEP_MODE_CMD ((uint8_t)0xE6) +#define ATA_STANDBY_CMD ((uint8_t)0xE2) +#define ATA_STANDBY_IMMEDIATE_CMD ((uint8_t)0xE0) +#define ATA_TRANSLATE_SECTOR_CMD ((uint8_t)0x87) +#define ATA_WEAR_LEVEL_CMD ((uint8_t)0xF5) +#define ATA_WRITE_BUFFER_CMD ((uint8_t)0xE8) +#define ATA_WRITE_LONG_SECTOR_CMD ((uint8_t)0x32) +#define ATA_WRITE_MULTIPLE_CMD ((uint8_t)0xC5) +#define ATA_WRITE_MULTIPLE_WO_ERASE_CMD ((uint8_t)0xCD) +#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30) +#define ATA_WRITE_SECTOR_WO_ERASE_CMD ((uint8_t)0x38) +#define ATA_WRITE_VERIFY_CMD ((uint8_t)0x3C) + + /* feature command */ +#define ENABLE_8BIT_MODE 0x01 +#define ENABLE_PWR_LV1 0x0a +#define DISABLE_READ_LOOK_AHEAD 0x55 +#define DISABLE_POR 0x66 +#define NOP 0x69 +#define DISABLE_8BIT_MODE 0x81 +#define DISABLE_PWR_LV1 0x8a +#define SET_HOST_CUR_SOURCE_CAP 0x9a +#define APPLY_4BYTE_DATA_RW_LONG_CMD 0xbb +#define ENABLE_POR 0xcc + + /* status register */ +#define BUSY_BIT 0x80 +#define RDY_BIT 0x40 +#define DWF_BIT 0x20 +#define DSC_BIT 0x10 +#define DRQ_BIT 0x08 +#define CORR_BIT 0x04 +#define ERR_BIT 0x01 + + /* error register */ +#define BBK_BIT 0x80 +#define UNC_BIT 0x40 +#define IDNF_BIT 0x10 +#define ABRT_BIT 0x04 +#define AMNF_BIT 0x01 + + /* Compact Flash status */ +#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60) +#define PCCARD_BUSY ((uint8_t)0x80) +#define PCCARD_PROGR ((uint8_t)0x01) +#define PCCARD_READY ((uint8_t)0x40) + +//#define PCCARD_SECTOR_SIZE ((uint32_t)255) /* In half words */ +#define PCCARD_SECTOR_SIZE ((uint32_t)512) +#define PCCARD_LONG_SECTOR_SIZE ((uint32_t)516) +#define PCCARD_25_SECTORS_SIZES ((uint32_t)(512*25)) + /* CF CIS information */ +#define CISTPL_DEVICE 0x01 +#define CISTPL_DEVICE_OC 0x1c +#define CISTPL_JEDEC_C 0x18 +#define CISTPL_MANFID 0x20 +#define CISTPL_VERS_1 0x15 +#define CISTPL_FUNCID 0x21 +#define CISTPL_FUNCE 0x22 +#define CISTPL_CONFIG 0x1a +#define CISTPL_CFTABLE_ENTRY 0x1b +#define CISTPL_NO_LINK 0x14 +#define CISTPL_END 0xff +#define TPL_LINK_LOC 16 +#define MAX_CIS_LEN 0x200 + + /* Compact Flash redefinition */ + +#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS +#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS +#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS +#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS +#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR + +#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR +#define CF_BUSY PCCARD_BUSY +#define CF_PROGR PCCARD_PROGR +#define CF_READY PCCARD_READY + +#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE +#define Read_Transfer 1 +#define Write_Transfer 0 +#define Enable_8_bit_Transfer 1 +#define Enable_16_bit_Transfer 0 + +#define CF_print( cond, _x_) \ + if ( cond ) { \ + printf _x_ ; \ + } + + /* For print message level */ +#define ERR_REG_INFO 0 +#define STS_REG_INFO 0 +#define PRT_INIT_INFO 1 +#define PRT_CMD_INFO 0 +#define PRT_ERR_INFO 0 + + /** + * @} + */ + + /* Exported typedef ----------------------------------------------------------*/ + /** @defgroup PCCARD_Exported_Types PCCARD Exported Types + * @{ + */ + + typedef unsigned char BOOL; + typedef enum + { + UNLOCKED = 0x00, + LOCKED = 0x01 + } LockType; + typedef enum + { + STATUS_OK = 0x00, + STATUS_ERROR = 0x01, + } StatusType; + + /** + * @brief HAL PCCARD State structures definition + */ + typedef enum + { + PCCARD_STATE_RESET = 0x00, /*!< PCCARD peripheral not yet initialized or disabled */ + PCCARD_STATE_READY = 0x01, /*!< PCCARD peripheral ready */ + PCCARD_STATE_BUSY = 0x02, /*!< PCCARD peripheral busy */ + PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */ + } PCCARD_StateType; + + + /* CF type */ + typedef struct + { + uint16_t Default_Cylinder; + uint8_t Default_Head; + uint16_t Default_Sector; + uint16_t Current_Cylinder; + uint8_t Current_Head; + uint16_t Current_Sector; + uint32_t Total_Sector; + uint32_t Total_LBA_Sector; + uint16_t Max_Mutiple_Sector; + uint16_t Mutiple_Sector_Setting; + } CFCardInfoStruct; + + /* CF address struct */ + typedef struct + { + uint16_t Sector_Count; + uint16_t Cylinder; + uint8_t Head; + uint8_t Sector; + uint8_t Drv; + uint32_t SectorSize; + } CFCardAddrStruct; + + /* CF card structure */ + typedef struct + { + uint32_t IOAddr; + BOOL DMAEnable; + BOOL Enable_8_bit_mode; + CFCardInfoStruct CFCardInfo; + CFCardAddrStruct CFAddr; + uint16_t Protocol; + + /* Drive Name */ + uint32_t Drive; + + } CFCardStruct; + + /* ATA-Command verification result */ + typedef struct + { + BOOL ATA_CHECK_POWER_MODE_PASS; + BOOL ATA_EXECUTE_DRIVE_DIAG_PASS; + BOOL ATA_ERASE_SECTOR_PASS; + BOOL ATA_FORMAT_TRACK_PASS; + BOOL ATA_IDENTIFY_DRIVE_PASS; + BOOL ATA_IDLE_PASS; + BOOL ATA_IDLE_IMMEDIATE_PASS; + BOOL ATA_INIT_DRIVE_PARA_PASS; + BOOL ATA_READ_BUFFER_PASS; + BOOL ATA_READ_LONG_SECTOR_PASS; + BOOL ATA_READ_MULTIPLE_PASS; + BOOL ATA_READ_SECTOR_PASS; + BOOL ATA_READ_VERIFY_SECTOR_PASS; + BOOL ATA_RECALIBRATE_PASS; + BOOL ATA_REQUEST_SENSE_PASS; + BOOL ATA_SECURITY_DISABLE_PASSWORD_PASS; + BOOL ATA_SECURITY_EREASE_PREPARE_PASS; + BOOL ATA_SECURITY_ERASE_UNIT_PASS; + BOOL ATA_SECURITY_FREEZE_LOCK_PASS; + BOOL ATA_SECURITY_SET_PASSWORD_PASS; + BOOL ATA_SECURITY_UNLOCK_PASS; + BOOL ATA_SEEK_PASS; + BOOL ATA_SET_FEATURE_PASS; + BOOL ATA_SET_MULTIPLE_MODE_PASS; + BOOL ATA_SET_SLEEP_MODE_PASS; + BOOL ATA_STANDBY_PASS; + BOOL ATA_STANDBY_IMMEDIATE_PASS; + BOOL ATA_TRANSLATE_SECTOR_PASS; + BOOL ATA_WEAR_LEVEL_PASS; + BOOL ATA_WRITE_BUFFER_PASS; + BOOL ATA_WRITE_LONG_SECTOR_PASS; + BOOL ATA_WRITE_MULTIPLE_PASS; + BOOL ATA_WRITE_MULTIPLE_WO_ERASE_PASS; + BOOL ATA_WRITE_SECTOR_PASS; + BOOL ATA_WRITE_SECTOR_WO_ERASE_PASS; + BOOL ATA_WRITE_VERIFY_PASS; + BOOL ACESS_25_SECTORS_PASS; + BOOL CIS_READ_PASS; + BOOL ATTRIBUTE_RW_PASS; + + } verification_result_struct; + + /** + * @brief XMC_PCCARD handle Structure definition + */ + typedef struct + { + xmc_bank4_type *Instance; /*!< Register base address for PCCARD device */ + + xmc_pccard_init_type Init; /*!< PCCARD device control configuration parameters */ + + __IO PCCARD_StateType State; /*!< PCCARD device access state */ + + LockType Lock; /*!< PCCARD Lock */ + + CFCardStruct CF; + + } PCCARD_HandleType; + /** + * @} + */ + + /* Exported constants --------------------------------------------------------*/ + /* Exported macro ------------------------------------------------------------*/ + /** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros + * @{ + */ + + /** @brief Reset PCCARD handle state + * @param __HANDLE__: specifies the PCCARD handle. + * @retval None + */ +#define __PCCARD_Reset_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = PCCARD_STATE_RESET) + /** + * @} + */ + + /* Exported functions --------------------------------------------------------*/ + /** @addtogroup PCCARD_Exported_Functions PCCARD Exported Functions + * @{ + */ + + /** @addtogroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + /* Initialization/de-initialization functions **********************************/ + StatusType PCCARD_Init(PCCARD_HandleType *hpccard, xmc_nand_pccard_timinginit_type *ComSpaceTiming, xmc_nand_pccard_timinginit_type *AttSpaceTiming, xmc_nand_pccard_timinginit_type *IOSpaceTiming); + StatusType PCCARD_DeInit(PCCARD_HandleType *hpccard); + StatusType Enable_Wait_Feature(PCCARD_HandleType *hpccard); + /** + * @} + */ + + /** @addtogroup PCCARD_Exported_Functions_Group2 Input Output and memory functions + * @{ + */ + /* IO operation functions *****************************************************/ + + BOOL PCCARD_Read_ID(PCCARD_HandleType *hpccard); + BOOL PCCARD_Identify(PCCARD_HandleType *hpccard); + BOOL PCCARD_Write_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Read_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Erase_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Diagnostic(PCCARD_HandleType *hpccard); + BOOL PCCARD_Reset(PCCARD_HandleType *hpccard); + BOOL PCCARD_Check_Power_Mode(PCCARD_HandleType *hpccard); + BOOL PCCARD_Idle(PCCARD_HandleType *hpccard, uint32_t Sector_Count); + BOOL PCCARD_Idle_Immediate(PCCARD_HandleType *hpccard); + BOOL PCCARD_Set_Sleep_Mode(PCCARD_HandleType *hpccard); + BOOL PCCARD_Standby(PCCARD_HandleType *hpccard); + BOOL PCCARD_Standby_Immediate(PCCARD_HandleType *hpccard); + BOOL PCCARD_Reuqest_Sense(PCCARD_HandleType *hpccard); + BOOL PCCARD_Read_Buffer(PCCARD_HandleType *hpccard, uint8_t *pBuffer); + BOOL PCCARD_Write_Buffer(PCCARD_HandleType *hpccard, uint8_t *pBuffer); + BOOL PCCARD_Recalibrate(PCCARD_HandleType *hpccard); + BOOL PCCARD_Init_Drive_Para(PCCARD_HandleType *hpccard, uint16_t Sector_Count, uint8_t Head_Count); + BOOL PCCARD_Seek(PCCARD_HandleType *hpccard, uint8_t Head_Count, uint16_t Cylinder_Count); + BOOL PCCARD_Translate_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address); + BOOL PCCARD_Read_Long_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint8_t *pBuffer); + BOOL PCCARD_Write_Long_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint8_t *pBuffer); + BOOL PCCARD_Write_Sector_WO_ERASE(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Format_Track(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Read_Verify_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint16_t Sector_Count); + BOOL PCCARD_Write_Verify(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Set_Multiple_Mode(PCCARD_HandleType *hpccard, uint32_t Sector_Count); + BOOL PCCARD_Set_Features(PCCARD_HandleType *hpccard, uint32_t Sector_Count, uint8_t Feature); + BOOL PCCARD_Write_Multiple(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Read_Multiple(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Write_Multiple_WO_ERASE(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + + BOOL ReadCFCardCISInformation(PCCARD_HandleType *hpccard); + BOOL CF_SendCommand(PCCARD_HandleType *hpccard, uint8_t Cmd); + BOOL TaskFileRegIsValid(PCCARD_HandleType *hpccard); + BOOL Vaild_Init_Drive_Para(PCCARD_HandleType *hpccard, uint16_t Sector_Count, uint8_t Head_Count); + + void Translate_CHSAddr(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint16_t Sector_Count, uint16_t Sector_Limit); + void PCCARD_IRQHandler(PCCARD_HandleType *hpccard); + void PCCARD_ITCallback(PCCARD_HandleType *hpccard); + void show_verification_result(verification_result_struct *result); + uint8_t *Read_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Transfer_Size); + uint8_t *Write_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Transfer_Size); + + /** + * @} + */ + + /** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions + * @{ + */ + /* PCCARD State functions *******************************************************/ + PCCARD_StateType PCCARD_GetState(PCCARD_HandleType *hpccard); + uint8_t PCCARD_Read_ERROR_REG(PCCARD_HandleType *hpccard); + uint8_t PCCARD_Read_STATUS_REG(PCCARD_HandleType *hpccard); + + +#define __XMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->BK4STS &(__FLAG__)) == (__FLAG__)) +#define __XMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) BIT_CLEAR((__INSTANCE__)->BK4STS, (__FLAG__)) + + StatusType XMC_PCCARD_InitCtrl(xmc_bank4_type *Device, xmc_pccard_init_type *Init, uint8_t Set_reg_8_bit); + StatusType XMC_Enable_Wait_Feature(xmc_bank4_type *Device, xmc_pccard_init_type *Init); + StatusType XMC_Enable_16bit_Feature(xmc_bank4_type *Device, xmc_pccard_init_type *Init, uint8_t Set_reg_8_bit); + StatusType XMC_PCCARD_InitCommonSpaceTiming(xmc_bank4_type *Device, xmc_nand_pccard_timinginit_type *Timing); + StatusType XMC_PCCARD_InitAttributeSpaceTiming(xmc_bank4_type *Device, xmc_nand_pccard_timinginit_type *Timing); + StatusType XMC_PCCARD_InitIOSpaceTiming(xmc_bank4_type *Device, xmc_nand_pccard_timinginit_type *Timing); + + +#define XMC_BKxCTRL_DEV_PCCARD ((uint32_t)0x00000000) +#define BKxTMGMEM_CLEAR_MASK ((uint32_t)(XMC_BK4TMGMEM_STP | XMC_BK4TMGMEM_OP |\ + XMC_BK4TMGMEM_HLD | XMC_BK4TMGMEM_WRSTP)) + +#define BKxTMGATT_CLEAR_MASK ((uint32_t)(XMC_BK4TMGATT_STP | XMC_BK4TMGATT_OP |\ + XMC_BK4TMGATT_HLD | XMC_BK4TMGATT_WRSTP)) + +#define BK4TMGIO_CLEAR_MASK ((uint32_t)(XMC_BK4TMGIO_STP | XMC_BK4TMGIO_OP | \ + XMC_BK4TMGIO_HLD | XMC_BK4TMGIO_WRSTP)) +#endif + /** + * @} + */ + /** + * @} + */ +#ifdef __cplusplus +} +#endif + + /** + * @} + */ + /** + * @} + */ + + diff --git a/project/at_start_f435/examples/xmc/pc_card/readme.txt b/project/at_start_f435/examples/xmc/pc_card/readme.txt new file mode 100644 index 00000000..18d53dd5 --- /dev/null +++ b/project/at_start_f435/examples/xmc/pc_card/readme.txt @@ -0,0 +1,56 @@ +/** + ************************************************************************** + * @file readme.txt + * @brief readme + ************************************************************************** + */ + + this example provides a basic example of how to use the xmc firmware library and + an associate driver to perform read/write operations on the sandisk compactflash + memory. + usart1 using pa9 to printf the result. + + the pin to pin with compactflash and xmc: + - xmc_a0 pf0 ---> a0 + - xmc_a1 pf1 ---> a1 + - xmc_a2 pf2 ---> a2 + - xmc_a3 pf3 ---> a3 + - xmc_a4 pf4 ---> a4 + - xmc_a5 pf5 ---> a5 + - xmc_a6 pf12 ---> a6 + - xmc_a7 pf13 ---> a7 + - xmc_a8 pf14 ---> a8 + - xmc_a9 pf15 ---> a9 + - xmc_a10 pd5 ---> a10 + + - xmc_d0 pb14 ---> data[0] + - xmc_d1 pc6 ---> data[1] + - xmc_d2 pc11 ---> data[2] + - xmc_d3 pc12 ---> data[3] + - xmc_d4 pe7 ---> data[4] + - xmc_d5 pa3 ---> data[5] + - xmc_d6 pa4 ---> data[6] + - xmc_d7 pa5 ---> data[7] + - xmc_d8 pe11 ---> data[8] + - xmc_d9 pe12 ---> data[9] + - xmc_d10 pe13 ---> data[10] + - xmc_d11 pe14 ---> data[11] + - xmc_d12 pe15 ---> data[12] + - xmc_d13 pb12 ---> data[13] + - xmc_d14 pd9 ---> data[14] + - xmc_d15 pd10 ---> data[15] + + - xmc_nce4_1 pg10 ---> CE1 + - xmc_nce4_2 pg11 ---> CE2 + - xmc_noe pd4 ---> NOE + - xmc_nwe pc2 ---> NWE + - xmc_nwait pd6 ---> WAIT + - xmc_intr pf10 ---> INTR + - xmc_cd pf9 ---> CD + - xmc_nreg pf7 ---> REG + - xmc_niowr pf8 ---> IOWR + - xmc_niord pf6 ---> IORD + + + + diff --git a/project/at_start_f435/examples/xmc/pc_card/src/at32f435_437_clock.c b/project/at_start_f435/examples/xmc/pc_card/src/at32f435_437_clock.c new file mode 100644 index 00000000..5fcdf0aa --- /dev/null +++ b/project/at_start_f435/examples/xmc/pc_card/src/at32f435_437_clock.c @@ -0,0 +1,119 @@ +/** + ************************************************************************** + * @file at32f435_437_clock.c + * @brief system clock config program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437_clock.h" + +/** + * @brief system clock config program + * @note the system clock is configured as follow: + * - system clock = (hext * pll_ns)/(pll_ms * pll_fr) + * - system clock source = pll (hext) + * - hext = 8000000 + * - sclk = 288000000 + * - ahbdiv = 1 + * - ahbclk = 288000000 + * - apb2div = 2 + * - apb2clk = 144000000 + * - apb1div = 2 + * - apb1clk = 144000000 + * - pll_ns = 144 + * - pll_ms = 1 + * - pll_fr = 4 + * @param none + * @retval none + */ +void system_clock_config(void) +{ + /* enable pwc periph clock */ + crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); + + /* config ldo voltage */ + pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3); + + /* set the flash clock divider */ + flash_clock_divider_set(FLASH_CLOCK_DIV_3); + + /* reset crm */ + crm_reset(); + + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); + + /* wait till hext is ready */ + while(crm_hext_stable_wait() == ERROR) + { + } + + /* config pll clock resource + common frequency config list: pll source selected hick or hext(8mhz) + _________________________________________________________________________________________________ + | | | | | | | | | | | + |pll(mhz)| 288 | 252 | 216 | 192 | 180 | 144 | 108 | 72 | 36 | + |________|_________|_________|_________|_________|_________|_________|_________|_________________| + | | | | | | | | | | | + |pll_ns | 144 | 126 | 108 | 96 | 90 | 72 | 108 | 72 | 72 | + | | | | | | | | | | | + |pll_ms | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | + | | | | | | | | | | | + |pll_fr | FR_4 | FR_4 | FR_4 | FR_4 | FR_4 | FR_4 | FR_8 | FR_8 | FR_16| + |________|_________|_________|_________|_________|_________|_________|_________|________|________| + + if pll clock source selects hext with other frequency values, or configure pll to other + frequency values, please use the at32 new clock configuration tool for configuration. */ + crm_pll_config(CRM_PLL_SOURCE_HEXT, 144, 1, CRM_PLL_FR_4); + + /* enable pll */ + crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); + + /* wait till pll is ready */ + while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) + { + } + + /* config ahbclk */ + crm_ahb_div_set(CRM_AHB_DIV_1); + + /* config apb2clk, the maximum frequency of APB1/APB2 clock is 144 MHz */ + crm_apb2_div_set(CRM_APB2_DIV_2); + + /* config apb1clk, the maximum frequency of APB1/APB2 clock is 144 MHz */ + crm_apb1_div_set(CRM_APB1_DIV_2); + + /* enable auto step mode */ + crm_auto_step_mode_enable(TRUE); + + /* select pll as system clock source */ + crm_sysclk_switch(CRM_SCLK_PLL); + + /* wait till pll is used as system clock source */ + while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) + { + } + + /* disable auto step mode */ + crm_auto_step_mode_enable(FALSE); + + /* update system_core_clock global variable */ + system_core_clock_update(); +} diff --git a/project/at_start_f435/examples/xmc/pc_card/src/at32f435_437_int.c b/project/at_start_f435/examples/xmc/pc_card/src/at32f435_437_int.c new file mode 100644 index 00000000..83aa2e6a --- /dev/null +++ b/project/at_start_f435/examples/xmc/pc_card/src/at32f435_437_int.c @@ -0,0 +1,139 @@ +/** + ************************************************************************** + * @file at32f435_437_int.c + * @brief main interrupt service routines. + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437_int.h" + +/** @addtogroup AT32F435_periph_examples + * @{ + */ + +/** @addtogroup 435_XMC_sram + * @{ + */ + +/** + * @brief this function handles nmi exception. + * @param none + * @retval none + */ +void NMI_Handler(void) +{ +} + +/** + * @brief this function handles hard fault exception. + * @param none + * @retval none + */ +void HardFault_Handler(void) +{ + /* go to infinite loop when hard fault exception occurs */ + while (1) + { + } +} + +/** + * @brief this function handles memory manage exception. + * @param none + * @retval none + */ +void MemManage_Handler(void) +{ + /* go to infinite loop when memory manage exception occurs */ + while (1) + { + } +} + +/** + * @brief this function handles bus fault exception. + * @param none + * @retval none + */ +void BusFault_Handler(void) +{ + /* go to infinite loop when bus fault exception occurs */ + while (1) + { + } +} + +/** + * @brief this function handles usage fault exception. + * @param none + * @retval none + */ +void UsageFault_Handler(void) +{ + /* go to infinite loop when usage fault exception occurs */ + while (1) + { + } +} + +/** + * @brief this function handles svcall exception. + * @param none + * @retval none + */ +void SVC_Handler(void) +{ +} + +/** + * @brief this function handles debug monitor exception. + * @param none + * @retval none + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief this function handles pendsv_handler exception. + * @param none + * @retval none + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief this function handles systick handler. + * @param none + * @retval none + */ +void SysTick_Handler(void) +{ +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/project/at_start_f435/examples/xmc/pc_card/src/main.c b/project/at_start_f435/examples/xmc/pc_card/src/main.c new file mode 100644 index 00000000..bf2d5f03 --- /dev/null +++ b/project/at_start_f435/examples/xmc/pc_card/src/main.c @@ -0,0 +1,707 @@ +/** + ************************************************************************** + * @file main.c + * @brief main program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ +#include +#include +#include +#include "at32f435_437_board.h" +#include "at32f435_437_clock.h" +#include "cf.h" + + +/** @addtogroup AT32F435_periph_examples + * @{ + */ + +/** @addtogroup 435_XMC_pc_card + * @{ + */ + +typedef enum +{ + FAILED = 0, + PASSED = 1 +} TestStatus; + +/* Private define ------------------------------------------------------------*/ +#define Start_Sector 0 + +/* Private variables ---------------------------------------------------------*/ +PCCARD_HandleType pccardHandle; +xmc_nand_pccard_timinginit_type PCCARD_PMEM4_Timing; +xmc_nand_pccard_timinginit_type PCCARD_PATT4_Timing; +xmc_nand_pccard_timinginit_type PCCARD_PIO4_Timing; +verification_result_struct verification_result; +/* 0 -> Memory/PIO mode, 1 -> IO/PIO mode, 2 -> Memory/DMA mode, 3 -> IO/DMA mode */ +uint8_t Test_Mode = 0; +uint8_t pccard_TxBuffer[PCCARD_SECTOR_SIZE * sizeof(uint8_t)] __attribute__ ((aligned (4))); +uint8_t pccard_RxBuffer[PCCARD_SECTOR_SIZE * sizeof(uint8_t)] __attribute__ ((aligned (4))); +uint8_t pccard_25_Sectors_TxBuffer[PCCARD_25_SECTORS_SIZES * sizeof(uint8_t)] __attribute__ ((aligned (4))); +uint8_t pccard_25_Sectors_RxBuffer[PCCARD_25_SECTORS_SIZES * sizeof(uint8_t)] __attribute__ ((aligned (4))); +uint8_t orig_default_Sector; +uint8_t orig_default_head; +uint32_t u32i; +/* Private function prototypes -----------------------------------------------*/ +static void Fill_Buffer(uint8_t *pBuffer, uint32_t BufferLenght, uint32_t Offset); +static TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint32_t BufferLength); + +/** + * @brief main function. + * @param none + * @retval none + */ +int main(void) +{ + system_clock_config(); + + at32_board_init(); + + uart_print_init(115200); + + crm_periph_clock_enable(CRM_XMC_PERIPH_CLOCK, TRUE); + + pccardHandle.Instance = XMC_BANK4; + PCCARD_PMEM4_Timing.mem_setup_time = 12; + PCCARD_PMEM4_Timing.mem_waite_time = 61; + PCCARD_PMEM4_Timing.mem_hold_time = 14 ; + PCCARD_PMEM4_Timing.mem_hiz_time = 0; + + PCCARD_PATT4_Timing.mem_setup_time = 12; + PCCARD_PATT4_Timing.mem_waite_time = 99; + PCCARD_PATT4_Timing.mem_hold_time = 12; + PCCARD_PATT4_Timing.mem_hiz_time = 1; + + PCCARD_PIO4_Timing.mem_setup_time = 24; + PCCARD_PIO4_Timing.mem_waite_time = 61; + PCCARD_PIO4_Timing.mem_hold_time = 8; + PCCARD_PIO4_Timing.mem_hiz_time = 1; + + + pccardHandle.Init.enable_wait = 1; + pccardHandle.Init.delay_time_cr = 0; + pccardHandle.Init.delay_time_ar = 0; + memset(&verification_result, 0, sizeof(verification_result)); + + + while(Test_Mode < 4) + { + /* 0 -> 16-bit Memory/PIO mode + * 2 -> 16-bit IO/PIO mode + * 4 -> 16-bit Memory/DMA mode + * 6 -> 16-bit IO/DMA mode + */ + switch(Test_Mode) + { + case 0: + pccardHandle.CF.Protocol = CF_MEM_MAP_MODE; + pccardHandle.CF.IOAddr = PCCARD_COMMON_SPACE_ADDRESS; + pccardHandle.CF.DMAEnable = FALSE; + pccardHandle.CF.Enable_8_bit_mode = FALSE; + printf("\r\n16-bit Memory/PIO mode Start... "); + break; + + case 1: + pccardHandle.CF.Protocol = CF_IO_16_MODE; + pccardHandle.CF.IOAddr = PCCARD_IO_SPACE_ADDRESS; + pccardHandle.CF.DMAEnable = FALSE; + pccardHandle.CF.Enable_8_bit_mode = FALSE; + printf("\r\n16-bit IO/PIO mode Start... "); + break; + + case 2: + pccardHandle.CF.Protocol = CF_MEM_MAP_MODE; + pccardHandle.CF.IOAddr = PCCARD_COMMON_SPACE_ADDRESS; + pccardHandle.CF.DMAEnable = TRUE; + pccardHandle.CF.Enable_8_bit_mode = FALSE; + printf("\r\n16-bit Memory/DMA mode Start... "); + break; + + case 3: + pccardHandle.CF.Protocol = CF_IO_16_MODE; + pccardHandle.CF.IOAddr = PCCARD_IO_SPACE_ADDRESS; + pccardHandle.CF.DMAEnable = TRUE; + pccardHandle.CF.Enable_8_bit_mode = FALSE; + printf("\r\n16-bit IO/DMA mode Start... "); + break; + + + default: + printf("\r\nSelect Test Mode Failed"); + break; + } + + pccardHandle.CF.Drive = 0; + + /* Init Compact Flash Controller */ + CF_print(PRT_INIT_INFO, ("\r\nInit Compact Flash Card...")); + + if(PCCARD_Init(&pccardHandle, &PCCARD_PMEM4_Timing, &PCCARD_PATT4_Timing, &PCCARD_PIO4_Timing) != STATUS_OK) + { + printf("\r\nCompact Flash card Init Failed"); + break; + } + + /* Reset Compact Flash card */ + CF_print(PRT_INIT_INFO, ("\r\nReset Compact Flash Card...")); + + if(PCCARD_Reset(&pccardHandle)) + { + verification_result.ATTRIBUTE_RW_PASS = TRUE; + } + + CF_print(PRT_INIT_INFO, ("\r\nSet Wait Feature...")); + + if(Enable_Wait_Feature(&pccardHandle) != STATUS_OK) + { + printf("\r\nCompact Flash card Set Wait Feature Failed"); + break; + } + + /* Read CF Card CIS from CF card's attribute memory */ + if(ReadCFCardCISInformation(&pccardHandle)) + { + verification_result.CIS_READ_PASS = TRUE; + } + + /* CF-ATA Command Set Test Started */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_IDENTIFY_DRIVE...")); + + /* Read Compact Flash Card ID (CF_ATA_IDENTIFY_DRIVE) */ + if(PCCARD_Read_ID(&pccardHandle)) + { + verification_result.ATA_IDENTIFY_DRIVE_PASS = TRUE; + } + + /* Execute Drive Diagnostic */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_EXECUTE_DRIVE_DIAG...")); + + if(PCCARD_Diagnostic(&pccardHandle)) + { + verification_result.ATA_EXECUTE_DRIVE_DIAG_PASS = TRUE; + } + + /* Write Compact Flash Card Sector */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_WRITE_SECTOR...")); + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); + if(!PCCARD_Write_Sector(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Secor Failed"); + break; + } + + /* Read Compact Flash Card Sector */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_READ_SECTOR...")); + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Sector(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Secor Failed"); + break; + } + /* Checking data integrity */ + if(Buffercmp(pccard_TxBuffer, pccard_RxBuffer, PCCARD_SECTOR_SIZE) == PASSED) + { + verification_result.ATA_READ_SECTOR_PASS = TRUE; + verification_result.ATA_WRITE_SECTOR_PASS = TRUE; + } + else + { + verification_result.ATA_READ_SECTOR_PASS = FALSE; + verification_result.ATA_WRITE_SECTOR_PASS = FALSE; + } + + + /* Write Compact Flash Card Buffer */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_WRITE_BUFFER...")); + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); + + if(!PCCARD_Write_Buffer(&pccardHandle, pccard_TxBuffer)) + { + printf("\r\nCompact Flash card Write Buffer Failed"); + break; + } + + /* Read Compact Flash Card Buffer */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_READ_BUFFER...")); + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Buffer(&pccardHandle, pccard_RxBuffer)) + { + printf("\r\nCompact Flash card Read Buffer Failed"); + break; + } + /* Checking data integrity */ + if(Buffercmp(pccard_TxBuffer, pccard_RxBuffer, PCCARD_SECTOR_SIZE) == PASSED) + { + verification_result.ATA_READ_BUFFER_PASS = TRUE; + verification_result.ATA_WRITE_BUFFER_PASS = TRUE; + } + else + { + verification_result.ATA_READ_BUFFER_PASS = FALSE; + verification_result.ATA_WRITE_BUFFER_PASS = FALSE; + } + + /* Recalibrate */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_RECALIBRATE...")); + + if(PCCARD_Recalibrate(&pccardHandle)) + { + verification_result.ATA_RECALIBRATE_PASS = TRUE; + } + + /* Initialize Drive Parameters */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_Init_Drive_Para...")); + orig_default_Sector = pccardHandle.CF.CFCardInfo.Current_Sector; + orig_default_head = pccardHandle.CF.CFCardInfo.Current_Head; + + + pccardHandle.CF.CFCardInfo.Current_Sector -= 1; + pccardHandle.CF.CFCardInfo.Current_Head -= 1; + + if(!PCCARD_Init_Drive_Para(&pccardHandle, pccardHandle.CF.CFCardInfo.Current_Sector, pccardHandle.CF.CFCardInfo.Current_Head - 1)) + { + printf("\r\nInit Drive Para fail"); + break; + } + /* check the command is vailded */ + if(Vaild_Init_Drive_Para(&pccardHandle, pccardHandle.CF.CFCardInfo.Current_Sector, pccardHandle.CF.CFCardInfo.Current_Head)) + { + verification_result.ATA_INIT_DRIVE_PARA_PASS = TRUE; + } + + pccardHandle.CF.CFCardInfo.Current_Sector = orig_default_Sector; + pccardHandle.CF.CFCardInfo.Current_Head = orig_default_head; + + if(!PCCARD_Init_Drive_Para(&pccardHandle, orig_default_Sector, orig_default_head - 1)) + { + printf("\r\nInit Drive Para fail"); + break; + } + /* check restore is vailded */ + if(!Vaild_Init_Drive_Para(&pccardHandle, pccardHandle.CF.CFCardInfo.Current_Sector, pccardHandle.CF.CFCardInfo.Current_Head)) + { + verification_result.ATA_INIT_DRIVE_PARA_PASS = FALSE; + } + + /* Seek */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_SEEK...")); + + if(PCCARD_Seek(&pccardHandle, pccardHandle.CF.CFCardInfo.Default_Head - 1, pccardHandle.CF.CFCardInfo.Default_Cylinder + 1)) + { + verification_result.ATA_SEEK_PASS = TRUE; + } + + /* Erase Compact Flash Card Sector */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_ERASE_SECTOR...")); + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); + + if(!PCCARD_Write_Sector(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Secor Failed"); + break; + } + + if(!PCCARD_Erase_Sector(&pccardHandle, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Erase Secor Failed"); + break; + } + + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Sector(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Secor Failed"); + break; + } + else + { + verification_result.ATA_ERASE_SECTOR_PASS = TRUE; + + for(u32i = 0; u32i < PCCARD_SECTOR_SIZE; u32i++) + { + if(*(pccard_RxBuffer + u32i) != 0x0) + { + verification_result.ATA_ERASE_SECTOR_PASS = FALSE; + CF_print(PRT_ERR_INFO, ("\r\nErase sector error at address offset 0x%0.2x:(0x%0.2x)", u32i, *(pccard_RxBuffer + u32i))); + break; + } + } + } + + /* Write Compact Flash Card Write Sector Without Erase */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_WRITE_SECTOR_WO_ERASE...")); + + if(!PCCARD_Erase_Sector(&pccardHandle, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Erase Secor Failed"); + break; + } + + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); + + if(!PCCARD_Write_Sector_WO_ERASE(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Secor Without Erase Failed"); + break; + } + + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Sector(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Secor Failed"); + break; + } + /* Checking data integrity */ + if(Buffercmp(pccard_TxBuffer, pccard_RxBuffer, PCCARD_SECTOR_SIZE) == PASSED) + { + verification_result.ATA_WRITE_SECTOR_WO_ERASE_PASS = TRUE; + } + else + { + verification_result.ATA_WRITE_SECTOR_WO_ERASE_PASS = FALSE; + } + + /* Format Track */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_FORMAT_TRACK...")); + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); + + if(!PCCARD_Write_Sector(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Secor Failed"); + break; + } + + + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Sector(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Secor Failed"); + break; + } + else + { + verification_result.ATA_FORMAT_TRACK_PASS = TRUE; + + for(u32i = 0; u32i < PCCARD_SECTOR_SIZE; u32i++) + { + if(!(*(pccard_RxBuffer + u32i) == 0xff || *(pccard_RxBuffer + u32i) == 0x0)) + { + verification_result.ATA_FORMAT_TRACK_PASS = FALSE; + CF_print(PRT_ERR_INFO, ("\r\nFormat track error at address offset 0x%0.2x:(0x%0.2x)", u32i, *(pccard_RxBuffer + u32i))); + break; + } + } + } + + /* Read Verify Sector */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_READ_VERIFY_SECTOR...")); + + if(PCCARD_Read_Verify_Sector(&pccardHandle, Start_Sector, 1)) + { + verification_result.ATA_READ_VERIFY_SECTOR_PASS = TRUE; + } + + /* Write verify */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_WRITE_VERIFY...")); + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); // Fill the buffer to write + + if(!PCCARD_Write_Verify(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Verify Failed"); + break; + } + + /* Read Compact Flash Card Sector */ + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Sector(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Secor Failed"); + break; + } + /* Checking data integrity */ + if(Buffercmp(pccard_TxBuffer, pccard_RxBuffer, PCCARD_SECTOR_SIZE) == PASSED) + { + verification_result.ATA_WRITE_VERIFY_PASS = TRUE; + } + else + { + verification_result.ATA_WRITE_VERIFY_PASS = FALSE; + } + + /* Translate Sector */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_TRANSLATE_SECTOR...")); + + if(!PCCARD_Translate_Sector(&pccardHandle, Start_Sector)) + { + printf("\r\nCompact Flash card Translate Sector Failed"); + break; + } + + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Buffer(&pccardHandle, pccard_RxBuffer)) + { + printf("\r\nCompact Flash card Read Buffer Failed"); + break; + } + + if((pccard_RxBuffer[1]) == pccardHandle.CF.CFAddr.Cylinder && + (pccard_RxBuffer[2]) == pccardHandle.CF.CFAddr.Head && + (pccard_RxBuffer[3]) == pccardHandle.CF.CFAddr.Sector) + { + verification_result.ATA_TRANSLATE_SECTOR_PASS = TRUE; + } + + /* Set Multiple Mode */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_SET_MULTIPLE_MODE...")); + PCCARD_Set_Multiple_Mode(&pccardHandle, pccardHandle.CF.CFCardInfo.Max_Mutiple_Sector + 1); + + if(PCCARD_Read_ERROR_REG(&pccardHandle) & ABRT_BIT) + { + verification_result.ATA_SET_MULTIPLE_MODE_PASS = TRUE; + } + + PCCARD_Set_Multiple_Mode(&pccardHandle, pccardHandle.CF.CFCardInfo.Max_Mutiple_Sector); + + if(PCCARD_Read_ERROR_REG(&pccardHandle)) + { + verification_result.ATA_SET_MULTIPLE_MODE_PASS = FALSE; + } + + /* Set Feature */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_SET_FEATURE...")); + + // send a valid feature to CF card, we expect there are no bit will be assert in Error register . + PCCARD_Set_Features(&pccardHandle, 0, NOP); + + if(PCCARD_Read_ERROR_REG(&pccardHandle)) + { + verification_result.ATA_SET_FEATURE_PASS = FALSE; + } + else + { + verification_result.ATA_SET_FEATURE_PASS = TRUE; + } + + /* Write Multiple */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_WRITE_MULTIPLE...")); + /* Note that the maximun number of sectors on Read/Write Multiple command in our CF test card is 1, + so it will work same as Read/Write Sector command. */ + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); // Fill the buffer to write + + if(!PCCARD_Write_Multiple(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Multiple Secors Failed"); + break; + } + + /* Read Multiple */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_READ_MULTIPLE...")); + /* Note that the maximun number of sectors on Read/Write Multiple command in our CF test card is 1, + so it will work same as Read/Write Sector command. */ + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Multiple(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Multiple Secors Failed"); + break; + } + /* Checking data integrity */ + if(Buffercmp(pccard_TxBuffer, pccard_RxBuffer, PCCARD_SECTOR_SIZE) == PASSED) + { + verification_result.ATA_READ_MULTIPLE_PASS = TRUE; + verification_result.ATA_WRITE_MULTIPLE_PASS = TRUE; + } + else + { + verification_result.ATA_READ_MULTIPLE_PASS = FALSE; + verification_result.ATA_WRITE_MULTIPLE_PASS = FALSE; + } + + /* Write Multiple Without Erase */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_WRITE_MULTIPLE_WO_ERASE...")); + + /* Note that the maximun number of sectors on Read/Write Multiple command in our CF test card is 1, + so it will work same as Read/Write Sector command. */ + if(!PCCARD_Erase_Sector(&pccardHandle, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Erase Secor Failed"); + break; + } + + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); + + if(!PCCARD_Write_Multiple_WO_ERASE(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Multiple Secors Without Erase Failed"); + break; + } + + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Multiple(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Multiple Secors Failed"); + break; + } + + if(Buffercmp(pccard_TxBuffer, pccard_RxBuffer, PCCARD_SECTOR_SIZE) == PASSED) // Checking data integrity + { + verification_result.ATA_WRITE_MULTIPLE_WO_ERASE_PASS = TRUE; + } + else + { + verification_result.ATA_WRITE_MULTIPLE_WO_ERASE_PASS = FALSE; + } + + + /* disable the Read/Write Multiple command, we expect Abort bit in Error register will be assert. */ + if(!PCCARD_Set_Multiple_Mode(&pccardHandle, 0)) + { + printf("\r\nSet multiple mode to 0 Failed"); + break; + } + + /* Test Read/Write 50 sectors */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying Test Read/Write 50 sectors...")); + + memset(pccard_25_Sectors_TxBuffer, 0, PCCARD_25_SECTORS_SIZES * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_25_Sectors_TxBuffer, PCCARD_25_SECTORS_SIZES, 0x78); + + + + if(!PCCARD_Write_Sector(&pccardHandle, pccard_25_Sectors_TxBuffer, Start_Sector, 25)) + { + printf("\r\nCompact Flash card Write 50 Secors Failed"); + break; + } + + memset(pccard_25_Sectors_RxBuffer, 0, PCCARD_25_SECTORS_SIZES * sizeof(uint8_t)); + + if(!PCCARD_Read_Sector(&pccardHandle, pccard_25_Sectors_RxBuffer, Start_Sector, 25)) + { + printf("\r\nCompact Flash card Read 50 Secors Failed"); + break; + } + /* Checking data integrity */ + if(Buffercmp(pccard_25_Sectors_TxBuffer, pccard_25_Sectors_RxBuffer, PCCARD_25_SECTORS_SIZES) == PASSED) + { + verification_result.ACESS_25_SECTORS_PASS = TRUE; + } + else + { + verification_result.ACESS_25_SECTORS_PASS = FALSE; + } + + /* Show the Compact Flash Storage Card Test results */ + show_verification_result(&verification_result); + + Test_Mode++; + } + + printf("\r\nCompact Flash Storage Card Test End"); + + /* Infinite loop */ + while(1) + { + } + + +} + + +/** + * @brief Fills buffer with user predefined data. + * @param pBuffer: pointer on the buffer to fill + * @param uwBufferLenght: size of the buffer to fill + * @param uwOffset: first value to fill on the buffer + * @retval None + */ +static void Fill_Buffer(uint8_t *pBuffer, uint32_t uwBufferLenght, uint32_t uwOffset) +{ + uint32_t index = 0; + + /* Put in global buffer same values */ + for (index = 0; index < uwBufferLenght; index++ ) + { + pBuffer[index] = index + uwOffset; + } +} + +/** + * @brief Compares two buffers. + * @param pBuffer: pointer to the buffers. + * @param pBuffer1: pointer to the buffers1. + * @param uwBufferLenght: Compared buffer's length + * @retval 1: pBuffer identical to pBuffer1 + * 0: pBuffer differs from pBuffer1 + */ +static TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint32_t uwBufferLenght) +{ + uint32_t counter = 0; + + while(uwBufferLenght--) + { + if(*pBuffer != *pBuffer1) + { + printf("\r\nFormat track error at address offset 0x%0.2x:(0x%0.2x) <-> (0x%0.2x)", counter, *(pBuffer), *(pBuffer1)); + return FAILED; + } + + pBuffer++; + pBuffer1++; + counter++; + } + return PASSED; +} + +/** + * @} + */ + +/** + * @} + */ + diff --git a/project/at_start_f435/examples/xmc/psram/inc/at32f435_437_conf.h b/project/at_start_f435/examples/xmc/psram/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/xmc/psram/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/xmc/psram/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/xmc/psram/mdk_v5/psram.uvoptx b/project/at_start_f435/examples/xmc/psram/mdk_v5/psram.uvoptx index 0e001a6d..1014487c 100644 --- a/project/at_start_f435/examples/xmc/psram/mdk_v5/psram.uvoptx +++ b/project/at_start_f435/examples/xmc/psram/mdk_v5/psram.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/xmc/psram/mdk_v5/psram.uvprojx b/project/at_start_f435/examples/xmc/psram/mdk_v5/psram.uvprojx index 5247775a..45bdb5f7 100644 --- a/project/at_start_f435/examples/xmc/psram/mdk_v5/psram.uvprojx +++ b/project/at_start_f435/examples/xmc/psram/mdk_v5/psram.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/xmc/psram/src/at32f435_437_clock.c b/project/at_start_f435/examples/xmc/psram/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/xmc/psram/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/xmc/psram/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/xmc/sdram_basic/inc/at32f435_437_conf.h b/project/at_start_f435/examples/xmc/sdram_basic/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/xmc/sdram_basic/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/xmc/sdram_basic/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvoptx b/project/at_start_f435/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvoptx index da96d880..30be8cf9 100644 --- a/project/at_start_f435/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvoptx +++ b/project/at_start_f435/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvprojx b/project/at_start_f435/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvprojx index cea654fb..d643418c 100644 --- a/project/at_start_f435/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvprojx +++ b/project/at_start_f435/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -479,4 +479,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/xmc/sdram_basic/src/at32f435_437_clock.c b/project/at_start_f435/examples/xmc/sdram_basic/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/xmc/sdram_basic/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/xmc/sdram_basic/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/xmc/sdram_dma/inc/at32f435_437_conf.h b/project/at_start_f435/examples/xmc/sdram_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/xmc/sdram_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/xmc/sdram_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvoptx b/project/at_start_f435/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvoptx index e1e7684c..9d2680c4 100644 --- a/project/at_start_f435/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvoptx +++ b/project/at_start_f435/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvprojx b/project/at_start_f435/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvprojx index 90a7aa30..055c0c7c 100644 --- a/project/at_start_f435/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvprojx +++ b/project/at_start_f435/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f435/examples/xmc/sdram_dma/src/at32f435_437_clock.c b/project/at_start_f435/examples/xmc/sdram_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/xmc/sdram_dma/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/xmc/sdram_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/examples/xmc/sram/inc/at32f435_437_conf.h b/project/at_start_f435/examples/xmc/sram/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f435/examples/xmc/sram/inc/at32f435_437_conf.h +++ b/project/at_start_f435/examples/xmc/sram/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/examples/xmc/sram/mdk_v5/sram.uvoptx b/project/at_start_f435/examples/xmc/sram/mdk_v5/sram.uvoptx index 5f2587bf..f448fa40 100644 --- a/project/at_start_f435/examples/xmc/sram/mdk_v5/sram.uvoptx +++ b/project/at_start_f435/examples/xmc/sram/mdk_v5/sram.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/examples/xmc/sram/mdk_v5/sram.uvprojx b/project/at_start_f435/examples/xmc/sram/mdk_v5/sram.uvprojx index 34750854..28a3a6f0 100644 --- a/project/at_start_f435/examples/xmc/sram/mdk_v5/sram.uvprojx +++ b/project/at_start_f435/examples/xmc/sram/mdk_v5/sram.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/examples/xmc/sram/src/at32f435_437_clock.c b/project/at_start_f435/examples/xmc/sram/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f435/examples/xmc/sram/src/at32f435_437_clock.c +++ b/project/at_start_f435/examples/xmc/sram/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435/templates/inc/at32f435_437_conf.h b/project/at_start_f435/templates/inc/at32f435_437_conf.h index 44a46964..9c52a658 100644 --- a/project/at_start_f435/templates/inc/at32f435_437_conf.h +++ b/project/at_start_f435/templates/inc/at32f435_437_conf.h @@ -55,8 +55,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f435/templates/mdk_v5/template.uvoptx b/project/at_start_f435/templates/mdk_v5/template.uvoptx index 1b747417..11d0b5f4 100644 --- a/project/at_start_f435/templates/mdk_v5/template.uvoptx +++ b/project/at_start_f435/templates/mdk_v5/template.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f435/templates/mdk_v5/template.uvprojx b/project/at_start_f435/templates/mdk_v5/template.uvprojx index 609b5cf6..787f6231 100644 --- a/project/at_start_f435/templates/mdk_v5/template.uvprojx +++ b/project/at_start_f435/templates/mdk_v5/template.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -593,6 +593,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f435/templates/src/at32f435_437_clock.c b/project/at_start_f435/templates/src/at32f435_437_clock.c index ff35c697..58d49352 100644 --- a/project/at_start_f435/templates/src/at32f435_437_clock.c +++ b/project/at_start_f435/templates/src/at32f435_437_clock.c @@ -54,6 +54,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -63,9 +66,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f435_Example_list.htm b/project/at_start_f435_Example_list.htm index c5eb9409..f2b18615 100644 --- a/project/at_start_f435_Example_list.htm +++ b/project/at_start_f435_Example_list.htm @@ -10,20 +10,22 @@ {font-family:; panose-1:2 1 6 0 3 1 1 1 1 1;} @font-face - {font-family:; - panose-1:2 1 6 0 3 1 1 1 1 1;} + {font-family:"Cambria Math"; + panose-1:2 4 5 3 5 4 6 3 2 4;} @font-face - {font-family:Calibri; - panose-1:2 15 5 2 2 2 4 3 2 4;} + {font-family:; + panose-1:2 1 6 0 3 1 1 1 1 1;} @font-face {font-family:; panose-1:2 1 6 9 6 1 1 1 1 1;} @font-face - {font-family:"\@"; - panose-1:2 1 6 9 6 1 1 1 1 1;} + {font-family:"\@";} @font-face {font-family:"\@"; panose-1:2 1 6 0 3 1 1 1 1 1;} +@font-face + {font-family:"\@"; + panose-1:2 1 6 0 3 1 1 1 1 1;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {margin:0cm; @@ -31,9 +33,9 @@ text-align:justify; text-justify:inter-ideograph; font-size:10.5pt; - font-family:"Calibri","sans-serif";} + font-family:;} .MsoChpDefault - {font-family:"Calibri","sans-serif";} + {font-family:;} /* Page Definitions */ @page WordSection1 {size:595.3pt 841.9pt; @@ -3491,7 +3493,7 @@ div.WordSection1

                    164

                    -

                    pc_card

                    + + +

                    PC Card洢д

                    + + + + +

                    169

                    + + +

                    psram

                    169

                    + style='font-size:11.0pt;font-family:;color:black'>170

                    170

                    + style='font-size:11.0pt;font-family:;color:black'>171

                    171

                    + style='font-size:11.0pt;font-family:;color:black'>172

                    Collection of Component include folders: - C:\Users\Arm\Packs\ArteryTek\AT32F435_437_DFP\2.1.0\Device\Include + C:\Users\sheltonyu\AppData\Local\Arm\Packs\ArteryTek\AT32F435_437_DFP\2.0.1\Device\Include

                    Collection of Component Files used:

                    -Build Time Elapsed: 00:00:08 +Build Time Elapsed: 00:00:06 diff --git a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.hex b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.hex index 6f0400ce..75289b17 100644 --- a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.hex +++ b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.hex @@ -35,14 +35,14 @@ :1002100000F049F80AA090E8000C82448344AAF157 :100220000107DA4501D100F03EF8AFF2090EBAE855 :100230000F0013F0010F18BFFB1A43F0010318471A -:10024000D8200000F8200000103A24BF78C878C1F8 +:10024000F020000010210000103A24BF78C878C1C7 :10025000FAD8520724BF30C830C144BF04680C60CC :10026000704700000023002400250026103A28BF14 :1002700078C1FBD8520728BF30C148BF0B60704718 -:10028000662901F04987002070471FB501F037FF4C -:1002900000F0AAFA04000020002101F0A3FEE060B3 +:10028000662901F05587002070471FB501F043FF34 +:1002900000F0AAFA04000020002101F0AFFEE060A7 :1002A0001FBD10B510BD00F0BFFB1146FFF7EDFFFD -:1002B00001F0B4F800F0DDFB03B4FFF7F2FF03BC7C +:1002B00001F0C8F800F0DDFB03B4FFF7F2FF03BC68 :1002C00000F066FC0948804709480047FEE7FEE762 :1002D000FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE7F6 :1002E00004480549054A064B70470000250B0008E5 @@ -69,11 +69,11 @@ :10043000FBDB30460022002121540B99C1F80880D3 :10044000C1E900200FB0BDE8F08FBD1B6D1CDEE7D9 :100450004A4600DA694206A800F06CFA06AB93E857 -:10046000070003AB83E8070050460A9901F0BBF987 +:10046000070003AB83E8070050460A9901F0C9F979 :100470008DE80700A0F500501F3800900398002D6C :100480000ADD42F21F014A460844002303A90390F3 -:10049000684601F025FC09E0A0F500504A461F38E7 -:1004A000002303A90390684601F02FFC8DE80700A4 +:10049000684601F032FC09E0A0F500504A461F38DA +:1004A000002303A90390684601F03CFC8DE8070097 :1004B0000004000C03D04FF0FF30410800E010466C :1004C000B8F1000F03D00022009215461EE0751E01 :1004D00005D400F091F9303262556D1EF9D5B3465E @@ -86,7 +86,7 @@ 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+:102150000000409C00000000194000000020BCBEB0 +:102160000000000034400000BFC91B8E00000004C6 +:10217000B5400000504BCFD06607E2CF0100000011 +:102180006C4100003E8251AADFEEA734010000003E +:10219000D9420000DCB5A0E23A301F97FFFFFFFFF5 +:1021A000B4450000FD25A0C8E9A3C14FFFFFFFFF14 +:1021B000FF3F00000000008000000000FF3F000023 +:1021C000000000800000000014000100D00000208A +:1021D00014000400E021000804000100202300088E +:1021E00000002842000014420000A2420000E0412A +:1021F0000000A64200009042000010420000184279 +:102200000000004200004C4200007C42000080427E +:102210000000C2420000A4420000BE420000B442DE +:102220000000844200004C42000058420000284256 +:102230000000864200006042000034420000644218 +:102240000000864200008A4200000C42000050421A +:102250000000E8410000A2420000684200003C4249 +:1022600000001842000098420000C8420000E84107 +:102270000000044200003C420000E84100004842E7 +:10228000000008420000244200007442000038426E +:10229000000050420000484200004042000010424E +:1022A00000003C4200005C4200003042000020423E +:1022B0000000C8420000BC420000A84200001442D6 +:1022C0000000004200008E4200003C4200009A42A2 +:1022D0000000F841000048420000444200000C4267 +:1022E00000007C4200008642000020420000F841CD +:1022F0000000E841000088420000744200001842DB +:102300000000F8410000E0410000E0410000984278 +:1023100000005C42000004420000E84100001C4252 +:102320000000803F0000803F0000803F0000803FB1 +:102330007023000800000020080000004802000888 +:10234000782300080800002010080000640200083C +:102350001C00000043000000F8FFFFFF0C0000001D +:102360000E0000000F0000002E0000000000000022 +:082370001400000000127A00C5 :040000050800020DE0 :00000001FF diff --git a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.htm b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.htm index 1a6a035a..d8586426 100644 --- a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.htm +++ b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/cmsis_dsp.htm @@ -3,7 +3,7 @@ Static Call Graph - [.\Objects\cmsis_dsp.axf]

                    Static Call Graph for image .\Objects\cmsis_dsp.axf

                    -

                    #<CALLGRAPH># ARM Linker, 6160001: Last Updated: Thu Nov 17 20:33:56 2022 +

                    #<CALLGRAPH># ARM Linker, 6140002: Last Updated: Fri Feb 17 15:02:48 2023

                    Maximum Stack Usage = 324 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)

                    Call chain for Maximum Stack Depth:

                    @@ -647,10 +647,10 @@ Global Symbols

                    _printf_fp_dec_real (Thumb, 620 bytes, Stack size 104 bytes, _printf_fp_dec.o(.text))

                    [Stack]

                    • Max Depth = 324
                    • Call Chain = _printf_fp_dec_real ⇒ _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e
                    -
                    [Calls]
                    • >>   _fp_digits -
                    • >>   __ARM_fpclassify +
                      [Calls]
                      • >>   __ARM_fpclassify
                      • >>   _printf_fp_infnan
                      • >>   __rt_locale +
                      • >>   _fp_digits

                      [Called By]
                      • >>   _printf_fp_dec
                      @@ -796,7 +796,7 @@ Global Symbols

                      [Called By]
                      • >>   __rt_exit_exit
                      -

                      arm_mat_mult_f32 (Thumb, 320 bytes, Stack size 68 bytes, matrixfunctions.o(.text.arm_mat_mult_f32)) +

                      arm_mat_mult_f32 (Thumb, 344 bytes, Stack size 68 bytes, matrixfunctions.o(.text.arm_mat_mult_f32))

                      [Stack]

                      • Max Depth = 68
                      • Call Chain = arm_mat_mult_f32

                      [Called By]
                      • >>   main @@ -820,8 +820,8 @@ Global Symbols
                        [Called By]
                        • >>   main
                        -

                        arm_std_f32 (Thumb, 68 bytes, Stack size 16 bytes, statisticsfunctions.o(.text.arm_std_f32)) -

                        [Stack]

                        • Max Depth = 40
                        • Call Chain = arm_std_f32 ⇒ __hardfp_sqrtf ⇒ __set_errno +

                          arm_std_f32 (Thumb, 80 bytes, Stack size 24 bytes, statisticsfunctions.o(.text.arm_std_f32)) +

                          [Stack]

                          • Max Depth = 48
                          • Call Chain = arm_std_f32 ⇒ __hardfp_sqrtf ⇒ __set_errno

                          [Calls]
                          • >>   arm_var_f32
                          • >>   __hardfp_sqrtf @@ -848,7 +848,7 @@ Global Symbols

                            [Called By]
                            • >>   system_clock_config
                            -

                            crm_auto_step_mode_enable (Thumb, 24 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_auto_step_mode_enable)) +

                            crm_auto_step_mode_enable (Thumb, 26 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_auto_step_mode_enable))

                            [Called By]

                            • >>   system_clock_config
                            @@ -856,7 +856,7 @@ Global Symbols

                            [Called By]
                            • >>   system_clock_config
                            -

                            crm_clocks_freq_get (Thumb, 140 bytes, Stack size 16 bytes, at32f435_437_crm.o(.text.crm_clocks_freq_get)) +

                            crm_clocks_freq_get (Thumb, 172 bytes, Stack size 16 bytes, at32f435_437_crm.o(.text.crm_clocks_freq_get))

                            [Stack]

                            • Max Depth = 16
                            • Call Chain = crm_clocks_freq_get

                            [Calls]
                            • >>   crm_sysclk_switch_status_get @@ -877,7 +877,7 @@ Global Symbols
                              [Called By]
                              • >>   system_clock_config
                              -

                              crm_periph_clock_enable (Thumb, 40 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_periph_clock_enable)) +

                              crm_periph_clock_enable (Thumb, 40 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_periph_clock_enable))

                              [Called By]

                              • >>   uart_print_init
                              • >>   system_clock_config
                              @@ -888,7 +888,7 @@ Global Symbols
                              [Called By]
                              • >>   system_clock_config
                              -

                              crm_reset (Thumb, 80 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_reset)) +

                              crm_reset (Thumb, 80 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_reset))

                              [Called By]

                              • >>   system_clock_config
                              @@ -897,9 +897,9 @@ Global Symbols

                            crm_sysclk_switch_status_get (Thumb, 16 bytes, Stack size 0 bytes, at32f435_437_crm.o(.text.crm_sysclk_switch_status_get)) -

                            [Called By]

                            • >>   crm_clocks_freq_get -
                            • >>   system_core_clock_update +

                              [Called By]
                              • >>   system_core_clock_update
                              • >>   system_clock_config +
                              • >>   crm_clocks_freq_get

                              fputc (Thumb, 36 bytes, Stack size 16 bytes, at32f435_437_board.o(.text.fputc)) @@ -926,7 +926,7 @@ Global Symbols
                              [Called By]

                              • >>   uart_print_init
                              -

                              main (Thumb, 268 bytes, Stack size 56 bytes, main.o(.text.main)) +

                              main (Thumb, 332 bytes, Stack size 56 bytes, main.o(.text.main))

                              [Stack]

                              • Max Depth = 184 + Unknown Stack Size
                              • Call Chain = main ⇒ __2printf ⇒ _printf_char_file ⇒ _printf_char_common ⇒ __printf
                              @@ -950,9 +950,9 @@ Global Symbols
                              [Calls]
                              • >>   system_core_clock_update
                              • >>   crm_sysclk_switch_status_get
                              • >>   crm_sysclk_switch -
                              • >>   crm_reset +
                              • >>   crm_reset
                              • >>   crm_pll_config -
                              • >>   crm_periph_clock_enable +
                              • >>   crm_periph_clock_enable
                              • >>   crm_hext_stable_wait
                              • >>   crm_flag_get
                              • >>   crm_clock_source_enable @@ -964,7 +964,7 @@ Global Symbols
                                [Called By]
                                • >>   main
                                -

                                system_core_clock_update (Thumb, 116 bytes, Stack size 16 bytes, system_at32f435_437.o(.text.system_core_clock_update)) +

                                system_core_clock_update (Thumb, 140 bytes, Stack size 16 bytes, system_at32f435_437.o(.text.system_core_clock_update))

                                [Stack]

                                • Max Depth = 16
                                • Call Chain = system_core_clock_update

                                [Calls]
                                • >>   crm_sysclk_switch_status_get @@ -981,7 +981,7 @@ Global Symbols
                                • >>   gpio_pin_mux_config
                                • >>   gpio_init
                                • >>   gpio_default_para_init -
                                • >>   crm_periph_clock_enable +
                                • >>   crm_periph_clock_enable

                                [Called By]
                                • >>   main
                                @@ -998,7 +998,7 @@ Global Symbols

                                [Called By]
                                • >>   fputc
                                -

                                usart_init (Thumb, 180 bytes, Stack size 40 bytes, at32f435_437_usart.o(.text.usart_init)) +

                                usart_init (Thumb, 166 bytes, Stack size 40 bytes, at32f435_437_usart.o(.text.usart_init))

                                [Stack]

                                • Max Depth = 56
                                • Call Chain = usart_init ⇒ crm_clocks_freq_get

                                [Calls]
                                • >>   crm_clocks_freq_get @@ -1045,8 +1045,8 @@ Global Symbols
                                  [Calls]
                                  • >>   _e2e
                                  • >>   __btod_div_common
                                  -
                                  [Called By]
                                  • >>   _fp_digits -
                                  • >>   _btod_etento +
                                    [Called By]
                                    • >>   _btod_etento +
                                    • >>   _fp_digits

                                    _btod_emul (Thumb, 42 bytes, Stack size 28 bytes, btod.o(CL$$btod_emul)) @@ -1055,8 +1055,8 @@ Global Symbols
                                    [Calls]

                                    • >>   __btod_mult_common
                                    • >>   _e2e
                                    -
                                    [Called By]
                                    • >>   _fp_digits -
                                    • >>   _btod_etento +
                                      [Called By]
                                      • >>   _btod_etento +
                                      • >>   _fp_digits

                                      __btod_mult_common (Thumb, 580 bytes, Stack size 16 bytes, btod.o(CL$$btod_mult_common)) diff --git a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/commontables.o b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/commontables.o index a5944db0..d47bb273 100644 Binary files a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/commontables.o and b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/commontables.o differ diff --git a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/complexmathfunctions.o b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/complexmathfunctions.o index 69238393..5a724c44 100644 Binary files a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/complexmathfunctions.o and b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/complexmathfunctions.o differ diff --git a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/controllerfunctions.o b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/controllerfunctions.o index 8ccc87c6..4294f0e5 100644 Binary files a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/controllerfunctions.o and b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/controllerfunctions.o differ diff --git a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/distancefunctions.o b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/distancefunctions.o index eb07b5eb..e4fd333b 100644 Binary files a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/distancefunctions.o and b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/distancefunctions.o differ diff --git a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/fastmathfunctions.o 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a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/transformfunctions.o and b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/Objects/transformfunctions.o differ diff --git a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvoptx b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvoptx index 6bfb7c34..b3b604b7 100644 --- a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvoptx +++ b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvprojx b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvprojx index 05e658e1..e0fa3cb2 100644 --- a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvprojx +++ b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/mdk_v5/cmsis_dsp.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -543,6 +543,11 @@ template + + + + + 0 1 diff --git a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/src/at32f435_437_clock.c b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/src/at32f435_437_clock.c index f4c86b5b..3eada448 100644 --- a/project/at_start_f437/examples/cortex_m4/cmsis_dsp/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/cortex_m4/cmsis_dsp/src/at32f435_437_clock.c @@ -54,6 +54,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -63,9 +66,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/cortex_m4/fpu/inc/at32f435_437_conf.h b/project/at_start_f437/examples/cortex_m4/fpu/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/cortex_m4/fpu/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/cortex_m4/fpu/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/cortex_m4/fpu/mdk_v5/fpu.uvoptx b/project/at_start_f437/examples/cortex_m4/fpu/mdk_v5/fpu.uvoptx index 4b581f62..e402077f 100644 --- a/project/at_start_f437/examples/cortex_m4/fpu/mdk_v5/fpu.uvoptx +++ b/project/at_start_f437/examples/cortex_m4/fpu/mdk_v5/fpu.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/cortex_m4/fpu/mdk_v5/fpu.uvprojx b/project/at_start_f437/examples/cortex_m4/fpu/mdk_v5/fpu.uvprojx index 42e1b1c7..2263bbf1 100644 --- a/project/at_start_f437/examples/cortex_m4/fpu/mdk_v5/fpu.uvprojx +++ b/project/at_start_f437/examples/cortex_m4/fpu/mdk_v5/fpu.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -938,6 +938,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/cortex_m4/fpu/src/at32f435_437_clock.c b/project/at_start_f437/examples/cortex_m4/fpu/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/cortex_m4/fpu/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/cortex_m4/fpu/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/cortex_m4/systick_interrupt/inc/at32f435_437_conf.h b/project/at_start_f437/examples/cortex_m4/systick_interrupt/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/cortex_m4/systick_interrupt/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/cortex_m4/systick_interrupt/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvoptx b/project/at_start_f437/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvoptx index 1504f970..79c83394 100644 --- a/project/at_start_f437/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvoptx +++ b/project/at_start_f437/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvprojx b/project/at_start_f437/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvprojx index 196f4839..1afa370f 100644 --- a/project/at_start_f437/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvprojx +++ b/project/at_start_f437/examples/cortex_m4/systick_interrupt/mdk_v5/systick_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/cortex_m4/systick_interrupt/src/at32f435_437_clock.c b/project/at_start_f437/examples/cortex_m4/systick_interrupt/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/cortex_m4/systick_interrupt/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/cortex_m4/systick_interrupt/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/crc/calculation/inc/at32f435_437_conf.h b/project/at_start_f437/examples/crc/calculation/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/crc/calculation/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/crc/calculation/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/crc/calculation/mdk_v5/calculation.uvoptx b/project/at_start_f437/examples/crc/calculation/mdk_v5/calculation.uvoptx index ac4a86b6..bb222ab4 100644 --- a/project/at_start_f437/examples/crc/calculation/mdk_v5/calculation.uvoptx +++ b/project/at_start_f437/examples/crc/calculation/mdk_v5/calculation.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/crc/calculation/mdk_v5/calculation.uvprojx b/project/at_start_f437/examples/crc/calculation/mdk_v5/calculation.uvprojx index 8ff8ff3b..ccf071dd 100644 --- a/project/at_start_f437/examples/crc/calculation/mdk_v5/calculation.uvprojx +++ b/project/at_start_f437/examples/crc/calculation/mdk_v5/calculation.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/crc/calculation/src/at32f435_437_clock.c b/project/at_start_f437/examples/crc/calculation/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/crc/calculation/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/crc/calculation/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/crm/clock_failure_detection/inc/at32f435_437_conf.h b/project/at_start_f437/examples/crm/clock_failure_detection/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/crm/clock_failure_detection/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/crm/clock_failure_detection/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvoptx b/project/at_start_f437/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvoptx index e1d66f4f..ebc97f27 100644 --- a/project/at_start_f437/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvoptx +++ b/project/at_start_f437/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvprojx b/project/at_start_f437/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvprojx index 9c016a41..f05561d0 100644 --- a/project/at_start_f437/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvprojx +++ b/project/at_start_f437/examples/crm/clock_failure_detection/mdk_v5/clock_failure_detection.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/crm/clock_failure_detection/src/at32f435_437_clock.c b/project/at_start_f437/examples/crm/clock_failure_detection/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/crm/clock_failure_detection/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/crm/clock_failure_detection/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/crm/clock_failure_detection/src/main.c b/project/at_start_f437/examples/crm/clock_failure_detection/src/main.c index 77ddff7a..f4d6608a 100644 --- a/project/at_start_f437/examples/crm/clock_failure_detection/src/main.c +++ b/project/at_start_f437/examples/crm/clock_failure_detection/src/main.c @@ -108,6 +108,9 @@ void clock_failure_detection_handler(void) */ static void sclk_288m_hick_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -117,9 +120,6 @@ static void sclk_288m_hick_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); /* wait till hick is ready */ diff --git a/project/at_start_f437/examples/crm/pll_parameter_calculate/inc/at32f435_437_conf.h b/project/at_start_f437/examples/crm/pll_parameter_calculate/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/crm/pll_parameter_calculate/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/crm/pll_parameter_calculate/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvoptx b/project/at_start_f437/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvoptx index 4b9a0f47..7cd3bc5e 100644 --- a/project/at_start_f437/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvoptx +++ b/project/at_start_f437/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvprojx b/project/at_start_f437/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvprojx index a88b5232..42097f5b 100644 --- a/project/at_start_f437/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvprojx +++ b/project/at_start_f437/examples/crm/pll_parameter_calculate/mdk_v5/pll_parameter_calculate.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/crm/pll_parameter_calculate/src/at32f435_437_clock.c b/project/at_start_f437/examples/crm/pll_parameter_calculate/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/crm/pll_parameter_calculate/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/crm/pll_parameter_calculate/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/crm/pll_parameter_calculate/src/main.c b/project/at_start_f437/examples/crm/pll_parameter_calculate/src/main.c index 30f2f3e6..fba72a42 100644 --- a/project/at_start_f437/examples/crm/pll_parameter_calculate/src/main.c +++ b/project/at_start_f437/examples/crm/pll_parameter_calculate/src/main.c @@ -85,6 +85,9 @@ void system_clock_config_200mhz(void) { uint16_t pll_ns, pll_ms, pll_fr; + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -94,9 +97,6 @@ void system_clock_config_200mhz(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/crm/sysclk_switch/inc/at32f435_437_conf.h b/project/at_start_f437/examples/crm/sysclk_switch/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/crm/sysclk_switch/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/crm/sysclk_switch/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvoptx b/project/at_start_f437/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvoptx index 5f98b24b..138e888d 100644 --- a/project/at_start_f437/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvoptx +++ b/project/at_start_f437/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvprojx b/project/at_start_f437/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvprojx index 97fd061f..695e2a36 100644 --- a/project/at_start_f437/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvprojx +++ b/project/at_start_f437/examples/crm/sysclk_switch/mdk_v5/sysclk_switch.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/crm/sysclk_switch/src/at32f435_437_clock.c b/project/at_start_f437/examples/crm/sysclk_switch/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/crm/sysclk_switch/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/crm/sysclk_switch/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/crm/sysclk_switch/src/main.c b/project/at_start_f437/examples/crm/sysclk_switch/src/main.c index eb5c581c..4a3f87cd 100644 --- a/project/at_start_f437/examples/crm/sysclk_switch/src/main.c +++ b/project/at_start_f437/examples/crm/sysclk_switch/src/main.c @@ -105,6 +105,9 @@ static void switch_system_clock(void) */ static void sclk_64m_hick_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -114,9 +117,6 @@ static void sclk_64m_hick_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); /* wait till hick is ready */ @@ -192,6 +192,9 @@ static void sclk_64m_hick_config(void) */ static void sclk_96m_hext_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -201,9 +204,6 @@ static void sclk_96m_hext_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/dac/double_mode_dma_sinewave/inc/at32f435_437_conf.h b/project/at_start_f437/examples/dac/double_mode_dma_sinewave/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/dac/double_mode_dma_sinewave/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/dac/double_mode_dma_sinewave/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvoptx b/project/at_start_f437/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvoptx index 3f96826b..6288c29a 100644 --- a/project/at_start_f437/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvoptx +++ b/project/at_start_f437/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvprojx b/project/at_start_f437/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvprojx index 337c9c93..1ec0d4d4 100644 --- a/project/at_start_f437/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvprojx +++ b/project/at_start_f437/examples/dac/double_mode_dma_sinewave/mdk_v5/double_mode_dma_sinewave.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/dac/double_mode_dma_sinewave/src/at32f435_437_clock.c b/project/at_start_f437/examples/dac/double_mode_dma_sinewave/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/dac/double_mode_dma_sinewave/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/dac/double_mode_dma_sinewave/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/dac/double_mode_dma_squarewave/inc/at32f435_437_conf.h b/project/at_start_f437/examples/dac/double_mode_dma_squarewave/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/dac/double_mode_dma_squarewave/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/dac/double_mode_dma_squarewave/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvoptx b/project/at_start_f437/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvoptx index 64c395ee..b76d016b 100644 --- a/project/at_start_f437/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvoptx +++ b/project/at_start_f437/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvprojx b/project/at_start_f437/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvprojx index 05478ed0..3a3b6d67 100644 --- a/project/at_start_f437/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvprojx +++ b/project/at_start_f437/examples/dac/double_mode_dma_squarewave/mdk_v5/double_mode_dma_squarewave.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/dac/double_mode_dma_squarewave/src/at32f435_437_clock.c b/project/at_start_f437/examples/dac/double_mode_dma_squarewave/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/dac/double_mode_dma_squarewave/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/dac/double_mode_dma_squarewave/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/dac/one_dac_dma_escalator/inc/at32f435_437_conf.h b/project/at_start_f437/examples/dac/one_dac_dma_escalator/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/dac/one_dac_dma_escalator/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/dac/one_dac_dma_escalator/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvoptx b/project/at_start_f437/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvoptx index 13dba930..c8e164d4 100644 --- a/project/at_start_f437/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvoptx +++ b/project/at_start_f437/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvprojx b/project/at_start_f437/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvprojx index 6442560f..1feb646c 100644 --- a/project/at_start_f437/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvprojx +++ b/project/at_start_f437/examples/dac/one_dac_dma_escalator/mdk_v5/one_dac_dma_escalator.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/dac/one_dac_dma_escalator/src/at32f435_437_clock.c b/project/at_start_f437/examples/dac/one_dac_dma_escalator/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/dac/one_dac_dma_escalator/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/dac/one_dac_dma_escalator/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/dac/one_dac_noisewave/inc/at32f435_437_conf.h b/project/at_start_f437/examples/dac/one_dac_noisewave/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/dac/one_dac_noisewave/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/dac/one_dac_noisewave/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvoptx b/project/at_start_f437/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvoptx index 1a6bcf34..33c57072 100644 --- a/project/at_start_f437/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvoptx +++ b/project/at_start_f437/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvprojx b/project/at_start_f437/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvprojx index 633ac411..001b7dee 100644 --- a/project/at_start_f437/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvprojx +++ b/project/at_start_f437/examples/dac/one_dac_noisewave/mdk_v5/one_dac_noisewave.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/dac/one_dac_noisewave/src/at32f435_437_clock.c b/project/at_start_f437/examples/dac/one_dac_noisewave/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/dac/one_dac_noisewave/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/dac/one_dac_noisewave/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/dac/two_dac_trianglewave/inc/at32f435_437_conf.h b/project/at_start_f437/examples/dac/two_dac_trianglewave/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/dac/two_dac_trianglewave/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/dac/two_dac_trianglewave/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvoptx b/project/at_start_f437/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvoptx index decdbef4..aa72f8c2 100644 --- a/project/at_start_f437/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvoptx +++ b/project/at_start_f437/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvprojx b/project/at_start_f437/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvprojx index f4e2ccf0..6dd5de5a 100644 --- a/project/at_start_f437/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvprojx +++ b/project/at_start_f437/examples/dac/two_dac_trianglewave/mdk_v5/two_dac_trianglewave.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/dac/two_dac_trianglewave/src/at32f435_437_clock.c b/project/at_start_f437/examples/dac/two_dac_trianglewave/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/dac/two_dac_trianglewave/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/dac/two_dac_trianglewave/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/debug/tmr1/inc/at32f435_437_conf.h b/project/at_start_f437/examples/debug/tmr1/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/debug/tmr1/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/debug/tmr1/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/debug/tmr1/mdk_v5/tmr1.uvoptx b/project/at_start_f437/examples/debug/tmr1/mdk_v5/tmr1.uvoptx index caf6487d..8d3161ac 100644 --- a/project/at_start_f437/examples/debug/tmr1/mdk_v5/tmr1.uvoptx +++ b/project/at_start_f437/examples/debug/tmr1/mdk_v5/tmr1.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/debug/tmr1/mdk_v5/tmr1.uvprojx b/project/at_start_f437/examples/debug/tmr1/mdk_v5/tmr1.uvprojx index 4e6ab631..ea394b32 100644 --- a/project/at_start_f437/examples/debug/tmr1/mdk_v5/tmr1.uvprojx +++ b/project/at_start_f437/examples/debug/tmr1/mdk_v5/tmr1.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/debug/tmr1/src/at32f435_437_clock.c b/project/at_start_f437/examples/debug/tmr1/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/debug/tmr1/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/debug/tmr1/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/dma/dmamux_data_to_gpio/inc/at32f435_437_conf.h b/project/at_start_f437/examples/dma/dmamux_data_to_gpio/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/dma/dmamux_data_to_gpio/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/dma/dmamux_data_to_gpio/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvoptx b/project/at_start_f437/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvoptx index a73fb2ab..5f54c1b7 100644 --- a/project/at_start_f437/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvoptx +++ b/project/at_start_f437/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvprojx b/project/at_start_f437/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvprojx index 171dda9b..0f8d07cc 100644 --- a/project/at_start_f437/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvprojx +++ b/project/at_start_f437/examples/dma/dmamux_data_to_gpio/mdk_v5/dmamux_data_to_gpio.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/dma/dmamux_data_to_gpio/src/at32f435_437_clock.c b/project/at_start_f437/examples/dma/dmamux_data_to_gpio/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/dma/dmamux_data_to_gpio/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/dma/dmamux_data_to_gpio/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/dma/dmamux_genertor_exint/inc/at32f435_437_conf.h b/project/at_start_f437/examples/dma/dmamux_genertor_exint/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/dma/dmamux_genertor_exint/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/dma/dmamux_genertor_exint/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx b/project/at_start_f437/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx index 3fc7e181..0ef38952 100644 --- a/project/at_start_f437/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx +++ b/project/at_start_f437/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx b/project/at_start_f437/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx index 53ce484b..ec10431a 100644 --- a/project/at_start_f437/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx +++ b/project/at_start_f437/examples/dma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/dma/dmamux_genertor_exint/src/at32f435_437_clock.c b/project/at_start_f437/examples/dma/dmamux_genertor_exint/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/dma/dmamux_genertor_exint/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/dma/dmamux_genertor_exint/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/dma/dmamux_synchronization_exint/inc/at32f435_437_conf.h b/project/at_start_f437/examples/dma/dmamux_synchronization_exint/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/dma/dmamux_synchronization_exint/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/dma/dmamux_synchronization_exint/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx b/project/at_start_f437/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx index a98d8504..c9e5fbf0 100644 --- a/project/at_start_f437/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx +++ b/project/at_start_f437/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx b/project/at_start_f437/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx index 7f39e6da..4b8a0372 100644 --- a/project/at_start_f437/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx +++ b/project/at_start_f437/examples/dma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/dma/dmamux_synchronization_exint/src/at32f435_437_clock.c b/project/at_start_f437/examples/dma/dmamux_synchronization_exint/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/dma/dmamux_synchronization_exint/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/dma/dmamux_synchronization_exint/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/dma/flash_to_sram/inc/at32f435_437_conf.h b/project/at_start_f437/examples/dma/flash_to_sram/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/dma/flash_to_sram/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/dma/flash_to_sram/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx b/project/at_start_f437/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx index 8925ccf3..d249e5d2 100644 --- a/project/at_start_f437/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx +++ b/project/at_start_f437/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx b/project/at_start_f437/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx index 452a3d40..a1630f93 100644 --- a/project/at_start_f437/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx +++ b/project/at_start_f437/examples/dma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/dma/flash_to_sram/src/at32f435_437_clock.c b/project/at_start_f437/examples/dma/flash_to_sram/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/dma/flash_to_sram/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/dma/flash_to_sram/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/dvp/ov2640_capture/inc/at32f435_437_conf.h b/project/at_start_f437/examples/dvp/ov2640_capture/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/dvp/ov2640_capture/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/dvp/ov2640_capture/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvoptx b/project/at_start_f437/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvoptx index c304b215..48dd2ef1 100644 --- a/project/at_start_f437/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvoptx +++ b/project/at_start_f437/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvprojx b/project/at_start_f437/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvprojx index 7aaa2e85..dff81db1 100644 --- a/project/at_start_f437/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvprojx +++ b/project/at_start_f437/examples/dvp/ov2640_capture/mdk_v5/ov2640_capture.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -523,6 +523,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/dvp/ov2640_capture/src/at32f435_437_clock.c b/project/at_start_f437/examples/dvp/ov2640_capture/src/at32f435_437_clock.c index 2589036e..0250becc 100644 --- a/project/at_start_f437/examples/dvp/ov2640_capture/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/dvp/ov2640_capture/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/dvp/ov5640_capture/inc/at32f435_437_conf.h b/project/at_start_f437/examples/dvp/ov5640_capture/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/dvp/ov5640_capture/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/dvp/ov5640_capture/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvoptx b/project/at_start_f437/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvoptx index 50bd9696..3ffa5cea 100644 --- a/project/at_start_f437/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvoptx +++ b/project/at_start_f437/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvprojx b/project/at_start_f437/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvprojx index b45f39ad..dc135093 100644 --- a/project/at_start_f437/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvprojx +++ b/project/at_start_f437/examples/dvp/ov5640_capture/mdk_v5/ov5640_capture.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -523,6 +523,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/dvp/ov5640_capture/src/at32f435_437_clock.c b/project/at_start_f437/examples/dvp/ov5640_capture/src/at32f435_437_clock.c index 2589036e..0250becc 100644 --- a/project/at_start_f437/examples/dvp/ov5640_capture/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/dvp/ov5640_capture/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/edma/burst_mode/inc/at32f435_437_conf.h b/project/at_start_f437/examples/edma/burst_mode/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/edma/burst_mode/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/edma/burst_mode/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/edma/burst_mode/mdk_v5/burst_mode.uvoptx b/project/at_start_f437/examples/edma/burst_mode/mdk_v5/burst_mode.uvoptx index db682a1f..f80a26c6 100644 --- a/project/at_start_f437/examples/edma/burst_mode/mdk_v5/burst_mode.uvoptx +++ b/project/at_start_f437/examples/edma/burst_mode/mdk_v5/burst_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/edma/burst_mode/mdk_v5/burst_mode.uvprojx b/project/at_start_f437/examples/edma/burst_mode/mdk_v5/burst_mode.uvprojx index 87f4b05a..6d35d1a1 100644 --- a/project/at_start_f437/examples/edma/burst_mode/mdk_v5/burst_mode.uvprojx +++ b/project/at_start_f437/examples/edma/burst_mode/mdk_v5/burst_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/edma/burst_mode/src/at32f435_437_clock.c b/project/at_start_f437/examples/edma/burst_mode/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/edma/burst_mode/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/edma/burst_mode/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/edma/dmamux_genertor_exint/inc/at32f435_437_conf.h b/project/at_start_f437/examples/edma/dmamux_genertor_exint/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/edma/dmamux_genertor_exint/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/edma/dmamux_genertor_exint/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx b/project/at_start_f437/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx index b771997f..54d86cbd 100644 --- a/project/at_start_f437/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx +++ b/project/at_start_f437/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx b/project/at_start_f437/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx index fedb6933..dff8a0c4 100644 --- a/project/at_start_f437/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx +++ b/project/at_start_f437/examples/edma/dmamux_genertor_exint/mdk_v5/dmamux_genertor_exint.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/edma/dmamux_genertor_exint/src/at32f435_437_clock.c b/project/at_start_f437/examples/edma/dmamux_genertor_exint/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/edma/dmamux_genertor_exint/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/edma/dmamux_genertor_exint/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/edma/dmamux_synchronization_exint/inc/at32f435_437_conf.h b/project/at_start_f437/examples/edma/dmamux_synchronization_exint/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/edma/dmamux_synchronization_exint/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/edma/dmamux_synchronization_exint/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx b/project/at_start_f437/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx index 608f678a..8eb4cddc 100644 --- a/project/at_start_f437/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx +++ b/project/at_start_f437/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx b/project/at_start_f437/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx index 2b711866..f2d6dfe4 100644 --- a/project/at_start_f437/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx +++ b/project/at_start_f437/examples/edma/dmamux_synchronization_exint/mdk_v5/dmamux_synchronization_exint.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/edma/dmamux_synchronization_exint/src/at32f435_437_clock.c b/project/at_start_f437/examples/edma/dmamux_synchronization_exint/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/edma/dmamux_synchronization_exint/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/edma/dmamux_synchronization_exint/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/edma/flash_to_sram/inc/at32f435_437_conf.h b/project/at_start_f437/examples/edma/flash_to_sram/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/edma/flash_to_sram/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/edma/flash_to_sram/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx b/project/at_start_f437/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx index bf4375e1..2cbb2c5a 100644 --- a/project/at_start_f437/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx +++ b/project/at_start_f437/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx b/project/at_start_f437/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx index a38b7628..c6ebf3f8 100644 --- a/project/at_start_f437/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx +++ b/project/at_start_f437/examples/edma/flash_to_sram/mdk_v5/flash_to_sram.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/edma/flash_to_sram/src/at32f435_437_clock.c b/project/at_start_f437/examples/edma/flash_to_sram/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/edma/flash_to_sram/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/edma/flash_to_sram/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/inc/at32f435_437_conf.h b/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvoptx b/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvoptx index c102eabb..ad2f2b4c 100644 --- a/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvoptx +++ b/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvprojx b/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvprojx index b3b734a3..1fada2af 100644 --- a/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvprojx +++ b/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/mdk_v5/i2s_halfduplex_edma_doublebuffer.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/src/at32f435_437_clock.c b/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/edma/i2s_halfduplex_edma_doublebuffer/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/edma/link_list_mode/inc/at32f435_437_conf.h b/project/at_start_f437/examples/edma/link_list_mode/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/edma/link_list_mode/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/edma/link_list_mode/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvoptx b/project/at_start_f437/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvoptx index 7907014d..d0450d94 100644 --- a/project/at_start_f437/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvoptx +++ b/project/at_start_f437/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvprojx b/project/at_start_f437/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvprojx index 4fd8258a..184457e0 100644 --- a/project/at_start_f437/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvprojx +++ b/project/at_start_f437/examples/edma/link_list_mode/mdk_v5/link_list_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/edma/link_list_mode/src/at32f435_437_clock.c b/project/at_start_f437/examples/edma/link_list_mode/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/edma/link_list_mode/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/edma/link_list_mode/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/edma/two_dimension_mode/inc/at32f435_437_conf.h b/project/at_start_f437/examples/edma/two_dimension_mode/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/edma/two_dimension_mode/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/edma/two_dimension_mode/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvoptx b/project/at_start_f437/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvoptx index d1b0a072..e345408f 100644 --- a/project/at_start_f437/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvoptx +++ b/project/at_start_f437/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvprojx b/project/at_start_f437/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvprojx index e3e7a46a..19523e01 100644 --- a/project/at_start_f437/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvprojx +++ b/project/at_start_f437/examples/edma/two_dimension_mode/mdk_v5/two_dimension_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/edma/two_dimension_mode/src/at32f435_437_clock.c b/project/at_start_f437/examples/edma/two_dimension_mode/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/edma/two_dimension_mode/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/edma/two_dimension_mode/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/emac/dns_client/inc/at32f435_437_conf.h b/project/at_start_f437/examples/emac/dns_client/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/emac/dns_client/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/emac/dns_client/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/emac/dns_client/inc/lwipopts.h b/project/at_start_f437/examples/emac/dns_client/inc/lwipopts.h index f9e17b32..47bd41c5 100644 --- a/project/at_start_f437/examples/emac/dns_client/inc/lwipopts.h +++ b/project/at_start_f437/examples/emac/dns_client/inc/lwipopts.h @@ -133,4 +133,9 @@ #define CHECKSUM_GEN_ICMP 1 #endif +/** + * LWIP_NOASSERT: Disable LWIP_ASSERT checks: + */ +#define LWIP_NOASSERT + #endif /* LWIP_HDR_LWIPOPTS_H */ diff --git a/project/at_start_f437/examples/emac/dns_client/mdk_v5/dns_client.uvoptx b/project/at_start_f437/examples/emac/dns_client/mdk_v5/dns_client.uvoptx index e0d43cad..08887444 100644 --- a/project/at_start_f437/examples/emac/dns_client/mdk_v5/dns_client.uvoptx +++ b/project/at_start_f437/examples/emac/dns_client/mdk_v5/dns_client.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/emac/dns_client/mdk_v5/dns_client.uvprojx b/project/at_start_f437/examples/emac/dns_client/mdk_v5/dns_client.uvprojx index 16a0a107..6d11514b 100644 --- a/project/at_start_f437/examples/emac/dns_client/mdk_v5/dns_client.uvprojx +++ b/project/at_start_f437/examples/emac/dns_client/mdk_v5/dns_client.uvprojx @@ -10,13 +10,13 @@ dns_client 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC 0 -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -48,7 +48,7 @@ 1 .\objects\ - telnet + dns_client 1 0 1 @@ -708,6 +708,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/emac/dns_client/src/at32f435_437_clock.c b/project/at_start_f437/examples/emac/dns_client/src/at32f435_437_clock.c index f58450d1..392c95f0 100644 --- a/project/at_start_f437/examples/emac/dns_client/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/emac/dns_client/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/emac/dns_client/src/netconf.c b/project/at_start_f437/examples/emac/dns_client/src/netconf.c index ca85de85..5016dba0 100644 --- a/project/at_start_f437/examples/emac/dns_client/src/netconf.c +++ b/project/at_start_f437/examples/emac/dns_client/src/netconf.c @@ -139,10 +139,7 @@ void tcpip_stack_init(void) void lwip_pkt_handle(void) { /* Read a received packet from the Ethernet buffers and send it to the lwIP for handling */ - if(ethernetif_input(&netif) != ERR_OK) - { - while(1); - } + ethernetif_input(&netif); } /** @@ -153,10 +150,7 @@ void lwip_pkt_handle(void) void lwip_rx_loop_handler(void) { /* handles all the received frames */ - while(emac_received_packet_size_get() != 0) - { - lwip_pkt_handle(); - } + lwip_pkt_handle(); } /** diff --git a/project/at_start_f437/examples/emac/http_server/inc/at32f435_437_conf.h b/project/at_start_f437/examples/emac/http_server/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/emac/http_server/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/emac/http_server/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/emac/http_server/inc/lwipopts.h b/project/at_start_f437/examples/emac/http_server/inc/lwipopts.h index f9e17b32..47bd41c5 100644 --- a/project/at_start_f437/examples/emac/http_server/inc/lwipopts.h +++ b/project/at_start_f437/examples/emac/http_server/inc/lwipopts.h @@ -133,4 +133,9 @@ #define CHECKSUM_GEN_ICMP 1 #endif +/** + * LWIP_NOASSERT: Disable LWIP_ASSERT checks: + */ +#define LWIP_NOASSERT + #endif /* LWIP_HDR_LWIPOPTS_H */ diff --git a/project/at_start_f437/examples/emac/http_server/mdk_v5/http_server.uvoptx b/project/at_start_f437/examples/emac/http_server/mdk_v5/http_server.uvoptx index 073cfa10..15b5c6b2 100644 --- a/project/at_start_f437/examples/emac/http_server/mdk_v5/http_server.uvoptx +++ b/project/at_start_f437/examples/emac/http_server/mdk_v5/http_server.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/emac/http_server/mdk_v5/http_server.uvprojx b/project/at_start_f437/examples/emac/http_server/mdk_v5/http_server.uvprojx index 50ebc759..ec9fde27 100644 --- a/project/at_start_f437/examples/emac/http_server/mdk_v5/http_server.uvprojx +++ b/project/at_start_f437/examples/emac/http_server/mdk_v5/http_server.uvprojx @@ -10,13 +10,13 @@ http_server 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC 0 -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -48,7 +48,7 @@ 1 .\objects\ - telnet + http_server 1 0 1 @@ -728,6 +728,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/emac/http_server/src/at32f435_437_clock.c b/project/at_start_f437/examples/emac/http_server/src/at32f435_437_clock.c index f58450d1..392c95f0 100644 --- a/project/at_start_f437/examples/emac/http_server/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/emac/http_server/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/emac/http_server/src/main.c b/project/at_start_f437/examples/emac/http_server/src/main.c index 1cbaa1fb..973d2f88 100644 --- a/project/at_start_f437/examples/emac/http_server/src/main.c +++ b/project/at_start_f437/examples/emac/http_server/src/main.c @@ -61,6 +61,8 @@ int main(void) nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); delay_init(); + + uart_print_init(115200); status = emac_system_init(); diff --git a/project/at_start_f437/examples/emac/http_server/src/netconf.c b/project/at_start_f437/examples/emac/http_server/src/netconf.c index 881eebf0..437d21ea 100644 --- a/project/at_start_f437/examples/emac/http_server/src/netconf.c +++ b/project/at_start_f437/examples/emac/http_server/src/netconf.c @@ -135,10 +135,7 @@ void tcpip_stack_init(void) void lwip_pkt_handle(void) { /* Read a received packet from the Ethernet buffers and send it to the lwIP for handling */ - if(ethernetif_input(&netif) != ERR_OK) - { - while(1); - } + ethernetif_input(&netif); } /** @@ -149,10 +146,7 @@ void lwip_pkt_handle(void) void lwip_rx_loop_handler(void) { /* handles all the received frames */ - while(emac_received_packet_size_get() != 0) - { - lwip_pkt_handle(); - } + lwip_pkt_handle(); } /** diff --git a/project/at_start_f437/examples/emac/iperf/inc/at32f435_437_conf.h b/project/at_start_f437/examples/emac/iperf/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/emac/iperf/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/emac/iperf/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/emac/iperf/inc/lwipopts.h b/project/at_start_f437/examples/emac/iperf/inc/lwipopts.h index f9e17b32..47bd41c5 100644 --- a/project/at_start_f437/examples/emac/iperf/inc/lwipopts.h +++ b/project/at_start_f437/examples/emac/iperf/inc/lwipopts.h @@ -133,4 +133,9 @@ #define CHECKSUM_GEN_ICMP 1 #endif +/** + * LWIP_NOASSERT: Disable LWIP_ASSERT checks: + */ +#define LWIP_NOASSERT + #endif /* LWIP_HDR_LWIPOPTS_H */ diff --git a/project/at_start_f437/examples/emac/iperf/mdk_v5/iperf.uvoptx b/project/at_start_f437/examples/emac/iperf/mdk_v5/iperf.uvoptx index f724d9ee..a63d8ce7 100644 --- a/project/at_start_f437/examples/emac/iperf/mdk_v5/iperf.uvoptx +++ b/project/at_start_f437/examples/emac/iperf/mdk_v5/iperf.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/emac/iperf/mdk_v5/iperf.uvprojx b/project/at_start_f437/examples/emac/iperf/mdk_v5/iperf.uvprojx index 5ebb8be0..52537eba 100644 --- a/project/at_start_f437/examples/emac/iperf/mdk_v5/iperf.uvprojx +++ b/project/at_start_f437/examples/emac/iperf/mdk_v5/iperf.uvprojx @@ -10,13 +10,13 @@ iperf 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC 0 -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -48,7 +48,7 @@ 1 .\objects\ - telnet + iperf 1 0 1 @@ -713,6 +713,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/emac/iperf/src/at32f435_437_clock.c b/project/at_start_f437/examples/emac/iperf/src/at32f435_437_clock.c index f58450d1..392c95f0 100644 --- a/project/at_start_f437/examples/emac/iperf/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/emac/iperf/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/emac/iperf/src/main.c b/project/at_start_f437/examples/emac/iperf/src/main.c index ecd90134..defe2d62 100644 --- a/project/at_start_f437/examples/emac/iperf/src/main.c +++ b/project/at_start_f437/examples/emac/iperf/src/main.c @@ -54,6 +54,8 @@ int main(void) system_clock_config(); at32_board_init(); + + uart_print_init(115200); nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); diff --git a/project/at_start_f437/examples/emac/iperf/src/netconf.c b/project/at_start_f437/examples/emac/iperf/src/netconf.c index 700dffe3..96b3be74 100644 --- a/project/at_start_f437/examples/emac/iperf/src/netconf.c +++ b/project/at_start_f437/examples/emac/iperf/src/netconf.c @@ -135,10 +135,7 @@ void tcpip_stack_init(void) void lwip_pkt_handle(void) { /* Read a received packet from the Ethernet buffers and send it to the lwIP for handling */ - if(ethernetif_input(&netif) != ERR_OK) - { - while(1); - } + ethernetif_input(&netif); } /** @@ -149,10 +146,7 @@ void lwip_pkt_handle(void) void lwip_rx_loop_handler(void) { /* handles all the received frames */ - while(emac_received_packet_size_get() != 0) - { - lwip_pkt_handle(); - } + lwip_pkt_handle(); } /** diff --git a/project/at_start_f437/examples/emac/mqtt_client/inc/at32f435_437_conf.h b/project/at_start_f437/examples/emac/mqtt_client/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/emac/mqtt_client/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/emac/mqtt_client/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/emac/mqtt_client/inc/lwipopts.h b/project/at_start_f437/examples/emac/mqtt_client/inc/lwipopts.h index f9e17b32..47bd41c5 100644 --- a/project/at_start_f437/examples/emac/mqtt_client/inc/lwipopts.h +++ b/project/at_start_f437/examples/emac/mqtt_client/inc/lwipopts.h @@ -133,4 +133,9 @@ #define CHECKSUM_GEN_ICMP 1 #endif +/** + * LWIP_NOASSERT: Disable LWIP_ASSERT checks: + */ +#define LWIP_NOASSERT + #endif /* LWIP_HDR_LWIPOPTS_H */ diff --git a/project/at_start_f437/examples/emac/mqtt_client/mdk_v5/mqtt_client.uvoptx b/project/at_start_f437/examples/emac/mqtt_client/mdk_v5/mqtt_client.uvoptx index bf0733c0..76572e29 100644 --- a/project/at_start_f437/examples/emac/mqtt_client/mdk_v5/mqtt_client.uvoptx +++ b/project/at_start_f437/examples/emac/mqtt_client/mdk_v5/mqtt_client.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/emac/mqtt_client/mdk_v5/mqtt_client.uvprojx b/project/at_start_f437/examples/emac/mqtt_client/mdk_v5/mqtt_client.uvprojx index f483923b..8d3a67f3 100644 --- a/project/at_start_f437/examples/emac/mqtt_client/mdk_v5/mqtt_client.uvprojx +++ b/project/at_start_f437/examples/emac/mqtt_client/mdk_v5/mqtt_client.uvprojx @@ -10,13 +10,13 @@ mqtt_client 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC 0 -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -718,6 +718,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/emac/mqtt_client/src/at32f435_437_clock.c b/project/at_start_f437/examples/emac/mqtt_client/src/at32f435_437_clock.c index f58450d1..392c95f0 100644 --- a/project/at_start_f437/examples/emac/mqtt_client/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/emac/mqtt_client/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/emac/mqtt_client/src/netconf.c b/project/at_start_f437/examples/emac/mqtt_client/src/netconf.c index 8fa49677..6a8fd42f 100644 --- a/project/at_start_f437/examples/emac/mqtt_client/src/netconf.c +++ b/project/at_start_f437/examples/emac/mqtt_client/src/netconf.c @@ -141,10 +141,7 @@ void tcpip_stack_init(void) void lwip_pkt_handle(void) { /* Read a received packet from the Ethernet buffers and send it to the lwIP for handling */ - if(ethernetif_input(&netif) != ERR_OK) - { - while(1); - } + ethernetif_input(&netif); } /** @@ -155,10 +152,7 @@ void lwip_pkt_handle(void) void lwip_rx_loop_handler(void) { /* handles all the received frames */ - while(emac_received_packet_size_get() != 0) - { - lwip_pkt_handle(); - } + lwip_pkt_handle(); } /** diff --git a/project/at_start_f437/examples/emac/tcp_client/inc/at32f435_437_conf.h b/project/at_start_f437/examples/emac/tcp_client/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/emac/tcp_client/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/emac/tcp_client/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/emac/tcp_client/inc/lwipopts.h b/project/at_start_f437/examples/emac/tcp_client/inc/lwipopts.h index f9e17b32..47bd41c5 100644 --- a/project/at_start_f437/examples/emac/tcp_client/inc/lwipopts.h +++ b/project/at_start_f437/examples/emac/tcp_client/inc/lwipopts.h @@ -133,4 +133,9 @@ #define CHECKSUM_GEN_ICMP 1 #endif +/** + * LWIP_NOASSERT: Disable LWIP_ASSERT checks: + */ +#define LWIP_NOASSERT + #endif /* LWIP_HDR_LWIPOPTS_H */ diff --git a/project/at_start_f437/examples/emac/tcp_client/mdk_v5/tcp_client.uvoptx b/project/at_start_f437/examples/emac/tcp_client/mdk_v5/tcp_client.uvoptx index 8aa0e8b9..a477aa8e 100644 --- a/project/at_start_f437/examples/emac/tcp_client/mdk_v5/tcp_client.uvoptx +++ b/project/at_start_f437/examples/emac/tcp_client/mdk_v5/tcp_client.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/emac/tcp_client/mdk_v5/tcp_client.uvprojx b/project/at_start_f437/examples/emac/tcp_client/mdk_v5/tcp_client.uvprojx index 1e6a2e77..b021d8cb 100644 --- a/project/at_start_f437/examples/emac/tcp_client/mdk_v5/tcp_client.uvprojx +++ b/project/at_start_f437/examples/emac/tcp_client/mdk_v5/tcp_client.uvprojx @@ -10,13 +10,13 @@ tcp_client 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC 0 -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -48,7 +48,7 @@ 1 .\objects\ - telnet + tcp_client 1 0 1 @@ -713,6 +713,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/emac/tcp_client/src/at32f435_437_clock.c b/project/at_start_f437/examples/emac/tcp_client/src/at32f435_437_clock.c index f58450d1..392c95f0 100644 --- a/project/at_start_f437/examples/emac/tcp_client/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/emac/tcp_client/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/emac/tcp_client/src/main.c b/project/at_start_f437/examples/emac/tcp_client/src/main.c index 0962af34..89644fd0 100644 --- a/project/at_start_f437/examples/emac/tcp_client/src/main.c +++ b/project/at_start_f437/examples/emac/tcp_client/src/main.c @@ -54,6 +54,8 @@ int main(void) system_clock_config(); at32_board_init(); + + uart_print_init(115200); nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); diff --git a/project/at_start_f437/examples/emac/tcp_client/src/netconf.c b/project/at_start_f437/examples/emac/tcp_client/src/netconf.c index 91291ef8..0b0c401c 100644 --- a/project/at_start_f437/examples/emac/tcp_client/src/netconf.c +++ b/project/at_start_f437/examples/emac/tcp_client/src/netconf.c @@ -138,10 +138,7 @@ void tcpip_stack_init(void) void lwip_pkt_handle(void) { /* Read a received packet from the Ethernet buffers and send it to the lwIP for handling */ - if(ethernetif_input(&netif) != ERR_OK) - { - while(1); - } + ethernetif_input(&netif); } /** @@ -152,10 +149,7 @@ void lwip_pkt_handle(void) void lwip_rx_loop_handler(void) { /* handles all the received frames */ - while(emac_received_packet_size_get() != 0) - { - lwip_pkt_handle(); - } + lwip_pkt_handle(); } /** diff --git a/project/at_start_f437/examples/emac/tcp_server/inc/at32f435_437_conf.h b/project/at_start_f437/examples/emac/tcp_server/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/emac/tcp_server/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/emac/tcp_server/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/emac/tcp_server/inc/lwipopts.h b/project/at_start_f437/examples/emac/tcp_server/inc/lwipopts.h index f9e17b32..47bd41c5 100644 --- a/project/at_start_f437/examples/emac/tcp_server/inc/lwipopts.h +++ b/project/at_start_f437/examples/emac/tcp_server/inc/lwipopts.h @@ -133,4 +133,9 @@ #define CHECKSUM_GEN_ICMP 1 #endif +/** + * LWIP_NOASSERT: Disable LWIP_ASSERT checks: + */ +#define LWIP_NOASSERT + #endif /* LWIP_HDR_LWIPOPTS_H */ diff --git a/project/at_start_f437/examples/emac/tcp_server/mdk_v5/tcp_server.uvoptx b/project/at_start_f437/examples/emac/tcp_server/mdk_v5/tcp_server.uvoptx index d2deb538..9b3ed137 100644 --- a/project/at_start_f437/examples/emac/tcp_server/mdk_v5/tcp_server.uvoptx +++ b/project/at_start_f437/examples/emac/tcp_server/mdk_v5/tcp_server.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/emac/tcp_server/mdk_v5/tcp_server.uvprojx b/project/at_start_f437/examples/emac/tcp_server/mdk_v5/tcp_server.uvprojx index a7e51b09..aa48d24c 100644 --- a/project/at_start_f437/examples/emac/tcp_server/mdk_v5/tcp_server.uvprojx +++ b/project/at_start_f437/examples/emac/tcp_server/mdk_v5/tcp_server.uvprojx @@ -10,13 +10,13 @@ tcp_server 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC 0 -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -48,7 +48,7 @@ 1 .\objects\ - telnet + tcp_server 1 0 1 @@ -713,6 +713,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/emac/tcp_server/src/at32f435_437_clock.c b/project/at_start_f437/examples/emac/tcp_server/src/at32f435_437_clock.c index f58450d1..392c95f0 100644 --- a/project/at_start_f437/examples/emac/tcp_server/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/emac/tcp_server/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/emac/tcp_server/src/main.c b/project/at_start_f437/examples/emac/tcp_server/src/main.c index 9f806ee4..a1cbd0d2 100644 --- a/project/at_start_f437/examples/emac/tcp_server/src/main.c +++ b/project/at_start_f437/examples/emac/tcp_server/src/main.c @@ -54,6 +54,8 @@ int main(void) system_clock_config(); at32_board_init(); + + uart_print_init(115200); nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); diff --git a/project/at_start_f437/examples/emac/tcp_server/src/netconf.c b/project/at_start_f437/examples/emac/tcp_server/src/netconf.c index af5c4fe0..c1c03ce5 100644 --- a/project/at_start_f437/examples/emac/tcp_server/src/netconf.c +++ b/project/at_start_f437/examples/emac/tcp_server/src/netconf.c @@ -135,10 +135,7 @@ void tcpip_stack_init(void) void lwip_pkt_handle(void) { /* Read a received packet from the Ethernet buffers and send it to the lwIP for handling */ - if(ethernetif_input(&netif) != ERR_OK) - { - while(1); - } + ethernetif_input(&netif); } /** @@ -149,10 +146,7 @@ void lwip_pkt_handle(void) void lwip_rx_loop_handler(void) { /* handles all the received frames */ - while(emac_received_packet_size_get() != 0) - { - lwip_pkt_handle(); - } + lwip_pkt_handle(); } /** diff --git a/project/at_start_f437/examples/emac/telnet/inc/at32f435_437_conf.h b/project/at_start_f437/examples/emac/telnet/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/emac/telnet/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/emac/telnet/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/emac/telnet/inc/lwipopts.h b/project/at_start_f437/examples/emac/telnet/inc/lwipopts.h index f9e17b32..47bd41c5 100644 --- a/project/at_start_f437/examples/emac/telnet/inc/lwipopts.h +++ b/project/at_start_f437/examples/emac/telnet/inc/lwipopts.h @@ -133,4 +133,9 @@ #define CHECKSUM_GEN_ICMP 1 #endif +/** + * LWIP_NOASSERT: Disable LWIP_ASSERT checks: + */ +#define LWIP_NOASSERT + #endif /* LWIP_HDR_LWIPOPTS_H */ diff --git a/project/at_start_f437/examples/emac/telnet/mdk_v5/telnet.uvoptx b/project/at_start_f437/examples/emac/telnet/mdk_v5/telnet.uvoptx index 4e84784a..65fc4766 100644 --- a/project/at_start_f437/examples/emac/telnet/mdk_v5/telnet.uvoptx +++ b/project/at_start_f437/examples/emac/telnet/mdk_v5/telnet.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/emac/telnet/mdk_v5/telnet.uvprojx b/project/at_start_f437/examples/emac/telnet/mdk_v5/telnet.uvprojx index 81d3dbaf..d319372f 100644 --- a/project/at_start_f437/examples/emac/telnet/mdk_v5/telnet.uvprojx +++ b/project/at_start_f437/examples/emac/telnet/mdk_v5/telnet.uvprojx @@ -10,13 +10,13 @@ telnet 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC 0 -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -713,6 +713,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/emac/telnet/src/at32f435_437_clock.c b/project/at_start_f437/examples/emac/telnet/src/at32f435_437_clock.c index f58450d1..392c95f0 100644 --- a/project/at_start_f437/examples/emac/telnet/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/emac/telnet/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/emac/telnet/src/main.c b/project/at_start_f437/examples/emac/telnet/src/main.c index c080b054..4fd6968d 100644 --- a/project/at_start_f437/examples/emac/telnet/src/main.c +++ b/project/at_start_f437/examples/emac/telnet/src/main.c @@ -54,6 +54,8 @@ int main(void) system_clock_config(); at32_board_init(); + + uart_print_init(115200); nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); diff --git a/project/at_start_f437/examples/emac/telnet/src/netconf.c b/project/at_start_f437/examples/emac/telnet/src/netconf.c index 967a5c9c..9450fc6e 100644 --- a/project/at_start_f437/examples/emac/telnet/src/netconf.c +++ b/project/at_start_f437/examples/emac/telnet/src/netconf.c @@ -135,10 +135,7 @@ void tcpip_stack_init(void) void lwip_pkt_handle(void) { /* Read a received packet from the Ethernet buffers and send it to the lwIP for handling */ - if(ethernetif_input(&netif) != ERR_OK) - { - while(1); - } + ethernetif_input(&netif); } /** @@ -149,10 +146,7 @@ void lwip_pkt_handle(void) void lwip_rx_loop_handler(void) { /* handles all the received frames */ - while(emac_received_packet_size_get() != 0) - { - lwip_pkt_handle(); - } + lwip_pkt_handle(); } /** diff --git a/project/at_start_f437/examples/emac/wake_on_lan/inc/at32f435_437_conf.h b/project/at_start_f437/examples/emac/wake_on_lan/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/emac/wake_on_lan/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/emac/wake_on_lan/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/emac/wake_on_lan/inc/lwipopts.h b/project/at_start_f437/examples/emac/wake_on_lan/inc/lwipopts.h index f9e17b32..47bd41c5 100644 --- a/project/at_start_f437/examples/emac/wake_on_lan/inc/lwipopts.h +++ b/project/at_start_f437/examples/emac/wake_on_lan/inc/lwipopts.h @@ -133,4 +133,9 @@ #define CHECKSUM_GEN_ICMP 1 #endif +/** + * LWIP_NOASSERT: Disable LWIP_ASSERT checks: + */ +#define LWIP_NOASSERT + #endif /* LWIP_HDR_LWIPOPTS_H */ diff --git a/project/at_start_f437/examples/emac/wake_on_lan/mdk_v5/wake_on_lan.uvoptx b/project/at_start_f437/examples/emac/wake_on_lan/mdk_v5/wake_on_lan.uvoptx index 77893ffd..00742537 100644 --- a/project/at_start_f437/examples/emac/wake_on_lan/mdk_v5/wake_on_lan.uvoptx +++ b/project/at_start_f437/examples/emac/wake_on_lan/mdk_v5/wake_on_lan.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/emac/wake_on_lan/mdk_v5/wake_on_lan.uvprojx b/project/at_start_f437/examples/emac/wake_on_lan/mdk_v5/wake_on_lan.uvprojx index d7a35e5e..4994873c 100644 --- a/project/at_start_f437/examples/emac/wake_on_lan/mdk_v5/wake_on_lan.uvprojx +++ b/project/at_start_f437/examples/emac/wake_on_lan/mdk_v5/wake_on_lan.uvprojx @@ -10,13 +10,13 @@ wake_on_lan 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC 0 -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -48,7 +48,7 @@ 1 .\objects\ - telnet + wake_on_lan 1 0 1 @@ -713,6 +713,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/emac/wake_on_lan/src/at32f435_437_clock.c b/project/at_start_f437/examples/emac/wake_on_lan/src/at32f435_437_clock.c index f58450d1..392c95f0 100644 --- a/project/at_start_f437/examples/emac/wake_on_lan/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/emac/wake_on_lan/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/emac/wake_on_lan/src/main.c b/project/at_start_f437/examples/emac/wake_on_lan/src/main.c index 572017ca..dfbab68d 100644 --- a/project/at_start_f437/examples/emac/wake_on_lan/src/main.c +++ b/project/at_start_f437/examples/emac/wake_on_lan/src/main.c @@ -57,7 +57,9 @@ int main(void) system_clock_config(); at32_board_init(); - + + uart_print_init(115200); + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); delay_init(); diff --git a/project/at_start_f437/examples/emac/wake_on_lan/src/netconf.c b/project/at_start_f437/examples/emac/wake_on_lan/src/netconf.c index e88d9f8d..22c54a4c 100644 --- a/project/at_start_f437/examples/emac/wake_on_lan/src/netconf.c +++ b/project/at_start_f437/examples/emac/wake_on_lan/src/netconf.c @@ -135,10 +135,7 @@ void tcpip_stack_init(void) void lwip_pkt_handle(void) { /* Read a received packet from the Ethernet buffers and send it to the lwIP for handling */ - if(ethernetif_input(&netif) != ERR_OK) - { - while(1); - } + ethernetif_input(&netif); } /** @@ -149,10 +146,7 @@ void lwip_pkt_handle(void) void lwip_rx_loop_handler(void) { /* handles all the received frames */ - while(emac_received_packet_size_get() != 0) - { - lwip_pkt_handle(); - } + lwip_pkt_handle(); } /** diff --git a/project/at_start_f437/examples/ertc/bpr_domain/inc/at32f435_437_conf.h b/project/at_start_f437/examples/ertc/bpr_domain/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/ertc/bpr_domain/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/ertc/bpr_domain/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvoptx b/project/at_start_f437/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvoptx index 61615e40..d0b04a1f 100644 --- a/project/at_start_f437/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvoptx +++ b/project/at_start_f437/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvprojx b/project/at_start_f437/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvprojx index 9cae6904..71c85204 100644 --- a/project/at_start_f437/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvprojx +++ b/project/at_start_f437/examples/ertc/bpr_domain/mdk_v5/bpr_domain.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/ertc/bpr_domain/src/at32f435_437_clock.c b/project/at_start_f437/examples/ertc/bpr_domain/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/ertc/bpr_domain/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/ertc/bpr_domain/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/ertc/calendar/inc/at32f435_437_conf.h b/project/at_start_f437/examples/ertc/calendar/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/ertc/calendar/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/ertc/calendar/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/ertc/calendar/mdk_v5/calendar.uvoptx b/project/at_start_f437/examples/ertc/calendar/mdk_v5/calendar.uvoptx index e83afdad..d0914d0d 100644 --- a/project/at_start_f437/examples/ertc/calendar/mdk_v5/calendar.uvoptx +++ b/project/at_start_f437/examples/ertc/calendar/mdk_v5/calendar.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/ertc/calendar/mdk_v5/calendar.uvprojx b/project/at_start_f437/examples/ertc/calendar/mdk_v5/calendar.uvprojx index 882f2c7b..60ae67e8 100644 --- a/project/at_start_f437/examples/ertc/calendar/mdk_v5/calendar.uvprojx +++ b/project/at_start_f437/examples/ertc/calendar/mdk_v5/calendar.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/ertc/calendar/src/at32f435_437_clock.c b/project/at_start_f437/examples/ertc/calendar/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/ertc/calendar/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/ertc/calendar/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/ertc/lick_calibration/inc/at32f435_437_conf.h b/project/at_start_f437/examples/ertc/lick_calibration/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/ertc/lick_calibration/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/ertc/lick_calibration/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvoptx b/project/at_start_f437/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvoptx index 1a902821..db195760 100644 --- a/project/at_start_f437/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvoptx +++ b/project/at_start_f437/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvprojx b/project/at_start_f437/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvprojx index 29aa0380..e0c7b361 100644 --- a/project/at_start_f437/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvprojx +++ b/project/at_start_f437/examples/ertc/lick_calibration/mdk_v5/lick_calibration.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/ertc/lick_calibration/src/at32f435_437_clock.c b/project/at_start_f437/examples/ertc/lick_calibration/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/ertc/lick_calibration/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/ertc/lick_calibration/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/ertc/tamper/inc/at32f435_437_conf.h b/project/at_start_f437/examples/ertc/tamper/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/ertc/tamper/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/ertc/tamper/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/ertc/tamper/mdk_v5/tamper.uvoptx b/project/at_start_f437/examples/ertc/tamper/mdk_v5/tamper.uvoptx index ce834a21..d6492500 100644 --- a/project/at_start_f437/examples/ertc/tamper/mdk_v5/tamper.uvoptx +++ b/project/at_start_f437/examples/ertc/tamper/mdk_v5/tamper.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/ertc/tamper/mdk_v5/tamper.uvprojx b/project/at_start_f437/examples/ertc/tamper/mdk_v5/tamper.uvprojx index cb0c37e0..ed4e4e5e 100644 --- a/project/at_start_f437/examples/ertc/tamper/mdk_v5/tamper.uvprojx +++ b/project/at_start_f437/examples/ertc/tamper/mdk_v5/tamper.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/ertc/tamper/src/at32f435_437_clock.c b/project/at_start_f437/examples/ertc/tamper/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/ertc/tamper/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/ertc/tamper/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/ertc/time_stamp/inc/at32f435_437_conf.h b/project/at_start_f437/examples/ertc/time_stamp/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/ertc/time_stamp/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/ertc/time_stamp/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/ertc/time_stamp/mdk_v5/time_stamp.uvoptx b/project/at_start_f437/examples/ertc/time_stamp/mdk_v5/time_stamp.uvoptx index 0dc7b75f..027e99cd 100644 --- a/project/at_start_f437/examples/ertc/time_stamp/mdk_v5/time_stamp.uvoptx +++ b/project/at_start_f437/examples/ertc/time_stamp/mdk_v5/time_stamp.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/ertc/time_stamp/mdk_v5/time_stamp.uvprojx b/project/at_start_f437/examples/ertc/time_stamp/mdk_v5/time_stamp.uvprojx index 4219d649..348553e2 100644 --- a/project/at_start_f437/examples/ertc/time_stamp/mdk_v5/time_stamp.uvprojx +++ b/project/at_start_f437/examples/ertc/time_stamp/mdk_v5/time_stamp.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/ertc/time_stamp/src/at32f435_437_clock.c b/project/at_start_f437/examples/ertc/time_stamp/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/ertc/time_stamp/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/ertc/time_stamp/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/ertc/wakeup_timer/inc/at32f435_437_conf.h b/project/at_start_f437/examples/ertc/wakeup_timer/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/ertc/wakeup_timer/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/ertc/wakeup_timer/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvoptx b/project/at_start_f437/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvoptx index a28cbba6..f01c1765 100644 --- a/project/at_start_f437/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvoptx +++ b/project/at_start_f437/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvprojx b/project/at_start_f437/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvprojx index 16dda71e..9e5b5b25 100644 --- a/project/at_start_f437/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvprojx +++ b/project/at_start_f437/examples/ertc/wakeup_timer/mdk_v5/wakeup_timer.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/ertc/wakeup_timer/src/at32f435_437_clock.c b/project/at_start_f437/examples/ertc/wakeup_timer/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/ertc/wakeup_timer/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/ertc/wakeup_timer/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/exint/exint_config/inc/at32f435_437_conf.h b/project/at_start_f437/examples/exint/exint_config/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/exint/exint_config/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/exint/exint_config/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/exint/exint_config/mdk_v5/exint_config.uvoptx b/project/at_start_f437/examples/exint/exint_config/mdk_v5/exint_config.uvoptx index 5b3984a6..3a124ecf 100644 --- a/project/at_start_f437/examples/exint/exint_config/mdk_v5/exint_config.uvoptx +++ b/project/at_start_f437/examples/exint/exint_config/mdk_v5/exint_config.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/exint/exint_config/mdk_v5/exint_config.uvprojx b/project/at_start_f437/examples/exint/exint_config/mdk_v5/exint_config.uvprojx index 2dcdf493..14905b9d 100644 --- a/project/at_start_f437/examples/exint/exint_config/mdk_v5/exint_config.uvprojx +++ b/project/at_start_f437/examples/exint/exint_config/mdk_v5/exint_config.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/exint/exint_config/src/at32f435_437_clock.c b/project/at_start_f437/examples/exint/exint_config/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/exint/exint_config/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/exint/exint_config/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/exint/exint_software_trigger/inc/at32f435_437_conf.h b/project/at_start_f437/examples/exint/exint_software_trigger/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/exint/exint_software_trigger/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/exint/exint_software_trigger/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvoptx b/project/at_start_f437/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvoptx index 1d38dcbc..70861cce 100644 --- a/project/at_start_f437/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvoptx +++ b/project/at_start_f437/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvprojx b/project/at_start_f437/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvprojx index 226101bc..71e3a790 100644 --- a/project/at_start_f437/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvprojx +++ b/project/at_start_f437/examples/exint/exint_software_trigger/mdk_v5/exint_software_trigger.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/exint/exint_software_trigger/src/at32f435_437_clock.c b/project/at_start_f437/examples/exint/exint_software_trigger/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/exint/exint_software_trigger/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/exint/exint_software_trigger/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/flash/fap_enable/inc/at32f435_437_conf.h b/project/at_start_f437/examples/flash/fap_enable/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/flash/fap_enable/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/flash/fap_enable/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/flash/fap_enable/mdk_v5/fap_enable.uvoptx b/project/at_start_f437/examples/flash/fap_enable/mdk_v5/fap_enable.uvoptx index 84469c47..8dbc5820 100644 --- a/project/at_start_f437/examples/flash/fap_enable/mdk_v5/fap_enable.uvoptx +++ b/project/at_start_f437/examples/flash/fap_enable/mdk_v5/fap_enable.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/flash/fap_enable/mdk_v5/fap_enable.uvprojx b/project/at_start_f437/examples/flash/fap_enable/mdk_v5/fap_enable.uvprojx index e8fa3449..4418edd2 100644 --- a/project/at_start_f437/examples/flash/fap_enable/mdk_v5/fap_enable.uvprojx +++ b/project/at_start_f437/examples/flash/fap_enable/mdk_v5/fap_enable.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,12 @@ fap_enable + + + + + + 0 1 diff --git a/project/at_start_f437/examples/flash/fap_enable/src/at32f435_437_clock.c b/project/at_start_f437/examples/flash/fap_enable/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/flash/fap_enable/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/flash/fap_enable/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/flash/flash_write_read/inc/at32f435_437_conf.h b/project/at_start_f437/examples/flash/flash_write_read/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/flash/flash_write_read/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/flash/flash_write_read/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvoptx b/project/at_start_f437/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvoptx index b4534b38..7a8181d6 100644 --- a/project/at_start_f437/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvoptx +++ b/project/at_start_f437/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvprojx b/project/at_start_f437/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvprojx index 130f1171..5575effd 100644 --- a/project/at_start_f437/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvprojx +++ b/project/at_start_f437/examples/flash/flash_write_read/mdk_v5/flash_write_read.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -479,4 +479,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/flash/flash_write_read/src/at32f435_437_clock.c b/project/at_start_f437/examples/flash/flash_write_read/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/flash/flash_write_read/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/flash/flash_write_read/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/gpio/io_toggle/inc/at32f435_437_conf.h b/project/at_start_f437/examples/gpio/io_toggle/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/gpio/io_toggle/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/gpio/io_toggle/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/gpio/io_toggle/mdk_v5/io_toggle.uvoptx b/project/at_start_f437/examples/gpio/io_toggle/mdk_v5/io_toggle.uvoptx index 6df8f136..57735c3d 100644 --- a/project/at_start_f437/examples/gpio/io_toggle/mdk_v5/io_toggle.uvoptx +++ b/project/at_start_f437/examples/gpio/io_toggle/mdk_v5/io_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/gpio/io_toggle/mdk_v5/io_toggle.uvprojx b/project/at_start_f437/examples/gpio/io_toggle/mdk_v5/io_toggle.uvprojx index 1b56e30c..1bcde03a 100644 --- a/project/at_start_f437/examples/gpio/io_toggle/mdk_v5/io_toggle.uvprojx +++ b/project/at_start_f437/examples/gpio/io_toggle/mdk_v5/io_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/gpio/io_toggle/src/at32f435_437_clock.c b/project/at_start_f437/examples/gpio/io_toggle/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/gpio/io_toggle/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/gpio/io_toggle/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/gpio/led_toggle/inc/at32f435_437_conf.h b/project/at_start_f437/examples/gpio/led_toggle/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/gpio/led_toggle/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/gpio/led_toggle/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/gpio/led_toggle/mdk_v5/led_toggle.uvoptx b/project/at_start_f437/examples/gpio/led_toggle/mdk_v5/led_toggle.uvoptx index 68f9e5e3..f2ca0a6e 100644 --- a/project/at_start_f437/examples/gpio/led_toggle/mdk_v5/led_toggle.uvoptx +++ b/project/at_start_f437/examples/gpio/led_toggle/mdk_v5/led_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/gpio/led_toggle/mdk_v5/led_toggle.uvprojx b/project/at_start_f437/examples/gpio/led_toggle/mdk_v5/led_toggle.uvprojx index bdbae6b7..8aba61ed 100644 --- a/project/at_start_f437/examples/gpio/led_toggle/mdk_v5/led_toggle.uvprojx +++ b/project/at_start_f437/examples/gpio/led_toggle/mdk_v5/led_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/gpio/led_toggle/src/at32f435_437_clock.c b/project/at_start_f437/examples/gpio/led_toggle/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/gpio/led_toggle/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/gpio/led_toggle/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/gpio/swjtag_mux/inc/at32f435_437_conf.h b/project/at_start_f437/examples/gpio/swjtag_mux/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/gpio/swjtag_mux/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/gpio/swjtag_mux/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvoptx b/project/at_start_f437/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvoptx index c9ec6dd7..8dfd6e9b 100644 --- a/project/at_start_f437/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvoptx +++ b/project/at_start_f437/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvprojx b/project/at_start_f437/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvprojx index f34fe4bf..37923cdc 100644 --- a/project/at_start_f437/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvprojx +++ b/project/at_start_f437/examples/gpio/swjtag_mux/mdk_v5/swjtag_mux.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/gpio/swjtag_mux/src/at32f435_437_clock.c b/project/at_start_f437/examples/gpio/swjtag_mux/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/gpio/swjtag_mux/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/gpio/swjtag_mux/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/i2c/communication_dma/inc/at32f435_437_conf.h b/project/at_start_f437/examples/i2c/communication_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/i2c/communication_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/i2c/communication_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/i2c/communication_dma/mdk_v5/communication_dma.uvoptx b/project/at_start_f437/examples/i2c/communication_dma/mdk_v5/communication_dma.uvoptx index 65e83f4b..7764f274 100644 --- a/project/at_start_f437/examples/i2c/communication_dma/mdk_v5/communication_dma.uvoptx +++ b/project/at_start_f437/examples/i2c/communication_dma/mdk_v5/communication_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/i2c/communication_dma/mdk_v5/communication_dma.uvprojx b/project/at_start_f437/examples/i2c/communication_dma/mdk_v5/communication_dma.uvprojx index 19917275..9d305466 100644 --- a/project/at_start_f437/examples/i2c/communication_dma/mdk_v5/communication_dma.uvprojx +++ b/project/at_start_f437/examples/i2c/communication_dma/mdk_v5/communication_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -489,4 +489,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/i2c/communication_dma/src/at32f435_437_clock.c b/project/at_start_f437/examples/i2c/communication_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/i2c/communication_dma/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/i2c/communication_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/i2c/communication_int/inc/at32f435_437_conf.h b/project/at_start_f437/examples/i2c/communication_int/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/i2c/communication_int/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/i2c/communication_int/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/i2c/communication_int/mdk_v5/communication_int.uvoptx b/project/at_start_f437/examples/i2c/communication_int/mdk_v5/communication_int.uvoptx index 336e9647..e8ce37fd 100644 --- a/project/at_start_f437/examples/i2c/communication_int/mdk_v5/communication_int.uvoptx +++ b/project/at_start_f437/examples/i2c/communication_int/mdk_v5/communication_int.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/i2c/communication_int/mdk_v5/communication_int.uvprojx b/project/at_start_f437/examples/i2c/communication_int/mdk_v5/communication_int.uvprojx index 8854d3ba..3dca01d1 100644 --- a/project/at_start_f437/examples/i2c/communication_int/mdk_v5/communication_int.uvprojx +++ b/project/at_start_f437/examples/i2c/communication_int/mdk_v5/communication_int.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -489,4 +489,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/i2c/communication_int/src/at32f435_437_clock.c b/project/at_start_f437/examples/i2c/communication_int/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/i2c/communication_int/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/i2c/communication_int/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/i2c/communication_poll/inc/at32f435_437_conf.h b/project/at_start_f437/examples/i2c/communication_poll/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/i2c/communication_poll/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/i2c/communication_poll/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/i2c/communication_poll/mdk_v5/communication_poll.uvoptx b/project/at_start_f437/examples/i2c/communication_poll/mdk_v5/communication_poll.uvoptx index 1c661e85..3a5f498b 100644 --- a/project/at_start_f437/examples/i2c/communication_poll/mdk_v5/communication_poll.uvoptx +++ b/project/at_start_f437/examples/i2c/communication_poll/mdk_v5/communication_poll.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/i2c/communication_poll/mdk_v5/communication_poll.uvprojx b/project/at_start_f437/examples/i2c/communication_poll/mdk_v5/communication_poll.uvprojx index 8c1b8abf..53af7c53 100644 --- a/project/at_start_f437/examples/i2c/communication_poll/mdk_v5/communication_poll.uvprojx +++ b/project/at_start_f437/examples/i2c/communication_poll/mdk_v5/communication_poll.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -489,4 +489,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/i2c/communication_poll/src/at32f435_437_clock.c b/project/at_start_f437/examples/i2c/communication_poll/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/i2c/communication_poll/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/i2c/communication_poll/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/i2c/communication_smbus/inc/at32f435_437_conf.h b/project/at_start_f437/examples/i2c/communication_smbus/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/i2c/communication_smbus/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/i2c/communication_smbus/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvoptx b/project/at_start_f437/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvoptx index 349f85bf..60f56835 100644 --- a/project/at_start_f437/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvoptx +++ b/project/at_start_f437/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvprojx b/project/at_start_f437/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvprojx index 32afd608..5a6b0e36 100644 --- a/project/at_start_f437/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvprojx +++ b/project/at_start_f437/examples/i2c/communication_smbus/mdk_v5/communication_smbus.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -489,4 +489,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/i2c/communication_smbus/src/at32f435_437_clock.c b/project/at_start_f437/examples/i2c/communication_smbus/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/i2c/communication_smbus/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/i2c/communication_smbus/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/i2c/eeprom/inc/at32f435_437_conf.h b/project/at_start_f437/examples/i2c/eeprom/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/i2c/eeprom/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/i2c/eeprom/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/i2c/eeprom/mdk_v5/eeprom.uvoptx b/project/at_start_f437/examples/i2c/eeprom/mdk_v5/eeprom.uvoptx index 91e39a03..39b2efad 100644 --- a/project/at_start_f437/examples/i2c/eeprom/mdk_v5/eeprom.uvoptx +++ b/project/at_start_f437/examples/i2c/eeprom/mdk_v5/eeprom.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/i2c/eeprom/mdk_v5/eeprom.uvprojx b/project/at_start_f437/examples/i2c/eeprom/mdk_v5/eeprom.uvprojx index e47aaa8c..f90b3eea 100644 --- a/project/at_start_f437/examples/i2c/eeprom/mdk_v5/eeprom.uvprojx +++ b/project/at_start_f437/examples/i2c/eeprom/mdk_v5/eeprom.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -489,4 +489,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/i2c/eeprom/src/at32f435_437_clock.c b/project/at_start_f437/examples/i2c/eeprom/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/i2c/eeprom/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/i2c/eeprom/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/i2s/fullduplex_dma/inc/at32f435_437_conf.h b/project/at_start_f437/examples/i2s/fullduplex_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/i2s/fullduplex_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/i2s/fullduplex_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvoptx b/project/at_start_f437/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvoptx index 41046dab..f54f8e3e 100644 --- a/project/at_start_f437/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvoptx +++ b/project/at_start_f437/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvprojx b/project/at_start_f437/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvprojx index a3dd31a4..639fe13b 100644 --- a/project/at_start_f437/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvprojx +++ b/project/at_start_f437/examples/i2s/fullduplex_dma/mdk_v5/fullduplex_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/i2s/fullduplex_dma/src/at32f435_437_clock.c b/project/at_start_f437/examples/i2s/fullduplex_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/i2s/fullduplex_dma/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/i2s/fullduplex_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/i2s/halfduplex_dma/inc/at32f435_437_conf.h b/project/at_start_f437/examples/i2s/halfduplex_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/i2s/halfduplex_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/i2s/halfduplex_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvoptx b/project/at_start_f437/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvoptx index c3073535..43807fc1 100644 --- a/project/at_start_f437/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvoptx +++ b/project/at_start_f437/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvprojx b/project/at_start_f437/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvprojx index 2100deb6..819c00b6 100644 --- a/project/at_start_f437/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvprojx +++ b/project/at_start_f437/examples/i2s/halfduplex_dma/mdk_v5/halfduplex_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/i2s/halfduplex_dma/src/at32f435_437_clock.c b/project/at_start_f437/examples/i2s/halfduplex_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/i2s/halfduplex_dma/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/i2s/halfduplex_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/i2s/halfduplex_interrupt/inc/at32f435_437_conf.h b/project/at_start_f437/examples/i2s/halfduplex_interrupt/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/i2s/halfduplex_interrupt/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/i2s/halfduplex_interrupt/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx b/project/at_start_f437/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx index 4a93353f..c96af29e 100644 --- a/project/at_start_f437/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx +++ b/project/at_start_f437/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx b/project/at_start_f437/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx index 969634f1..b79c30b3 100644 --- a/project/at_start_f437/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx +++ b/project/at_start_f437/examples/i2s/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/i2s/halfduplex_interrupt/src/at32f435_437_clock.c b/project/at_start_f437/examples/i2s/halfduplex_interrupt/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/i2s/halfduplex_interrupt/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/i2s/halfduplex_interrupt/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/inc/at32f435_437_conf.h b/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvoptx b/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvoptx index 6147753d..baf3be4a 100644 --- a/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvoptx +++ b/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvprojx b/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvprojx index 28f89b1e..3c94c1a9 100644 --- a/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvprojx +++ b/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/mdk_v5/spii2s_switch_halfduplex_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f435_437_clock.c b/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/i2s/spii2s_switch_halfduplex_polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/irtmr/irtmr_output/inc/at32f435_437_conf.h b/project/at_start_f437/examples/irtmr/irtmr_output/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/irtmr/irtmr_output/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/irtmr/irtmr_output/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvoptx b/project/at_start_f437/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvoptx index b60c0736..ae5991da 100644 --- a/project/at_start_f437/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvoptx +++ b/project/at_start_f437/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvprojx b/project/at_start_f437/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvprojx index 5fe0423f..0ce452ba 100644 --- a/project/at_start_f437/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvprojx +++ b/project/at_start_f437/examples/irtmr/irtmr_output/mdk_v5/irtmr_output.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/irtmr/irtmr_output/src/at32f435_437_clock.c b/project/at_start_f437/examples/irtmr/irtmr_output/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/irtmr/irtmr_output/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/irtmr/irtmr_output/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/inc/at32f435_437_conf.h b/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvoptx b/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvoptx index 0fe1b52b..0afcdeaf 100644 --- a/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvoptx +++ b/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvprojx b/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvprojx index c0d2811d..3bd14844 100644 --- a/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvprojx +++ b/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/mdk_v5/deepsleep_ertc_alarm.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/src/at32f435_437_clock.c b/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/pwc/deepsleep_ertc_alarm/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/inc/at32f435_437_conf.h b/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvoptx b/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvoptx index 4f3d3c30..214d318f 100644 --- a/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvoptx +++ b/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvprojx b/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvprojx index ae31a879..ba77766b 100644 --- a/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvprojx +++ b/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/mdk_v5/deepsleep_ertc_tamper.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/src/at32f435_437_clock.c b/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/pwc/deepsleep_ertc_tamper/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/inc/at32f435_437_conf.h b/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvoptx b/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvoptx index bac0c3e0..a4656e82 100644 --- a/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvoptx +++ b/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvprojx b/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvprojx index fe9fce74..d36fbec4 100644 --- a/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvprojx +++ b/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/mdk_v5/deepsleep_ertc_wakeup.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/src/at32f435_437_clock.c b/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/pwc/deepsleep_ertc_wakeup/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/pwc/ldo_set/inc/at32f435_437_conf.h b/project/at_start_f437/examples/pwc/ldo_set/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/pwc/ldo_set/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/pwc/ldo_set/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/pwc/ldo_set/mdk_v5/ldo_set.uvoptx b/project/at_start_f437/examples/pwc/ldo_set/mdk_v5/ldo_set.uvoptx index be44013b..28dd3343 100644 --- a/project/at_start_f437/examples/pwc/ldo_set/mdk_v5/ldo_set.uvoptx +++ b/project/at_start_f437/examples/pwc/ldo_set/mdk_v5/ldo_set.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/pwc/ldo_set/mdk_v5/ldo_set.uvprojx b/project/at_start_f437/examples/pwc/ldo_set/mdk_v5/ldo_set.uvprojx index 0dcc89b7..034f0170 100644 --- a/project/at_start_f437/examples/pwc/ldo_set/mdk_v5/ldo_set.uvprojx +++ b/project/at_start_f437/examples/pwc/ldo_set/mdk_v5/ldo_set.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/pwc/ldo_set/src/at32f435_437_clock.c b/project/at_start_f437/examples/pwc/ldo_set/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/pwc/ldo_set/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/pwc/ldo_set/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/pwc/power_voltage_monitor/inc/at32f435_437_conf.h b/project/at_start_f437/examples/pwc/power_voltage_monitor/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/pwc/power_voltage_monitor/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/pwc/power_voltage_monitor/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvoptx b/project/at_start_f437/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvoptx index 0ee4a587..17385a88 100644 --- a/project/at_start_f437/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvoptx +++ b/project/at_start_f437/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvprojx b/project/at_start_f437/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvprojx index f9a495e2..670c3d7c 100644 --- a/project/at_start_f437/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvprojx +++ b/project/at_start_f437/examples/pwc/power_voltage_monitor/mdk_v5/power_voltage_monitor.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/pwc/power_voltage_monitor/src/at32f435_437_clock.c b/project/at_start_f437/examples/pwc/power_voltage_monitor/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/pwc/power_voltage_monitor/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/pwc/power_voltage_monitor/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/pwc/sleep_tmr2/inc/at32f435_437_conf.h b/project/at_start_f437/examples/pwc/sleep_tmr2/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/pwc/sleep_tmr2/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/pwc/sleep_tmr2/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvoptx b/project/at_start_f437/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvoptx index 6346be67..0e0e7564 100644 --- a/project/at_start_f437/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvoptx +++ b/project/at_start_f437/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvprojx b/project/at_start_f437/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvprojx index b5bcb8f5..3687b817 100644 --- a/project/at_start_f437/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvprojx +++ b/project/at_start_f437/examples/pwc/sleep_tmr2/mdk_v5/sleep_tmr2.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/pwc/sleep_tmr2/src/at32f435_437_clock.c b/project/at_start_f437/examples/pwc/sleep_tmr2/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/pwc/sleep_tmr2/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/pwc/sleep_tmr2/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/pwc/sleep_usart1/inc/at32f435_437_conf.h b/project/at_start_f437/examples/pwc/sleep_usart1/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/pwc/sleep_usart1/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/pwc/sleep_usart1/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvoptx b/project/at_start_f437/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvoptx index d4f4e8f3..349b0b15 100644 --- a/project/at_start_f437/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvoptx +++ b/project/at_start_f437/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvprojx b/project/at_start_f437/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvprojx index a64d7cb1..edbe9568 100644 --- a/project/at_start_f437/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvprojx +++ b/project/at_start_f437/examples/pwc/sleep_usart1/mdk_v5/sleep_usart1.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/pwc/sleep_usart1/src/at32f435_437_clock.c b/project/at_start_f437/examples/pwc/sleep_usart1/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/pwc/sleep_usart1/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/pwc/sleep_usart1/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/pwc/standby_ertc_alarm/inc/at32f435_437_conf.h b/project/at_start_f437/examples/pwc/standby_ertc_alarm/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/pwc/standby_ertc_alarm/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/pwc/standby_ertc_alarm/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvoptx b/project/at_start_f437/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvoptx index a8e4c0ab..3aef295a 100644 --- a/project/at_start_f437/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvoptx +++ b/project/at_start_f437/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvprojx b/project/at_start_f437/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvprojx index 056ddfe1..d944e902 100644 --- a/project/at_start_f437/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvprojx +++ b/project/at_start_f437/examples/pwc/standby_ertc_alarm/mdk_v5/standby_ertc_alarm.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/pwc/standby_ertc_alarm/src/at32f435_437_clock.c b/project/at_start_f437/examples/pwc/standby_ertc_alarm/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/pwc/standby_ertc_alarm/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/pwc/standby_ertc_alarm/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/pwc/standby_wakeup_pin/inc/at32f435_437_conf.h b/project/at_start_f437/examples/pwc/standby_wakeup_pin/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/pwc/standby_wakeup_pin/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/pwc/standby_wakeup_pin/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvoptx b/project/at_start_f437/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvoptx index a6277dbe..8de40bf1 100644 --- a/project/at_start_f437/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvoptx +++ b/project/at_start_f437/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvprojx b/project/at_start_f437/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvprojx index 663f8382..1ff1b395 100644 --- a/project/at_start_f437/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvprojx +++ b/project/at_start_f437/examples/pwc/standby_wakeup_pin/mdk_v5/standby_wakeup_pin.uvprojx @@ -10,13 +10,13 @@ standby_wakeup_pin 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC + 5060750::V5.06 update 6 (build 750)::.\ARMCC 0 -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/pwc/standby_wakeup_pin/src/at32f435_437_clock.c b/project/at_start_f437/examples/pwc/standby_wakeup_pin/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/pwc/standby_wakeup_pin/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/pwc/standby_wakeup_pin/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/pwc/standby_wakeup_pin/src/main.c b/project/at_start_f437/examples/pwc/standby_wakeup_pin/src/main.c index 3984391c..62ea6178 100644 --- a/project/at_start_f437/examples/pwc/standby_wakeup_pin/src/main.c +++ b/project/at_start_f437/examples/pwc/standby_wakeup_pin/src/main.c @@ -74,6 +74,8 @@ int main(void) } at32_led_on(LED4); + + /*delay to check led status*/ delay_ms(1000); /* enable wakeup pin1(pa0), pin2(pc13) */ diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma/inc/at32f435_437_conf.h b/project/at_start_f437/examples/qspi/command_port_using_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/qspi/command_port_using_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvoptx b/project/at_start_f437/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvoptx index 337b3ed4..e8b7ce7f 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvoptx +++ b/project/at_start_f437/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvprojx b/project/at_start_f437/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvprojx index 1f683cdb..3cc1aa47 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvprojx +++ b/project/at_start_f437/examples/qspi/command_port_using_dma/mdk_v5/command_port_using_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma/src/at32f435_437_clock.c b/project/at_start_f437/examples/qspi/command_port_using_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/qspi/command_port_using_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma/src/qspi_cmd_esmt32m.c b/project/at_start_f437/examples/qspi/command_port_using_dma/src/qspi_cmd_esmt32m.c index ecd34872..35e9d304 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma/src/qspi_cmd_esmt32m.c +++ b/project/at_start_f437/examples/qspi/command_port_using_dma/src/qspi_cmd_esmt32m.c @@ -255,15 +255,10 @@ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { uint32_t blk_sz; do - { /* send up to 256 bytes at one time */ - if(total_len > FLASH_PAGE_PROGRAM_SIZE) - { - blk_sz = FLASH_PAGE_PROGRAM_SIZE; - } - else - { + { /* send up to 256 bytes at one time, and only one page */ + blk_sz = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < blk_sz) blk_sz = total_len; - } qspi_data_once_write(addr, blk_sz, buf); addr += blk_sz; buf += blk_sz; diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/inc/at32f435_437_conf.h b/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvoptx b/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvoptx index 5df7c5e9..a3f8bc30 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvoptx +++ b/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvprojx b/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvprojx index f5c1f031..95a998ea 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvprojx +++ b/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/mdk_v5/command_port_using_dma_and_pem.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/src/at32f435_437_clock.c b/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/src/qspi_cmd_esmt32m.c b/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/src/qspi_cmd_esmt32m.c index d33ca5fd..981baf24 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/src/qspi_cmd_esmt32m.c +++ b/project/at_start_f437/examples/qspi/command_port_using_dma_and_pem/src/qspi_cmd_esmt32m.c @@ -347,15 +347,10 @@ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { uint32_t blk_sz; do - { /* send up to 256 bytes at one time */ - if(total_len > FLASH_PAGE_PROGRAM_SIZE) - { - blk_sz = FLASH_PAGE_PROGRAM_SIZE; - } - else - { + { /* send up to 256 bytes at one time, and only one page */ + blk_sz = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < blk_sz) blk_sz = total_len; - } qspi_data_once_write(addr, blk_sz, buf); addr += blk_sz; buf += blk_sz; diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/inc/at32f435_437_conf.h b/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvoptx b/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvoptx index 3e213138..b9b9e783 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvoptx +++ b/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvprojx b/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvprojx index 3542f454..70dc9103 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvprojx +++ b/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/mdk_v5/command_port_using_dma_qpi_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/src/at32f435_437_clock.c b/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/src/qspi_cmd_esmt32m.c b/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/src/qspi_cmd_esmt32m.c index 4e96ac7c..d14a4090 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/src/qspi_cmd_esmt32m.c +++ b/project/at_start_f437/examples/qspi/command_port_using_dma_qpi_mode/src/qspi_cmd_esmt32m.c @@ -255,15 +255,10 @@ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { uint32_t blk_sz; do - { /* send up to 256 bytes at one time */ - if(total_len > FLASH_PAGE_PROGRAM_SIZE) - { - blk_sz = FLASH_PAGE_PROGRAM_SIZE; - } - else - { + { /* send up to 256 bytes at one time, and only one page */ + blk_sz = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < blk_sz) blk_sz = total_len; - } qspi_data_once_write(addr, blk_sz, buf); addr += blk_sz; buf += blk_sz; diff --git a/project/at_start_f437/examples/qspi/command_port_using_interrupt/inc/at32f435_437_conf.h b/project/at_start_f437/examples/qspi/command_port_using_interrupt/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_interrupt/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/qspi/command_port_using_interrupt/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvoptx b/project/at_start_f437/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvoptx index 707e4d51..8b57c816 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvoptx +++ b/project/at_start_f437/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvprojx b/project/at_start_f437/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvprojx index 59e7e072..c6ebfffb 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvprojx +++ b/project/at_start_f437/examples/qspi/command_port_using_interrupt/mdk_v5/command_port_using_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -479,4 +479,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/qspi/command_port_using_interrupt/src/at32f435_437_clock.c b/project/at_start_f437/examples/qspi/command_port_using_interrupt/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_interrupt/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/qspi/command_port_using_interrupt/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/qspi/command_port_using_interrupt/src/qspi_cmd_esmt32m.c b/project/at_start_f437/examples/qspi/command_port_using_interrupt/src/qspi_cmd_esmt32m.c index b34825e9..9466fe65 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_interrupt/src/qspi_cmd_esmt32m.c +++ b/project/at_start_f437/examples/qspi/command_port_using_interrupt/src/qspi_cmd_esmt32m.c @@ -244,19 +244,16 @@ void qspi_data_read(uint32_t addr, uint32_t total_len, uint8_t* buf) */ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { - uint32_t i, len = total_len; + uint32_t i, len; do { qspi_write_enable(); - if(total_len >= FLASH_PAGE_PROGRAM_SIZE) - { - len = FLASH_PAGE_PROGRAM_SIZE; - } - else - { + /* send up to 256 bytes at one time, and only one page */ + len = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < len) len = total_len; - } + /* set busy state */ qspi_command_set_busy(); diff --git a/project/at_start_f437/examples/qspi/command_port_using_polling/inc/at32f435_437_conf.h b/project/at_start_f437/examples/qspi/command_port_using_polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_polling/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/qspi/command_port_using_polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvoptx b/project/at_start_f437/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvoptx index 92fbe12d..10b04763 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvoptx +++ b/project/at_start_f437/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvprojx b/project/at_start_f437/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvprojx index 1007a660..19bffdc3 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvprojx +++ b/project/at_start_f437/examples/qspi/command_port_using_polling/mdk_v5/command_port_using_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x400000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -479,4 +479,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/qspi/command_port_using_polling/src/at32f435_437_clock.c b/project/at_start_f437/examples/qspi/command_port_using_polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_polling/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/qspi/command_port_using_polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/qspi/command_port_using_polling/src/qspi_cmd_esmt32m.c b/project/at_start_f437/examples/qspi/command_port_using_polling/src/qspi_cmd_esmt32m.c index bef7e9a9..38268911 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_polling/src/qspi_cmd_esmt32m.c +++ b/project/at_start_f437/examples/qspi/command_port_using_polling/src/qspi_cmd_esmt32m.c @@ -197,19 +197,16 @@ void qspi_data_read(uint32_t addr, uint32_t total_len, uint8_t* buf) */ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { - uint32_t i, len = total_len; + uint32_t i, len; do { qspi_write_enable(); - if(total_len >= FLASH_PAGE_PROGRAM_SIZE) - { - len = FLASH_PAGE_PROGRAM_SIZE; - } - else - { + /* send up to 256 bytes at one time, and only one page */ + len = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < len) len = total_len; - } + esmt32m_cmd_write_config(&esmt32m_cmd_config, addr, len); qspi_cmd_operation_kick(QSPI1, &esmt32m_cmd_config); diff --git a/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/inc/at32f435_437_conf.h b/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvoptx b/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvoptx index 97e653e9..36cbb4c6 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvoptx +++ b/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvprojx b/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvprojx index 5a5cca89..a8019159 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvprojx +++ b/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/mdk_v5/command_port_using_rdsr_sw.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -479,4 +479,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/src/at32f435_437_clock.c b/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/src/qspi_cmd_esmt32m.c b/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/src/qspi_cmd_esmt32m.c index 5fbe4b52..e1734b85 100644 --- a/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/src/qspi_cmd_esmt32m.c +++ b/project/at_start_f437/examples/qspi/command_port_using_rdsr_sw/src/qspi_cmd_esmt32m.c @@ -197,19 +197,16 @@ void qspi_data_read(uint32_t addr, uint32_t total_len, uint8_t* buf) */ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { - uint32_t i, len = total_len; + uint32_t i, len; do { qspi_write_enable(); - if(total_len >= FLASH_PAGE_PROGRAM_SIZE) - { - len = FLASH_PAGE_PROGRAM_SIZE; - } - else - { + /* send up to 256 bytes at one time, and only one page */ + len = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < len) len = total_len; - } + esmt32m_cmd_write_config(&esmt32m_cmd_config, addr, len); qspi_cmd_operation_kick(QSPI1, &esmt32m_cmd_config); diff --git a/project/at_start_f437/examples/qspi/xip_port_read_flash/inc/at32f435_437_conf.h b/project/at_start_f437/examples/qspi/xip_port_read_flash/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/qspi/xip_port_read_flash/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/qspi/xip_port_read_flash/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvoptx b/project/at_start_f437/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvoptx index 475b95a3..792c2e16 100644 --- a/project/at_start_f437/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvoptx +++ b/project/at_start_f437/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 @@ -282,18 +282,6 @@ 0 0 0 - ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_dma.c - at32f435_437_dma.c - 0 - 0 - - - 3 - 9 - 1 - 0 - 0 - 0 ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_qspi.c at32f435_437_qspi.c 0 @@ -301,7 +289,7 @@ 3 - 10 + 9 1 0 0 @@ -313,7 +301,7 @@ 3 - 11 + 10 1 0 0 @@ -333,7 +321,7 @@ 0 4 - 12 + 11 1 0 0 @@ -345,7 +333,7 @@ 4 - 13 + 12 2 0 0 @@ -365,7 +353,7 @@ 0 5 - 14 + 13 5 0 0 diff --git a/project/at_start_f437/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvprojx b/project/at_start_f437/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvprojx index 3cdfa4c5..dfe5505d 100644 --- a/project/at_start_f437/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvprojx +++ b/project/at_start_f437/examples/qspi/xip_port_read_flash/mdk_v5/xip_port_read_flash.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -427,11 +427,6 @@ 1 ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_misc.c - - at32f435_437_dma.c - 1 - ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_dma.c - at32f435_437_qspi.c 1 @@ -488,6 +483,12 @@ xip_port_read_flash + + + + + + 0 1 diff --git a/project/at_start_f437/examples/qspi/xip_port_read_flash/src/at32f435_437_clock.c b/project/at_start_f437/examples/qspi/xip_port_read_flash/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/qspi/xip_port_read_flash/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/qspi/xip_port_read_flash/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/qspi/xip_port_read_flash/src/main.c b/project/at_start_f437/examples/qspi/xip_port_read_flash/src/main.c index 5de53a6e..ade36e9d 100644 --- a/project/at_start_f437/examples/qspi/xip_port_read_flash/src/main.c +++ b/project/at_start_f437/examples/qspi/xip_port_read_flash/src/main.c @@ -34,7 +34,6 @@ * @{ */ -extern void qspi_data_read(uint32_t addr, uint32_t total_len, uint8_t* buf); extern void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf); extern void qspi_erase(uint32_t sec_addr); extern void en25qh128a_qspi_xip_init(void); @@ -59,8 +58,6 @@ ALIGNED_HEAD uint8_t rbuf[TEST_SIZE] ALIGNED_TAIL; void qspi_config(void) { gpio_init_type gpio_init_struct; - /* enable the dma clock */ - crm_periph_clock_enable(CRM_DMA2_PERIPH_CLOCK, TRUE); /* enable the qspi clock */ crm_periph_clock_enable(CRM_QSPI1_PERIPH_CLOCK, TRUE); @@ -142,18 +139,6 @@ int main(void) /* erase */ qspi_erase(0); - /* read */ - qspi_data_read(0, TEST_SIZE, rbuf); - - for(i = 0; i < TEST_SIZE; i++) - { - if(rbuf[i] != 0xFF) - { - err = 1; - break; - } - } - /* program */ qspi_data_write(0, TEST_SIZE, wbuf); diff --git a/project/at_start_f437/examples/qspi/xip_port_read_flash/src/qspi_cmd_en25qh128a.c b/project/at_start_f437/examples/qspi/xip_port_read_flash/src/qspi_cmd_en25qh128a.c index 5ade664f..7a466c9a 100644 --- a/project/at_start_f437/examples/qspi/xip_port_read_flash/src/qspi_cmd_en25qh128a.c +++ b/project/at_start_f437/examples/qspi/xip_port_read_flash/src/qspi_cmd_en25qh128a.c @@ -40,29 +40,6 @@ qspi_xip_type en25qh128a_xip_init; void qspi_busy_check(void); void qspi_write_enable(void); -/** - * @brief en25qh128a cmd read config - * @param qspi_cmd_struct: the pointer for qspi_cmd_type parameter - * @param addr: read start address - * @param counter: read data counter - * @retval none - */ -void en25qh128a_cmd_read_config(qspi_cmd_type *qspi_cmd_struct, uint32_t addr, uint32_t counter) -{ - qspi_cmd_struct->pe_mode_enable = FALSE; - qspi_cmd_struct->pe_mode_operate_code = 0; - qspi_cmd_struct->instruction_code = 0xEB; - qspi_cmd_struct->instruction_length = QSPI_CMD_INSLEN_1_BYTE; - qspi_cmd_struct->address_code = addr; - qspi_cmd_struct->address_length = QSPI_CMD_ADRLEN_3_BYTE; - qspi_cmd_struct->data_counter = counter; - qspi_cmd_struct->second_dummy_cycle_num = 6; - qspi_cmd_struct->operation_mode = QSPI_OPERATE_MODE_144; - qspi_cmd_struct->read_status_config = QSPI_RSTSC_HW_AUTO; - qspi_cmd_struct->read_status_enable = FALSE; - qspi_cmd_struct->write_data_enable = FALSE; -} - /** * @brief en25qh128a cmd write config * @param qspi_cmd_struct: the pointer for qspi_cmd_type parameter @@ -150,102 +127,6 @@ void en25qh128a_cmd_rdsr_config(qspi_cmd_type *qspi_cmd_struct) qspi_cmd_struct->write_data_enable = FALSE; } -/** - * @brief qspi dma set - * @param dir: dma transfer direction - * @param buf: the pointer for dma data - * @param length: data length - * @retval none - */ -void qspi_dma_set(dma_dir_type dir, uint8_t* buf, uint32_t length) -{ - dma_init_type dma_init_struct; - dma_reset(DMA2_CHANNEL1); - dma_default_para_init(&dma_init_struct); - dma_init_struct.buffer_size = length / 4; /* using word unit */ - dma_init_struct.loop_mode_enable = FALSE; - dma_init_struct.direction = dir; - dma_init_struct.memory_base_addr = (uint32_t)buf; - dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_WORD; - dma_init_struct.memory_inc_enable = TRUE; - dma_init_struct.peripheral_base_addr = (uint32_t)(&(QSPI1->dt)); - dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_WORD; - dma_init_struct.peripheral_inc_enable = FALSE; - dma_init_struct.priority = DMA_PRIORITY_HIGH; - - dma_init(DMA2_CHANNEL1, &dma_init_struct); - - dmamux_init(DMA2MUX_CHANNEL1, DMAMUX_DMAREQ_ID_QSPI1); - dmamux_enable(DMA2, TRUE); - - dma_channel_enable(DMA2_CHANNEL1, TRUE); -} - -/** - * @brief qspi read data - * @param addr: the address for read - * @param total_len: the length for read - * @param buf: the pointer for read data - * @retval none - */ -void qspi_data_read(uint32_t addr, uint32_t total_len, uint8_t* buf) -{ - /* config qspi's dma mode */ - qspi_dma_enable(QSPI1, TRUE); - qspi_dma_rx_threshold_set(QSPI1, QSPI_DMA_FIFO_THOD_WORD08); - - /* config and enable dma */ - qspi_dma_set(DMA_DIR_PERIPHERAL_TO_MEMORY, buf, total_len); - - /* kick command */ - en25qh128a_cmd_read_config(&en25qh128a_cmd_config, addr, total_len); - qspi_cmd_operation_kick(QSPI1, &en25qh128a_cmd_config); - - /* wait command completed */ - while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET); - qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG); - - /* wait dma completed */ - while(dma_flag_get(DMA2_FDT1_FLAG) == RESET); - dma_flag_clear(DMA2_FDT1_FLAG); - qspi_dma_enable(QSPI1, FALSE); -} - -/** - * @brief qspi write data for one time - * @param addr: the address for write - * @param sz: the length for write - * @param buf: the pointer for write data - * @retval none - */ -static void qspi_data_once_write(uint32_t addr, uint32_t sz, uint8_t* buf) -{ - qspi_write_enable(); - - /* config qspi's dma mode */ - qspi_dma_enable(QSPI1, TRUE); - qspi_dma_tx_threshold_set(QSPI1, QSPI_DMA_FIFO_THOD_WORD08); - - /* config and enable dma */ - qspi_dma_set(DMA_DIR_MEMORY_TO_PERIPHERAL, buf, sz); - - /* kick command */ - en25qh128a_cmd_write_config(&en25qh128a_cmd_config, addr, sz); - qspi_cmd_operation_kick(QSPI1, &en25qh128a_cmd_config); - - - /* wait command completed */ - while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET); - qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG); - - /* wait dma completed */ - while(dma_flag_get(DMA2_FDT1_FLAG) == RESET); - dma_flag_clear(DMA2_FDT1_FLAG); - qspi_dma_enable(QSPI1, FALSE); - - qspi_busy_check(); -} - /** * @brief qspi write data * @param addr: the address for write @@ -255,22 +136,33 @@ static void qspi_data_once_write(uint32_t addr, uint32_t sz, uint8_t* buf) */ void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf) { - uint32_t blk_sz; - do - { /* send up to 256 bytes at one time */ - if(total_len > FLASH_PAGE_PROGRAM_SIZE) - { - blk_sz = FLASH_PAGE_PROGRAM_SIZE; - } - else - { - blk_sz = total_len; - } - qspi_data_once_write(addr, blk_sz, buf); - addr += blk_sz; - buf += blk_sz; - total_len -= blk_sz; - }while(total_len > 0); + uint32_t i, len; + do + { + qspi_write_enable(); + /* send up to 256 bytes at one time, and only one page */ + len = (addr / FLASH_PAGE_PROGRAM_SIZE + 1) * FLASH_PAGE_PROGRAM_SIZE - addr; + if(total_len < len) + len = total_len; + + en25qh128a_cmd_write_config(&en25qh128a_cmd_config, addr, len); + qspi_cmd_operation_kick(QSPI1, &en25qh128a_cmd_config); + + for(i = 0; i < len; ++i) + { + while(qspi_flag_get(QSPI1, QSPI_TXFIFORDY_FLAG) == RESET); + qspi_byte_write(QSPI1, *buf++); + } + total_len -= len; + addr += len; + + /* wait command completed */ + while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET); + qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG); + + qspi_busy_check(); + + }while(total_len); } /** diff --git a/project/at_start_f437/examples/qspi/xip_port_read_write_sram/inc/at32f435_437_conf.h b/project/at_start_f437/examples/qspi/xip_port_read_write_sram/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/qspi/xip_port_read_write_sram/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/qspi/xip_port_read_write_sram/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvoptx b/project/at_start_f437/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvoptx index 4b323180..267ef103 100644 --- a/project/at_start_f437/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvoptx +++ b/project/at_start_f437/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvprojx b/project/at_start_f437/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvprojx index b8a71740..62d07933 100644 --- a/project/at_start_f437/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvprojx +++ b/project/at_start_f437/examples/qspi/xip_port_read_write_sram/mdk_v5/xip_port_read_write_sram.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,12 @@ xip_port_read_write_sram + + + + + + 0 1 diff --git a/project/at_start_f437/examples/qspi/xip_port_read_write_sram/src/at32f435_437_clock.c b/project/at_start_f437/examples/qspi/xip_port_read_write_sram/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/qspi/xip_port_read_write_sram/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/qspi/xip_port_read_write_sram/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/scfg/mem_map_sel/inc/at32f435_437_conf.h b/project/at_start_f437/examples/scfg/mem_map_sel/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/scfg/mem_map_sel/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/scfg/mem_map_sel/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvoptx b/project/at_start_f437/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvoptx index df13eae2..fc4c36fe 100644 --- a/project/at_start_f437/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvoptx +++ b/project/at_start_f437/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvprojx b/project/at_start_f437/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvprojx index bd8f0cc9..f919c005 100644 --- a/project/at_start_f437/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvprojx +++ b/project/at_start_f437/examples/scfg/mem_map_sel/mdk_v5/mem_map_sel.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/scfg/mem_map_sel/src/at32f435_437_clock.c b/project/at_start_f437/examples/scfg/mem_map_sel/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/scfg/mem_map_sel/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/scfg/mem_map_sel/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/sdio/sd_mmc_card/inc/at32f435_437_conf.h b/project/at_start_f437/examples/sdio/sd_mmc_card/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/sdio/sd_mmc_card/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/sdio/sd_mmc_card/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvoptx b/project/at_start_f437/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvoptx index bbe7852d..041ee186 100644 --- a/project/at_start_f437/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvoptx +++ b/project/at_start_f437/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvprojx b/project/at_start_f437/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvprojx index 0c5e6987..bd2027ad 100644 --- a/project/at_start_f437/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvprojx +++ b/project/at_start_f437/examples/sdio/sd_mmc_card/mdk_v5/sd_mmc_card.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/sdio/sd_mmc_card/src/at32f435_437_clock.c b/project/at_start_f437/examples/sdio/sd_mmc_card/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/sdio/sd_mmc_card/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/sdio/sd_mmc_card/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/sdio/sdio_fatfs/inc/at32f435_437_conf.h b/project/at_start_f437/examples/sdio/sdio_fatfs/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/sdio/sdio_fatfs/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/sdio/sdio_fatfs/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvoptx b/project/at_start_f437/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvoptx index e3d0dc39..f60f65aa 100644 --- a/project/at_start_f437/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvoptx +++ b/project/at_start_f437/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvprojx b/project/at_start_f437/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvprojx index 546cdc7a..5dcee7f7 100644 --- a/project/at_start_f437/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvprojx +++ b/project/at_start_f437/examples/sdio/sdio_fatfs/mdk_v5/sdio_fatfs.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -620,6 +620,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/sdio/sdio_fatfs/src/at32f435_437_clock.c b/project/at_start_f437/examples/sdio/sdio_fatfs/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/sdio/sdio_fatfs/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/sdio/sdio_fatfs/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/sdio/sdio_fatfs/src/diskio.c b/project/at_start_f437/examples/sdio/sdio_fatfs/src/diskio.c index 6edee5d2..f8f0e5f3 100644 --- a/project/at_start_f437/examples/sdio/sdio_fatfs/src/diskio.c +++ b/project/at_start_f437/examples/sdio/sdio_fatfs/src/diskio.c @@ -19,7 +19,10 @@ #define DEV_MMC 1 /* Example: Map MMC/SD card to physical drive 1 */ #define DEV_USB 2 /* Example: Map USB MSD to physical drive 2 */ -uint8_t sdio_data_buffer[512]; /* buf for sd_read_disk/sd_write_disk function used. */ +#if defined ( __ICCARM__ ) /* iar compiler */ + #pragma data_alignment=4 +#endif +ALIGNED_HEAD uint8_t sdio_data_buffer[512] ALIGNED_TAIL; /* buf for sd_read_disk/sd_write_disk function used. */ sd_error_status_type sd_read_disk(uint8_t *buf, uint32_t sector, uint8_t cnt); sd_error_status_type sd_write_disk(const uint8_t *buf, uint32_t sector, uint8_t cnt); diff --git a/project/at_start_f437/examples/spi/crc_transfer_polling/inc/at32f435_437_conf.h b/project/at_start_f437/examples/spi/crc_transfer_polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/spi/crc_transfer_polling/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/spi/crc_transfer_polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvoptx b/project/at_start_f437/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvoptx index 232ebe03..4fdb0355 100644 --- a/project/at_start_f437/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvoptx +++ b/project/at_start_f437/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvprojx b/project/at_start_f437/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvprojx index 667ac4a6..5c08b97e 100644 --- a/project/at_start_f437/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvprojx +++ b/project/at_start_f437/examples/spi/crc_transfer_polling/mdk_v5/crc_transfer_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/spi/crc_transfer_polling/src/at32f435_437_clock.c b/project/at_start_f437/examples/spi/crc_transfer_polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/spi/crc_transfer_polling/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/spi/crc_transfer_polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/spi/fullduplex_polling/inc/at32f435_437_conf.h b/project/at_start_f437/examples/spi/fullduplex_polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/spi/fullduplex_polling/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/spi/fullduplex_polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvoptx b/project/at_start_f437/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvoptx index b546afcf..2d214faf 100644 --- a/project/at_start_f437/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvoptx +++ b/project/at_start_f437/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvprojx b/project/at_start_f437/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvprojx index ebe7cb3d..efef72d1 100644 --- a/project/at_start_f437/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvprojx +++ b/project/at_start_f437/examples/spi/fullduplex_polling/mdk_v5/fullduplex_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/spi/fullduplex_polling/src/at32f435_437_clock.c b/project/at_start_f437/examples/spi/fullduplex_polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/spi/fullduplex_polling/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/spi/fullduplex_polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/spi/halfduplex_interrupt/inc/at32f435_437_conf.h b/project/at_start_f437/examples/spi/halfduplex_interrupt/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/spi/halfduplex_interrupt/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/spi/halfduplex_interrupt/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx b/project/at_start_f437/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx index 4a93353f..c96af29e 100644 --- a/project/at_start_f437/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx +++ b/project/at_start_f437/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx b/project/at_start_f437/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx index 969634f1..b79c30b3 100644 --- a/project/at_start_f437/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx +++ b/project/at_start_f437/examples/spi/halfduplex_interrupt/mdk_v5/halfduplex_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/spi/halfduplex_interrupt/src/at32f435_437_clock.c b/project/at_start_f437/examples/spi/halfduplex_interrupt/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/spi/halfduplex_interrupt/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/spi/halfduplex_interrupt/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/inc/at32f435_437_conf.h b/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvoptx b/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvoptx index 3caa5e12..821dcac6 100644 --- a/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvoptx +++ b/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvprojx b/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvprojx index 10fcf3f0..42c3e71f 100644 --- a/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvprojx +++ b/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/mdk_v5/halfduplex_transceiver_switch.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/src/at32f435_437_clock.c b/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/spi/halfduplex_transceiver_switch/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/spi/only_receive_mode_polling/inc/at32f435_437_conf.h b/project/at_start_f437/examples/spi/only_receive_mode_polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/spi/only_receive_mode_polling/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/spi/only_receive_mode_polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvoptx b/project/at_start_f437/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvoptx index 99dde7d5..babf22d3 100644 --- a/project/at_start_f437/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvoptx +++ b/project/at_start_f437/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvprojx b/project/at_start_f437/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvprojx index 85f12ec3..8b78df93 100644 --- a/project/at_start_f437/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvprojx +++ b/project/at_start_f437/examples/spi/only_receive_mode_polling/mdk_v5/only_receive_mode_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/spi/only_receive_mode_polling/src/at32f435_437_clock.c b/project/at_start_f437/examples/spi/only_receive_mode_polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/spi/only_receive_mode_polling/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/spi/only_receive_mode_polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/spi/ti_fullduplex_dma/inc/at32f435_437_conf.h b/project/at_start_f437/examples/spi/ti_fullduplex_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/spi/ti_fullduplex_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/spi/ti_fullduplex_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvoptx b/project/at_start_f437/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvoptx index 28995aea..2a3dbf73 100644 --- a/project/at_start_f437/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvoptx +++ b/project/at_start_f437/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvprojx b/project/at_start_f437/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvprojx index e502b709..35fa8597 100644 --- a/project/at_start_f437/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvprojx +++ b/project/at_start_f437/examples/spi/ti_fullduplex_dma/mdk_v5/ti_fullduplex_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/spi/ti_fullduplex_dma/src/at32f435_437_clock.c b/project/at_start_f437/examples/spi/ti_fullduplex_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/spi/ti_fullduplex_dma/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/spi/ti_fullduplex_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/inc/at32f435_437_conf.h b/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvoptx b/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvoptx index 66ca0781..e29c569b 100644 --- a/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvoptx +++ b/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvprojx b/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvprojx index 0ecfe913..6a966bf3 100644 --- a/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvprojx +++ b/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/mdk_v5/use_jtagpin_hardwarecs_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/src/at32f435_437_clock.c b/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/spi/use_jtagpin_hardwarecs_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/spi/w25q_flash/inc/at32f435_437_conf.h b/project/at_start_f437/examples/spi/w25q_flash/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/spi/w25q_flash/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/spi/w25q_flash/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvoptx b/project/at_start_f437/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvoptx index 5081a660..d66299a9 100644 --- a/project/at_start_f437/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvoptx +++ b/project/at_start_f437/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvprojx b/project/at_start_f437/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvprojx index e11aba87..ff6b19a1 100644 --- a/project/at_start_f437/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvprojx +++ b/project/at_start_f437/examples/spi/w25q_flash/mdk_v5/w25q_flash.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -488,6 +488,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/spi/w25q_flash/src/at32f435_437_clock.c b/project/at_start_f437/examples/spi/w25q_flash/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/spi/w25q_flash/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/spi/w25q_flash/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/sram/extend_sram/inc/at32f435_437_conf.h b/project/at_start_f437/examples/sram/extend_sram/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/sram/extend_sram/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/sram/extend_sram/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/sram/extend_sram/mdk_v5/extend_sram.uvoptx b/project/at_start_f437/examples/sram/extend_sram/mdk_v5/extend_sram.uvoptx index c1262584..55ebb279 100644 --- a/project/at_start_f437/examples/sram/extend_sram/mdk_v5/extend_sram.uvoptx +++ b/project/at_start_f437/examples/sram/extend_sram/mdk_v5/extend_sram.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/sram/extend_sram/mdk_v5/extend_sram.uvprojx b/project/at_start_f437/examples/sram/extend_sram/mdk_v5/extend_sram.uvprojx index 9e6a54eb..390363be 100644 --- a/project/at_start_f437/examples/sram/extend_sram/mdk_v5/extend_sram.uvprojx +++ b/project/at_start_f437/examples/sram/extend_sram/mdk_v5/extend_sram.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -3234,4 +3234,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/sram/extend_sram/src/at32f435_437_clock.c b/project/at_start_f437/examples/sram/extend_sram/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/sram/extend_sram/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/sram/extend_sram/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/6_steps/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/6_steps/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/6_steps/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/6_steps/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/6_steps/mdk_v5/6_steps.uvoptx b/project/at_start_f437/examples/tmr/6_steps/mdk_v5/6_steps.uvoptx index d59324a1..6b36d3ad 100644 --- a/project/at_start_f437/examples/tmr/6_steps/mdk_v5/6_steps.uvoptx +++ b/project/at_start_f437/examples/tmr/6_steps/mdk_v5/6_steps.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/6_steps/mdk_v5/6_steps.uvprojx b/project/at_start_f437/examples/tmr/6_steps/mdk_v5/6_steps.uvprojx index ef57d596..4b76b40c 100644 --- a/project/at_start_f437/examples/tmr/6_steps/mdk_v5/6_steps.uvprojx +++ b/project/at_start_f437/examples/tmr/6_steps/mdk_v5/6_steps.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/6_steps/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/6_steps/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/6_steps/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/6_steps/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/7_pwm_output/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/7_pwm_output/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/7_pwm_output/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/7_pwm_output/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvoptx b/project/at_start_f437/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvoptx index cfcdeb9d..0e67ef01 100644 --- a/project/at_start_f437/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvoptx +++ b/project/at_start_f437/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvprojx b/project/at_start_f437/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvprojx index 4b8cd81c..e94175ff 100644 --- a/project/at_start_f437/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvprojx +++ b/project/at_start_f437/examples/tmr/7_pwm_output/mdk_v5/7_pwm_output.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/7_pwm_output/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/7_pwm_output/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/7_pwm_output/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/7_pwm_output/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/cascade_synchro/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/cascade_synchro/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/cascade_synchro/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/cascade_synchro/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvoptx b/project/at_start_f437/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvoptx index fc21c380..4231b0a9 100644 --- a/project/at_start_f437/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvoptx +++ b/project/at_start_f437/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvprojx b/project/at_start_f437/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvprojx index 5c61a072..21f7388c 100644 --- a/project/at_start_f437/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvprojx +++ b/project/at_start_f437/examples/tmr/cascade_synchro/mdk_v5/cascade_synchro.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/cascade_synchro/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/cascade_synchro/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/cascade_synchro/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/cascade_synchro/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/complementary_signals/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/complementary_signals/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/complementary_signals/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/complementary_signals/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvoptx b/project/at_start_f437/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvoptx index cacff133..525a2e02 100644 --- a/project/at_start_f437/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvoptx +++ b/project/at_start_f437/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvprojx b/project/at_start_f437/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvprojx index 7583b0dc..4fbdcd60 100644 --- a/project/at_start_f437/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvprojx +++ b/project/at_start_f437/examples/tmr/complementary_signals/mdk_v5/complementary_signals.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/complementary_signals/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/complementary_signals/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/complementary_signals/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/complementary_signals/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/dma/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/dma/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/dma/mdk_v5/dma.uvoptx b/project/at_start_f437/examples/tmr/dma/mdk_v5/dma.uvoptx index c6c1e7e5..e1e01373 100644 --- a/project/at_start_f437/examples/tmr/dma/mdk_v5/dma.uvoptx +++ b/project/at_start_f437/examples/tmr/dma/mdk_v5/dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/dma/mdk_v5/dma.uvprojx b/project/at_start_f437/examples/tmr/dma/mdk_v5/dma.uvprojx index 1df21ce9..38f5c250 100644 --- a/project/at_start_f437/examples/tmr/dma/mdk_v5/dma.uvprojx +++ b/project/at_start_f437/examples/tmr/dma/mdk_v5/dma.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/dma/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/dma/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/dma_burst/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/dma_burst/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/dma_burst/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/dma_burst/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/dma_burst/mdk_v5/dma_burst.uvoptx b/project/at_start_f437/examples/tmr/dma_burst/mdk_v5/dma_burst.uvoptx index 701d2762..77fa9bd8 100644 --- a/project/at_start_f437/examples/tmr/dma_burst/mdk_v5/dma_burst.uvoptx +++ b/project/at_start_f437/examples/tmr/dma_burst/mdk_v5/dma_burst.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/dma_burst/mdk_v5/dma_burst.uvprojx b/project/at_start_f437/examples/tmr/dma_burst/mdk_v5/dma_burst.uvprojx index efeea154..7a606edf 100644 --- a/project/at_start_f437/examples/tmr/dma_burst/mdk_v5/dma_burst.uvprojx +++ b/project/at_start_f437/examples/tmr/dma_burst/mdk_v5/dma_burst.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/dma_burst/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/dma_burst/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/dma_burst/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/dma_burst/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/encoder_tmr2/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/encoder_tmr2/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/encoder_tmr2/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/encoder_tmr2/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvoptx b/project/at_start_f437/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvoptx index 8a212c24..b95bcd64 100644 --- a/project/at_start_f437/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvoptx +++ b/project/at_start_f437/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvprojx b/project/at_start_f437/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvprojx index 3c38caca..bad63b30 100644 --- a/project/at_start_f437/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvprojx +++ b/project/at_start_f437/examples/tmr/encoder_tmr2/mdk_v5/encoder_tmr2.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/encoder_tmr2/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/encoder_tmr2/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/encoder_tmr2/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/encoder_tmr2/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/external_clock/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/external_clock/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/external_clock/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/external_clock/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/external_clock/mdk_v5/external_clock.uvoptx b/project/at_start_f437/examples/tmr/external_clock/mdk_v5/external_clock.uvoptx index 68222a04..0ba3338d 100644 --- a/project/at_start_f437/examples/tmr/external_clock/mdk_v5/external_clock.uvoptx +++ b/project/at_start_f437/examples/tmr/external_clock/mdk_v5/external_clock.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/external_clock/mdk_v5/external_clock.uvprojx b/project/at_start_f437/examples/tmr/external_clock/mdk_v5/external_clock.uvprojx index f2cda688..096fb675 100644 --- a/project/at_start_f437/examples/tmr/external_clock/mdk_v5/external_clock.uvprojx +++ b/project/at_start_f437/examples/tmr/external_clock/mdk_v5/external_clock.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/external_clock/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/external_clock/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/external_clock/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/external_clock/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/hall_xor_tmr2/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/hall_xor_tmr2/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/hall_xor_tmr2/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/hall_xor_tmr2/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvoptx b/project/at_start_f437/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvoptx index f2c5ff8c..a3f397c1 100644 --- a/project/at_start_f437/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvoptx +++ b/project/at_start_f437/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvprojx b/project/at_start_f437/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvprojx index 742f8a61..a2a07bc7 100644 --- a/project/at_start_f437/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvprojx +++ b/project/at_start_f437/examples/tmr/hall_xor_tmr2/mdk_v5/hall_xor_tmr2.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/hall_xor_tmr2/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/hall_xor_tmr2/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/hall_xor_tmr2/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/hall_xor_tmr2/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/hang_mode/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/hang_mode/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/hang_mode/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/hang_mode/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/hang_mode/mdk_v5/hang_mode.uvoptx b/project/at_start_f437/examples/tmr/hang_mode/mdk_v5/hang_mode.uvoptx index abb399c9..1269bfb8 100644 --- a/project/at_start_f437/examples/tmr/hang_mode/mdk_v5/hang_mode.uvoptx +++ b/project/at_start_f437/examples/tmr/hang_mode/mdk_v5/hang_mode.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/hang_mode/mdk_v5/hang_mode.uvprojx b/project/at_start_f437/examples/tmr/hang_mode/mdk_v5/hang_mode.uvprojx index aed84a5f..38f29490 100644 --- a/project/at_start_f437/examples/tmr/hang_mode/mdk_v5/hang_mode.uvprojx +++ b/project/at_start_f437/examples/tmr/hang_mode/mdk_v5/hang_mode.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/hang_mode/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/hang_mode/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/hang_mode/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/hang_mode/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/input_capture/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/input_capture/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/input_capture/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/input_capture/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/input_capture/mdk_v5/input_capture.uvoptx b/project/at_start_f437/examples/tmr/input_capture/mdk_v5/input_capture.uvoptx index 4924c466..7ef4415d 100644 --- a/project/at_start_f437/examples/tmr/input_capture/mdk_v5/input_capture.uvoptx +++ b/project/at_start_f437/examples/tmr/input_capture/mdk_v5/input_capture.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/input_capture/mdk_v5/input_capture.uvprojx b/project/at_start_f437/examples/tmr/input_capture/mdk_v5/input_capture.uvprojx index 70e47c8d..86aeae25 100644 --- a/project/at_start_f437/examples/tmr/input_capture/mdk_v5/input_capture.uvprojx +++ b/project/at_start_f437/examples/tmr/input_capture/mdk_v5/input_capture.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/input_capture/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/input_capture/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/input_capture/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/input_capture/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/oc_high/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/oc_high/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/oc_high/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/oc_high/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/oc_high/mdk_v5/oc_high.uvoptx b/project/at_start_f437/examples/tmr/oc_high/mdk_v5/oc_high.uvoptx index fa38d8b7..b9f5bbe4 100644 --- a/project/at_start_f437/examples/tmr/oc_high/mdk_v5/oc_high.uvoptx +++ b/project/at_start_f437/examples/tmr/oc_high/mdk_v5/oc_high.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/oc_high/mdk_v5/oc_high.uvprojx b/project/at_start_f437/examples/tmr/oc_high/mdk_v5/oc_high.uvprojx index 01ef19dd..aa1c7c2d 100644 --- a/project/at_start_f437/examples/tmr/oc_high/mdk_v5/oc_high.uvprojx +++ b/project/at_start_f437/examples/tmr/oc_high/mdk_v5/oc_high.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/oc_high/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/oc_high/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/oc_high/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/oc_high/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/oc_low/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/oc_low/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/oc_low/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/oc_low/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/oc_low/mdk_v5/oc_low.uvoptx b/project/at_start_f437/examples/tmr/oc_low/mdk_v5/oc_low.uvoptx index 00ca9b2b..cf670791 100644 --- a/project/at_start_f437/examples/tmr/oc_low/mdk_v5/oc_low.uvoptx +++ b/project/at_start_f437/examples/tmr/oc_low/mdk_v5/oc_low.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/oc_low/mdk_v5/oc_low.uvprojx b/project/at_start_f437/examples/tmr/oc_low/mdk_v5/oc_low.uvprojx index 39fad65a..af23d1e6 100644 --- a/project/at_start_f437/examples/tmr/oc_low/mdk_v5/oc_low.uvprojx +++ b/project/at_start_f437/examples/tmr/oc_low/mdk_v5/oc_low.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/oc_low/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/oc_low/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/oc_low/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/oc_low/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/oc_toggle_tmr3/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/oc_toggle_tmr3/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/oc_toggle_tmr3/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/oc_toggle_tmr3/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvoptx b/project/at_start_f437/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvoptx index 47fbde12..5b727256 100644 --- a/project/at_start_f437/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvoptx +++ b/project/at_start_f437/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvprojx b/project/at_start_f437/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvprojx index c7c0e79a..867dcc9e 100644 --- a/project/at_start_f437/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvprojx +++ b/project/at_start_f437/examples/tmr/oc_toggle_tmr3/mdk_v5/oc_toggle_tmr3.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/oc_toggle_tmr3/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/oc_toggle_tmr3/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/oc_toggle_tmr3/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/oc_toggle_tmr3/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/oc_toggle_tmr9/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/oc_toggle_tmr9/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/oc_toggle_tmr9/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/oc_toggle_tmr9/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvoptx b/project/at_start_f437/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvoptx index 35d1bbde..a42e2fae 100644 --- a/project/at_start_f437/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvoptx +++ b/project/at_start_f437/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvprojx b/project/at_start_f437/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvprojx index c6da7f38..18eccf91 100644 --- a/project/at_start_f437/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvprojx +++ b/project/at_start_f437/examples/tmr/oc_toggle_tmr9/mdk_v5/oc_toggle_tmr9.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/oc_toggle_tmr9/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/oc_toggle_tmr9/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/oc_toggle_tmr9/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/oc_toggle_tmr9/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/one_cycle/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/one_cycle/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/one_cycle/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/one_cycle/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/one_cycle/mdk_v5/one_cycle.uvoptx b/project/at_start_f437/examples/tmr/one_cycle/mdk_v5/one_cycle.uvoptx index 46f5d402..1f21c8ae 100644 --- a/project/at_start_f437/examples/tmr/one_cycle/mdk_v5/one_cycle.uvoptx +++ b/project/at_start_f437/examples/tmr/one_cycle/mdk_v5/one_cycle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/one_cycle/mdk_v5/one_cycle.uvprojx b/project/at_start_f437/examples/tmr/one_cycle/mdk_v5/one_cycle.uvprojx index 06b5dd32..a43e012d 100644 --- a/project/at_start_f437/examples/tmr/one_cycle/mdk_v5/one_cycle.uvprojx +++ b/project/at_start_f437/examples/tmr/one_cycle/mdk_v5/one_cycle.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/one_cycle/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/one_cycle/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/one_cycle/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/one_cycle/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/parallel_synchro/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/parallel_synchro/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/parallel_synchro/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/parallel_synchro/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvoptx b/project/at_start_f437/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvoptx index 9ac17b20..8cd54711 100644 --- a/project/at_start_f437/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvoptx +++ b/project/at_start_f437/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvprojx b/project/at_start_f437/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvprojx index ec4b172d..3dcffed1 100644 --- a/project/at_start_f437/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvprojx +++ b/project/at_start_f437/examples/tmr/parallel_synchro/mdk_v5/parallel_synchro.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/parallel_synchro/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/parallel_synchro/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/parallel_synchro/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/parallel_synchro/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/pwm_input/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/pwm_input/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/pwm_input/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/pwm_input/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/pwm_input/mdk_v5/pwm_input.uvoptx b/project/at_start_f437/examples/tmr/pwm_input/mdk_v5/pwm_input.uvoptx index d247963a..58b93095 100644 --- a/project/at_start_f437/examples/tmr/pwm_input/mdk_v5/pwm_input.uvoptx +++ b/project/at_start_f437/examples/tmr/pwm_input/mdk_v5/pwm_input.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/pwm_input/mdk_v5/pwm_input.uvprojx b/project/at_start_f437/examples/tmr/pwm_input/mdk_v5/pwm_input.uvprojx index 7208b0a8..e8e9cebf 100644 --- a/project/at_start_f437/examples/tmr/pwm_input/mdk_v5/pwm_input.uvprojx +++ b/project/at_start_f437/examples/tmr/pwm_input/mdk_v5/pwm_input.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/pwm_input/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/pwm_input/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/pwm_input/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/pwm_input/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/pwm_input_dma/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/pwm_input_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/pwm_input_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/pwm_input_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvoptx b/project/at_start_f437/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvoptx index fd221905..e41aafa3 100644 --- a/project/at_start_f437/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvoptx +++ b/project/at_start_f437/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvprojx b/project/at_start_f437/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvprojx index 9c707c26..ca1ac2bf 100644 --- a/project/at_start_f437/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvprojx +++ b/project/at_start_f437/examples/tmr/pwm_input_dma/mdk_v5/pwm_input_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/pwm_input_dma/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/pwm_input_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/pwm_input_dma/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/pwm_input_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/pwm_output_simulate/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/pwm_output_simulate/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/pwm_output_simulate/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/pwm_output_simulate/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvoptx b/project/at_start_f437/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvoptx index 391e1a98..18361190 100644 --- a/project/at_start_f437/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvoptx +++ b/project/at_start_f437/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvprojx b/project/at_start_f437/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvprojx index d2c632d7..b068a31d 100644 --- a/project/at_start_f437/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvprojx +++ b/project/at_start_f437/examples/tmr/pwm_output_simulate/mdk_v5/pwm_output_simulate.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/pwm_output_simulate/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/pwm_output_simulate/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/pwm_output_simulate/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/pwm_output_simulate/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/pwm_output_tmr10/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/pwm_output_tmr10/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/pwm_output_tmr10/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/pwm_output_tmr10/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvoptx b/project/at_start_f437/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvoptx index e39c667d..27f4f855 100644 --- a/project/at_start_f437/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvoptx +++ b/project/at_start_f437/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvprojx b/project/at_start_f437/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvprojx index d82e72bf..9036cc66 100644 --- a/project/at_start_f437/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvprojx +++ b/project/at_start_f437/examples/tmr/pwm_output_tmr10/mdk_v5/pwm_output_tmr10.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/pwm_output_tmr10/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/pwm_output_tmr10/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/pwm_output_tmr10/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/pwm_output_tmr10/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/pwm_output_tmr3/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/pwm_output_tmr3/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/pwm_output_tmr3/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/pwm_output_tmr3/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvoptx b/project/at_start_f437/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvoptx index 490648a2..1d661a03 100644 --- a/project/at_start_f437/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvoptx +++ b/project/at_start_f437/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvprojx b/project/at_start_f437/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvprojx index 0aee1d42..97e2daa7 100644 --- a/project/at_start_f437/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvprojx +++ b/project/at_start_f437/examples/tmr/pwm_output_tmr3/mdk_v5/pwm_output_tmr3.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/pwm_output_tmr3/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/pwm_output_tmr3/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/pwm_output_tmr3/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/pwm_output_tmr3/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/timer_base/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/timer_base/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/timer_base/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/timer_base/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/timer_base/mdk_v5/timer_base.uvoptx b/project/at_start_f437/examples/tmr/timer_base/mdk_v5/timer_base.uvoptx index 38a84e81..8c860b45 100644 --- a/project/at_start_f437/examples/tmr/timer_base/mdk_v5/timer_base.uvoptx +++ b/project/at_start_f437/examples/tmr/timer_base/mdk_v5/timer_base.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/timer_base/mdk_v5/timer_base.uvprojx b/project/at_start_f437/examples/tmr/timer_base/mdk_v5/timer_base.uvprojx index a0414837..a2ed5ec1 100644 --- a/project/at_start_f437/examples/tmr/timer_base/mdk_v5/timer_base.uvprojx +++ b/project/at_start_f437/examples/tmr/timer_base/mdk_v5/timer_base.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/timer_base/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/timer_base/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/timer_base/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/timer_base/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/tmr1_synchro/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/tmr1_synchro/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/tmr1_synchro/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/tmr1_synchro/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvoptx b/project/at_start_f437/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvoptx index cafe8cb1..a47d3a77 100644 --- a/project/at_start_f437/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvoptx +++ b/project/at_start_f437/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvprojx b/project/at_start_f437/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvprojx index eba009dd..dea2b188 100644 --- a/project/at_start_f437/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvprojx +++ b/project/at_start_f437/examples/tmr/tmr1_synchro/mdk_v5/tmr1_synchro.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/tmr1_synchro/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/tmr1_synchro/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/tmr1_synchro/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/tmr1_synchro/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/tmr/tmr2_32bit/inc/at32f435_437_conf.h b/project/at_start_f437/examples/tmr/tmr2_32bit/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/tmr/tmr2_32bit/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/tmr/tmr2_32bit/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvoptx b/project/at_start_f437/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvoptx index c9316b35..a7381664 100644 --- a/project/at_start_f437/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvoptx +++ b/project/at_start_f437/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvprojx b/project/at_start_f437/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvprojx index 8ae2c47f..9b19a4a8 100644 --- a/project/at_start_f437/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvprojx +++ b/project/at_start_f437/examples/tmr/tmr2_32bit/mdk_v5/tmr2_32bit.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -478,6 +478,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/tmr/tmr2_32bit/src/at32f435_437_clock.c b/project/at_start_f437/examples/tmr/tmr2_32bit/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/tmr/tmr2_32bit/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/tmr/tmr2_32bit/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usart/half_duplex/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/half_duplex/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usart/half_duplex/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/half_duplex/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/half_duplex/mdk_v5/half_duplex.uvoptx b/project/at_start_f437/examples/usart/half_duplex/mdk_v5/half_duplex.uvoptx index 7eac6664..c5d9cb82 100644 --- a/project/at_start_f437/examples/usart/half_duplex/mdk_v5/half_duplex.uvoptx +++ b/project/at_start_f437/examples/usart/half_duplex/mdk_v5/half_duplex.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/half_duplex/mdk_v5/half_duplex.uvprojx b/project/at_start_f437/examples/usart/half_duplex/mdk_v5/half_duplex.uvprojx index c7aefcf2..4404d3f3 100644 --- a/project/at_start_f437/examples/usart/half_duplex/mdk_v5/half_duplex.uvprojx +++ b/project/at_start_f437/examples/usart/half_duplex/mdk_v5/half_duplex.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usart/half_duplex/src/at32f435_437_clock.c b/project/at_start_f437/examples/usart/half_duplex/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usart/half_duplex/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usart/half_duplex/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usart/hw_flow_control/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/hw_flow_control/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usart/hw_flow_control/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/hw_flow_control/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvoptx b/project/at_start_f437/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvoptx index 22c5551a..bf528755 100644 --- a/project/at_start_f437/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvoptx +++ b/project/at_start_f437/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvprojx b/project/at_start_f437/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvprojx index 33504ee4..2f107358 100644 --- a/project/at_start_f437/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvprojx +++ b/project/at_start_f437/examples/usart/hw_flow_control/mdk_v5/hw_flow_control.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usart/hw_flow_control/src/at32f435_437_clock.c b/project/at_start_f437/examples/usart/hw_flow_control/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usart/hw_flow_control/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usart/hw_flow_control/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usart/idle_detection/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/idle_detection/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usart/idle_detection/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/idle_detection/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/idle_detection/mdk_v5/idle_detection.uvoptx b/project/at_start_f437/examples/usart/idle_detection/mdk_v5/idle_detection.uvoptx index 969fe704..f21fde3c 100644 --- a/project/at_start_f437/examples/usart/idle_detection/mdk_v5/idle_detection.uvoptx +++ b/project/at_start_f437/examples/usart/idle_detection/mdk_v5/idle_detection.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/idle_detection/mdk_v5/idle_detection.uvprojx b/project/at_start_f437/examples/usart/idle_detection/mdk_v5/idle_detection.uvprojx index d1367e5c..10e8ba08 100644 --- a/project/at_start_f437/examples/usart/idle_detection/mdk_v5/idle_detection.uvprojx +++ b/project/at_start_f437/examples/usart/idle_detection/mdk_v5/idle_detection.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usart/idle_detection/src/at32f435_437_clock.c b/project/at_start_f437/examples/usart/idle_detection/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usart/idle_detection/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usart/idle_detection/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usart/interrupt/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/interrupt/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usart/interrupt/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/interrupt/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/interrupt/mdk_v5/interrupt.uvoptx b/project/at_start_f437/examples/usart/interrupt/mdk_v5/interrupt.uvoptx index 48777083..d1dedae4 100644 --- a/project/at_start_f437/examples/usart/interrupt/mdk_v5/interrupt.uvoptx +++ b/project/at_start_f437/examples/usart/interrupt/mdk_v5/interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/interrupt/mdk_v5/interrupt.uvprojx b/project/at_start_f437/examples/usart/interrupt/mdk_v5/interrupt.uvprojx index 87d44bb5..e47d018e 100644 --- a/project/at_start_f437/examples/usart/interrupt/mdk_v5/interrupt.uvprojx +++ b/project/at_start_f437/examples/usart/interrupt/mdk_v5/interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/usart/interrupt/src/at32f435_437_clock.c b/project/at_start_f437/examples/usart/interrupt/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usart/interrupt/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usart/interrupt/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usart/irda/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/irda/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usart/irda/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/irda/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/irda/mdk_v5/irda.uvoptx b/project/at_start_f437/examples/usart/irda/mdk_v5/irda.uvoptx index e8736d89..5e83ae8a 100644 --- a/project/at_start_f437/examples/usart/irda/mdk_v5/irda.uvoptx +++ b/project/at_start_f437/examples/usart/irda/mdk_v5/irda.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/irda/mdk_v5/irda.uvprojx b/project/at_start_f437/examples/usart/irda/mdk_v5/irda.uvprojx index 269ab190..85b52e13 100644 --- a/project/at_start_f437/examples/usart/irda/mdk_v5/irda.uvprojx +++ b/project/at_start_f437/examples/usart/irda/mdk_v5/irda.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -924,4 +924,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usart/irda/src/at32f435_437_clock.c b/project/at_start_f437/examples/usart/irda/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usart/irda/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usart/irda/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usart/polling/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usart/polling/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/polling/mdk_v5/polling.uvoptx b/project/at_start_f437/examples/usart/polling/mdk_v5/polling.uvoptx index cbab3afb..19b79712 100644 --- a/project/at_start_f437/examples/usart/polling/mdk_v5/polling.uvoptx +++ b/project/at_start_f437/examples/usart/polling/mdk_v5/polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/polling/mdk_v5/polling.uvprojx b/project/at_start_f437/examples/usart/polling/mdk_v5/polling.uvprojx index c09988db..ffd00799 100644 --- a/project/at_start_f437/examples/usart/polling/mdk_v5/polling.uvprojx +++ b/project/at_start_f437/examples/usart/polling/mdk_v5/polling.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usart/polling/src/at32f435_437_clock.c b/project/at_start_f437/examples/usart/polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usart/polling/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usart/polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usart/printf/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/printf/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usart/printf/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/printf/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/printf/mdk_v5/printf.uvoptx b/project/at_start_f437/examples/usart/printf/mdk_v5/printf.uvoptx index fae44cc3..a6e629c3 100644 --- a/project/at_start_f437/examples/usart/printf/mdk_v5/printf.uvoptx +++ b/project/at_start_f437/examples/usart/printf/mdk_v5/printf.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/printf/mdk_v5/printf.uvprojx b/project/at_start_f437/examples/usart/printf/mdk_v5/printf.uvprojx index ac248a59..ca52216d 100644 --- a/project/at_start_f437/examples/usart/printf/mdk_v5/printf.uvprojx +++ b/project/at_start_f437/examples/usart/printf/mdk_v5/printf.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -473,6 +473,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/usart/printf/src/at32f435_437_clock.c b/project/at_start_f437/examples/usart/printf/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usart/printf/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usart/printf/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usart/receiver_mute/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/receiver_mute/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usart/receiver_mute/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/receiver_mute/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvoptx b/project/at_start_f437/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvoptx index 9df0dace..c1973308 100644 --- a/project/at_start_f437/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvoptx +++ b/project/at_start_f437/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvprojx b/project/at_start_f437/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvprojx index 74fad2ad..7d5e9192 100644 --- a/project/at_start_f437/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvprojx +++ b/project/at_start_f437/examples/usart/receiver_mute/mdk_v5/receiver_mute.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usart/receiver_mute/src/at32f435_437_clock.c b/project/at_start_f437/examples/usart/receiver_mute/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usart/receiver_mute/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usart/receiver_mute/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usart/rs485/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/rs485/inc/at32f435_437_conf.h index 8645761d..4b9d618f 100644 --- a/project/at_start_f437/examples/usart/rs485/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/rs485/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/rs485/mdk_v5/rs485.uvoptx b/project/at_start_f437/examples/usart/rs485/mdk_v5/rs485.uvoptx index b438373a..c484ee32 100644 --- a/project/at_start_f437/examples/usart/rs485/mdk_v5/rs485.uvoptx +++ b/project/at_start_f437/examples/usart/rs485/mdk_v5/rs485.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/rs485/mdk_v5/rs485.uvprojx b/project/at_start_f437/examples/usart/rs485/mdk_v5/rs485.uvprojx index 0b7651d7..d4984053 100644 --- a/project/at_start_f437/examples/usart/rs485/mdk_v5/rs485.uvprojx +++ b/project/at_start_f437/examples/usart/rs485/mdk_v5/rs485.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usart/smartcard/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/smartcard/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usart/smartcard/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/smartcard/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/smartcard/mdk_v5/smartcard.uvoptx b/project/at_start_f437/examples/usart/smartcard/mdk_v5/smartcard.uvoptx index d9b91fad..2acf19a9 100644 --- a/project/at_start_f437/examples/usart/smartcard/mdk_v5/smartcard.uvoptx +++ b/project/at_start_f437/examples/usart/smartcard/mdk_v5/smartcard.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/smartcard/mdk_v5/smartcard.uvprojx b/project/at_start_f437/examples/usart/smartcard/mdk_v5/smartcard.uvprojx index 7b833993..1f457130 100644 --- a/project/at_start_f437/examples/usart/smartcard/mdk_v5/smartcard.uvprojx +++ b/project/at_start_f437/examples/usart/smartcard/mdk_v5/smartcard.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -479,4 +479,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usart/smartcard/src/at32f435_437_clock.c b/project/at_start_f437/examples/usart/smartcard/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usart/smartcard/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usart/smartcard/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usart/synchronous/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/synchronous/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usart/synchronous/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/synchronous/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/synchronous/mdk_v5/synchronous.uvoptx b/project/at_start_f437/examples/usart/synchronous/mdk_v5/synchronous.uvoptx index 11b5bc37..0411fe0b 100644 --- a/project/at_start_f437/examples/usart/synchronous/mdk_v5/synchronous.uvoptx +++ b/project/at_start_f437/examples/usart/synchronous/mdk_v5/synchronous.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/synchronous/mdk_v5/synchronous.uvprojx b/project/at_start_f437/examples/usart/synchronous/mdk_v5/synchronous.uvprojx index b429e063..e6455c82 100644 --- a/project/at_start_f437/examples/usart/synchronous/mdk_v5/synchronous.uvprojx +++ b/project/at_start_f437/examples/usart/synchronous/mdk_v5/synchronous.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usart/synchronous/src/at32f435_437_clock.c b/project/at_start_f437/examples/usart/synchronous/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usart/synchronous/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usart/synchronous/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvoptx b/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvoptx index 6677ac9d..63e72cff 100644 --- a/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvoptx +++ b/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvprojx b/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvprojx index bd073f1f..6aba5872 100644 --- a/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvprojx +++ b/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/mdk_v5/transfer_by_dma_interrupt.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/src/at32f435_437_clock.c b/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usart/transfer_by_dma_polling/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/transfer_by_dma_polling/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usart/transfer_by_dma_polling/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/transfer_by_dma_polling/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvoptx b/project/at_start_f437/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvoptx index 173f44f2..52d3e4bd 100644 --- a/project/at_start_f437/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvoptx +++ b/project/at_start_f437/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvprojx b/project/at_start_f437/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvprojx index 3c85f4f3..51811f5d 100644 --- a/project/at_start_f437/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvprojx +++ b/project/at_start_f437/examples/usart/transfer_by_dma_polling/mdk_v5/transfer_by_dma_polling.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -474,4 +474,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usart/transfer_by_dma_polling/src/at32f435_437_clock.c b/project/at_start_f437/examples/usart/transfer_by_dma_polling/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usart/transfer_by_dma_polling/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usart/transfer_by_dma_polling/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usart/tx_rx_swap/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usart/tx_rx_swap/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usart/tx_rx_swap/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usart/tx_rx_swap/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvoptx b/project/at_start_f437/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvoptx index 4db8aa03..9ccde500 100644 --- a/project/at_start_f437/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvoptx +++ b/project/at_start_f437/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvprojx b/project/at_start_f437/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvprojx index 246182a2..91655e78 100644 --- a/project/at_start_f437/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvprojx +++ b/project/at_start_f437/examples/usart/tx_rx_swap/mdk_v5/tx_rx_swap.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -469,4 +469,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usart/tx_rx_swap/src/at32f435_437_clock.c b/project/at_start_f437/examples/usart/tx_rx_swap/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usart/tx_rx_swap/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usart/tx_rx_swap/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/audio/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/audio/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/audio/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/audio/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/audio/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/audio/inc/usb_conf.h index f5f3b9a9..ec6849ce 100644 --- a/project/at_start_f437/examples/usb_device/audio/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/audio/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/audio/mdk_v5/audio.uvoptx b/project/at_start_f437/examples/usb_device/audio/mdk_v5/audio.uvoptx index bd119aca..97cbf370 100644 --- a/project/at_start_f437/examples/usb_device/audio/mdk_v5/audio.uvoptx +++ b/project/at_start_f437/examples/usb_device/audio/mdk_v5/audio.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/audio/mdk_v5/audio.uvprojx b/project/at_start_f437/examples/usb_device/audio/mdk_v5/audio.uvprojx index 78f3215c..0cf242b7 100644 --- a/project/at_start_f437/examples/usb_device/audio/mdk_v5/audio.uvprojx +++ b/project/at_start_f437/examples/usb_device/audio/mdk_v5/audio.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -639,4 +639,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_device/audio/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/audio/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/audio/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/audio/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/audio/src/main.c b/project/at_start_f437/examples/usb_device/audio/src/main.c index 4a6d3109..3a71d331 100644 --- a/project/at_start_f437/examples/usb_device/audio/src/main.c +++ b/project/at_start_f437/examples/usb_device/audio/src/main.c @@ -211,7 +211,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_device/composite_audio_hid/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/composite_audio_hid/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/composite_audio_hid/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/composite_audio_hid/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/composite_audio_hid/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/composite_audio_hid/inc/usb_conf.h index 8777b839..02e58d76 100644 --- a/project/at_start_f437/examples/usb_device/composite_audio_hid/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/composite_audio_hid/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvoptx b/project/at_start_f437/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvoptx index 12d7376f..b581eac0 100644 --- a/project/at_start_f437/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvoptx +++ b/project/at_start_f437/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvprojx b/project/at_start_f437/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvprojx index a240140c..5539db39 100644 --- a/project/at_start_f437/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvprojx +++ b/project/at_start_f437/examples/usb_device/composite_audio_hid/mdk_v5/composite_audio_hid.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -549,4 +549,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_device/composite_audio_hid/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/composite_audio_hid/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/composite_audio_hid/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/composite_audio_hid/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/composite_audio_hid/src/main.c b/project/at_start_f437/examples/usb_device/composite_audio_hid/src/main.c index 05c22499..1bad3ae1 100644 --- a/project/at_start_f437/examples/usb_device/composite_audio_hid/src/main.c +++ b/project/at_start_f437/examples/usb_device/composite_audio_hid/src/main.c @@ -218,7 +218,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/inc/usb_conf.h index 3ded54ab..7e42472e 100644 --- a/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/inc/usb_conf.h @@ -118,7 +118,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvoptx b/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvoptx index 4d493ea8..fc2b89ac 100644 --- a/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvoptx +++ b/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvprojx b/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvprojx index 91482c2d..3bf0fa67 100644 --- a/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvprojx +++ b/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/mdk_v5/composite_vcp_keyboard.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -629,4 +629,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/src/main.c b/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/src/main.c index 10200fcb..86a84351 100644 --- a/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/src/main.c +++ b/project/at_start_f437/examples/usb_device/composite_vcp_keyboard/src/main.c @@ -339,7 +339,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_device/composite_vcp_msc/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/composite_vcp_msc/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/composite_vcp_msc/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/composite_vcp_msc/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/composite_vcp_msc/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/composite_vcp_msc/inc/usb_conf.h index 59798b5b..bf2d82e8 100644 --- a/project/at_start_f437/examples/usb_device/composite_vcp_msc/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/composite_vcp_msc/inc/usb_conf.h @@ -118,7 +118,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvoptx b/project/at_start_f437/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvoptx index f8685f90..414cb909 100644 --- a/project/at_start_f437/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvoptx +++ b/project/at_start_f437/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvprojx b/project/at_start_f437/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvprojx index 0d3f8d26..5d8deabd 100644 --- a/project/at_start_f437/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvprojx +++ b/project/at_start_f437/examples/usb_device/composite_vcp_msc/mdk_v5/composite_vcp_msc.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -639,4 +639,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_device/composite_vcp_msc/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/composite_vcp_msc/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/composite_vcp_msc/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/composite_vcp_msc/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/composite_vcp_msc/src/main.c b/project/at_start_f437/examples/usb_device/composite_vcp_msc/src/main.c index e8436b47..7ecf8368 100644 --- a/project/at_start_f437/examples/usb_device/composite_vcp_msc/src/main.c +++ b/project/at_start_f437/examples/usb_device/composite_vcp_msc/src/main.c @@ -295,7 +295,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_device/custom_hid/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/custom_hid/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/custom_hid/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/custom_hid/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/custom_hid/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/custom_hid/inc/usb_conf.h index 50aa5406..d24963a9 100644 --- a/project/at_start_f437/examples/usb_device/custom_hid/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/custom_hid/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvoptx b/project/at_start_f437/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvoptx index 3cf0d3f8..9a6b9c26 100644 --- a/project/at_start_f437/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvoptx +++ b/project/at_start_f437/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvprojx b/project/at_start_f437/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvprojx index eb882da8..310c806a 100644 --- a/project/at_start_f437/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvprojx +++ b/project/at_start_f437/examples/usb_device/custom_hid/mdk_v5/custom_hid.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -629,4 +629,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_device/custom_hid/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/custom_hid/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/custom_hid/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/custom_hid/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/custom_hid/src/main.c b/project/at_start_f437/examples/usb_device/custom_hid/src/main.c index 65e82cb9..1575df5c 100644 --- a/project/at_start_f437/examples/usb_device/custom_hid/src/main.c +++ b/project/at_start_f437/examples/usb_device/custom_hid/src/main.c @@ -212,7 +212,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_device/keyboard/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/keyboard/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/keyboard/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/keyboard/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/keyboard/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/keyboard/inc/usb_conf.h index 83740261..5b0ff82d 100644 --- a/project/at_start_f437/examples/usb_device/keyboard/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/keyboard/inc/usb_conf.h @@ -117,7 +117,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/keyboard/mdk_v5/keyboard.uvoptx b/project/at_start_f437/examples/usb_device/keyboard/mdk_v5/keyboard.uvoptx index 52cda49f..ebc71aff 100644 --- a/project/at_start_f437/examples/usb_device/keyboard/mdk_v5/keyboard.uvoptx +++ b/project/at_start_f437/examples/usb_device/keyboard/mdk_v5/keyboard.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/keyboard/mdk_v5/keyboard.uvprojx b/project/at_start_f437/examples/usb_device/keyboard/mdk_v5/keyboard.uvprojx index cb8b8819..796f3b60 100644 --- a/project/at_start_f437/examples/usb_device/keyboard/mdk_v5/keyboard.uvprojx +++ b/project/at_start_f437/examples/usb_device/keyboard/mdk_v5/keyboard.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -629,4 +629,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_device/keyboard/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/keyboard/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/keyboard/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/keyboard/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/keyboard/src/main.c b/project/at_start_f437/examples/usb_device/keyboard/src/main.c index 840f8e68..b350935e 100644 --- a/project/at_start_f437/examples/usb_device/keyboard/src/main.c +++ b/project/at_start_f437/examples/usb_device/keyboard/src/main.c @@ -292,7 +292,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_device/mouse/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/mouse/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/mouse/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/mouse/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/mouse/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/mouse/inc/usb_conf.h index 5b4f6468..1b3c11c3 100644 --- a/project/at_start_f437/examples/usb_device/mouse/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/mouse/inc/usb_conf.h @@ -118,7 +118,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/mouse/mdk_v5/mouse.uvoptx b/project/at_start_f437/examples/usb_device/mouse/mdk_v5/mouse.uvoptx index 1208b602..73d9fd6e 100644 --- a/project/at_start_f437/examples/usb_device/mouse/mdk_v5/mouse.uvoptx +++ b/project/at_start_f437/examples/usb_device/mouse/mdk_v5/mouse.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/mouse/mdk_v5/mouse.uvprojx b/project/at_start_f437/examples/usb_device/mouse/mdk_v5/mouse.uvprojx index 4701d062..0c88179d 100644 --- a/project/at_start_f437/examples/usb_device/mouse/mdk_v5/mouse.uvprojx +++ b/project/at_start_f437/examples/usb_device/mouse/mdk_v5/mouse.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -629,4 +629,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_device/mouse/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/mouse/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/mouse/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/mouse/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/mouse/src/main.c b/project/at_start_f437/examples/usb_device/mouse/src/main.c index 698a8759..27b36e6f 100644 --- a/project/at_start_f437/examples/usb_device/mouse/src/main.c +++ b/project/at_start_f437/examples/usb_device/mouse/src/main.c @@ -262,7 +262,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_device/msc/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/msc/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/msc/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/msc/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/msc/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/msc/inc/usb_conf.h index 59bbb447..5fd791ce 100644 --- a/project/at_start_f437/examples/usb_device/msc/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/msc/inc/usb_conf.h @@ -86,7 +86,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 #define OTG_PIN_ID GPIO_PINS_10 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/msc/mdk_v5/msc.uvoptx b/project/at_start_f437/examples/usb_device/msc/mdk_v5/msc.uvoptx index db0cad55..184c0a7c 100644 --- a/project/at_start_f437/examples/usb_device/msc/mdk_v5/msc.uvoptx +++ b/project/at_start_f437/examples/usb_device/msc/mdk_v5/msc.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/msc/mdk_v5/msc.uvprojx b/project/at_start_f437/examples/usb_device/msc/mdk_v5/msc.uvprojx index 5a8708a5..54c7c7ee 100644 --- a/project/at_start_f437/examples/usb_device/msc/mdk_v5/msc.uvprojx +++ b/project/at_start_f437/examples/usb_device/msc/mdk_v5/msc.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -639,4 +639,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_device/msc/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/msc/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/msc/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/msc/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/msc/src/main.c b/project/at_start_f437/examples/usb_device/msc/src/main.c index f5004b09..f918986a 100644 --- a/project/at_start_f437/examples/usb_device/msc/src/main.c +++ b/project/at_start_f437/examples/usb_device/msc/src/main.c @@ -208,7 +208,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/inc/usb_conf.h index b8f4f207..a1f1bb0a 100644 --- a/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/inc/usb_conf.h @@ -112,7 +112,7 @@ extern "C" { #define OTG2_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG2_PIN_ID GPIO_PINS_12 -#define OTG2_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG2_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG2_PIN_SOF_GPIO GPIOA #define OTG2_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvoptx b/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvoptx index b6028d8a..974dc756 100644 --- a/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvoptx +++ b/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvprojx b/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvprojx index 712a11f1..6d4ca7a5 100644 --- a/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvprojx +++ b/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/mdk_v5/otg1_host_otg2_device_demo.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -674,4 +674,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/src/main.c b/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/src/main.c index 932f5a52..476544d9 100644 --- a/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/src/main.c +++ b/project/at_start_f437/examples/usb_device/otg1_host_otg2_device_demo/src/main.c @@ -283,7 +283,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_device/printer/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/printer/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/printer/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/printer/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/printer/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/printer/inc/usb_conf.h index 48b6e0ef..a0e1daac 100644 --- a/project/at_start_f437/examples/usb_device/printer/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/printer/inc/usb_conf.h @@ -117,7 +117,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/printer/mdk_v5/printer.uvoptx b/project/at_start_f437/examples/usb_device/printer/mdk_v5/printer.uvoptx index 6e8779ee..e75b2f16 100644 --- a/project/at_start_f437/examples/usb_device/printer/mdk_v5/printer.uvoptx +++ b/project/at_start_f437/examples/usb_device/printer/mdk_v5/printer.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/printer/mdk_v5/printer.uvprojx b/project/at_start_f437/examples/usb_device/printer/mdk_v5/printer.uvprojx index 262a78f9..31221518 100644 --- a/project/at_start_f437/examples/usb_device/printer/mdk_v5/printer.uvprojx +++ b/project/at_start_f437/examples/usb_device/printer/mdk_v5/printer.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -629,4 +629,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_device/printer/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/printer/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/printer/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/printer/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/printer/src/main.c b/project/at_start_f437/examples/usb_device/printer/src/main.c index 76461668..deababec 100644 --- a/project/at_start_f437/examples/usb_device/printer/src/main.c +++ b/project/at_start_f437/examples/usb_device/printer/src/main.c @@ -210,7 +210,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_device/two_otg_device_demo/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/two_otg_device_demo/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/two_otg_device_demo/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/two_otg_device_demo/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/two_otg_device_demo/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/two_otg_device_demo/inc/usb_conf.h index 1e689fd8..e038c192 100644 --- a/project/at_start_f437/examples/usb_device/two_otg_device_demo/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/two_otg_device_demo/inc/usb_conf.h @@ -109,7 +109,7 @@ extern "C" { #define OTG2_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG2_PIN_ID GPIO_PINS_12 -#define OTG2_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG2_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG2_PIN_SOF_GPIO GPIOA #define OTG2_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvoptx b/project/at_start_f437/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvoptx index 49c24299..717bc582 100644 --- a/project/at_start_f437/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvoptx +++ b/project/at_start_f437/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvprojx b/project/at_start_f437/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvprojx index 76d61a82..7861b2a4 100644 --- a/project/at_start_f437/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvprojx +++ b/project/at_start_f437/examples/usb_device/two_otg_device_demo/mdk_v5/two_otg_device_demo.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -639,4 +639,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_device/two_otg_device_demo/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/two_otg_device_demo/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/two_otg_device_demo/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/two_otg_device_demo/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/two_otg_device_demo/src/main.c b/project/at_start_f437/examples/usb_device/two_otg_device_demo/src/main.c index 4d8a3442..9544fcee 100644 --- a/project/at_start_f437/examples/usb_device/two_otg_device_demo/src/main.c +++ b/project/at_start_f437/examples/usb_device/two_otg_device_demo/src/main.c @@ -315,7 +315,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ @@ -346,7 +346,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG2_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG2_PIN_SOF; gpio_init(OTG2_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG2_PIN_GPIO, OTG2_PIN_SOF_SOURCE, OTG2_PIN_MUX); + gpio_pin_mux_config(OTG2_PIN_SOF_GPIO, OTG2_PIN_SOF_SOURCE, OTG2_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_device/vcp_loopback/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/vcp_loopback/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/vcp_loopback/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/vcp_loopback/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/vcp_loopback/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/vcp_loopback/inc/usb_conf.h index bcdb9d3a..64c5e704 100644 --- a/project/at_start_f437/examples/usb_device/vcp_loopback/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/vcp_loopback/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvoptx b/project/at_start_f437/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvoptx index 7b934402..db1fad4c 100644 --- a/project/at_start_f437/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvoptx +++ b/project/at_start_f437/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvprojx b/project/at_start_f437/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvprojx index ecda5ec2..09452327 100644 --- a/project/at_start_f437/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvprojx +++ b/project/at_start_f437/examples/usb_device/vcp_loopback/mdk_v5/vcp_loopback.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -629,4 +629,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_device/vcp_loopback/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/vcp_loopback/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/vcp_loopback/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/vcp_loopback/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/vcp_loopback/src/main.c b/project/at_start_f437/examples/usb_device/vcp_loopback/src/main.c index 11635c75..5ce65f3b 100644 --- a/project/at_start_f437/examples/usb_device/vcp_loopback/src/main.c +++ b/project/at_start_f437/examples/usb_device/vcp_loopback/src/main.c @@ -237,7 +237,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_device/virtual_comport/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/virtual_comport/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/virtual_comport/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/virtual_comport/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/virtual_comport/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/virtual_comport/inc/usb_conf.h index 5bf1c068..ad6e2f98 100644 --- a/project/at_start_f437/examples/usb_device/virtual_comport/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/virtual_comport/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvoptx b/project/at_start_f437/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvoptx index cc9690d1..e835a71e 100644 --- a/project/at_start_f437/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvoptx +++ b/project/at_start_f437/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvprojx b/project/at_start_f437/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvprojx index 6b456926..a9c9a0af 100644 --- a/project/at_start_f437/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvprojx +++ b/project/at_start_f437/examples/usb_device/virtual_comport/mdk_v5/virtual_comport.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -633,6 +633,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/usb_device/virtual_comport/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/virtual_comport/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/virtual_comport/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/virtual_comport/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/virtual_comport/src/main.c b/project/at_start_f437/examples/usb_device/virtual_comport/src/main.c index efe849af..55936e9e 100644 --- a/project/at_start_f437/examples/usb_device/virtual_comport/src/main.c +++ b/project/at_start_f437/examples/usb_device/virtual_comport/src/main.c @@ -455,7 +455,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_device/virtual_msc_iap/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_device/virtual_msc_iap/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_device/virtual_msc_iap/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_device/virtual_msc_iap/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_device/virtual_msc_iap/inc/usb_conf.h b/project/at_start_f437/examples/usb_device/virtual_msc_iap/inc/usb_conf.h index 744e8c0a..aeee9457 100644 --- a/project/at_start_f437/examples/usb_device/virtual_msc_iap/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_device/virtual_msc_iap/inc/usb_conf.h @@ -118,7 +118,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvoptx b/project/at_start_f437/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvoptx index 7a3f694b..d4aefc09 100644 --- a/project/at_start_f437/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvoptx +++ b/project/at_start_f437/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvprojx b/project/at_start_f437/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvprojx index f6a5394e..485140b7 100644 --- a/project/at_start_f437/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvprojx +++ b/project/at_start_f437/examples/usb_device/virtual_msc_iap/mdk_v5/virtual_msc_iap.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -644,4 +644,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_device/virtual_msc_iap/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_device/virtual_msc_iap/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_device/virtual_msc_iap/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_device/virtual_msc_iap/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_device/virtual_msc_iap/src/main.c b/project/at_start_f437/examples/usb_device/virtual_msc_iap/src/main.c index ca5989e2..da145fc9 100644 --- a/project/at_start_f437/examples/usb_device/virtual_msc_iap/src/main.c +++ b/project/at_start_f437/examples/usb_device/virtual_msc_iap/src/main.c @@ -223,7 +223,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_host/cdc_demo/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_host/cdc_demo/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_host/cdc_demo/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_host/cdc_demo/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_host/cdc_demo/inc/usb_conf.h b/project/at_start_f437/examples/usb_host/cdc_demo/inc/usb_conf.h index 5ea81f74..11d9887c 100644 --- a/project/at_start_f437/examples/usb_host/cdc_demo/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_host/cdc_demo/inc/usb_conf.h @@ -119,7 +119,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_host/cdc_demo/mdk_v5/cdc.uvoptx b/project/at_start_f437/examples/usb_host/cdc_demo/mdk_v5/cdc.uvoptx index e3a3d09c..89921963 100644 --- a/project/at_start_f437/examples/usb_host/cdc_demo/mdk_v5/cdc.uvoptx +++ b/project/at_start_f437/examples/usb_host/cdc_demo/mdk_v5/cdc.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_host/cdc_demo/mdk_v5/cdc.uvprojx b/project/at_start_f437/examples/usb_host/cdc_demo/mdk_v5/cdc.uvprojx index 3264a2af..5db69a9f 100644 --- a/project/at_start_f437/examples/usb_host/cdc_demo/mdk_v5/cdc.uvprojx +++ b/project/at_start_f437/examples/usb_host/cdc_demo/mdk_v5/cdc.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -633,6 +633,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/usb_host/cdc_demo/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_host/cdc_demo/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_host/cdc_demo/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_host/cdc_demo/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_host/cdc_demo/src/main.c b/project/at_start_f437/examples/usb_host/cdc_demo/src/main.c index 702188ec..d593381d 100644 --- a/project/at_start_f437/examples/usb_host/cdc_demo/src/main.c +++ b/project/at_start_f437/examples/usb_host/cdc_demo/src/main.c @@ -239,7 +239,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_host/hid_demo/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_host/hid_demo/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_host/hid_demo/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_host/hid_demo/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_host/hid_demo/inc/usb_conf.h b/project/at_start_f437/examples/usb_host/hid_demo/inc/usb_conf.h index 7ccde049..24198aee 100644 --- a/project/at_start_f437/examples/usb_host/hid_demo/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_host/hid_demo/inc/usb_conf.h @@ -120,7 +120,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvoptx b/project/at_start_f437/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvoptx index 08192035..a6f6e1c9 100644 --- a/project/at_start_f437/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvoptx +++ b/project/at_start_f437/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvprojx b/project/at_start_f437/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvprojx index abfe944c..27adac5a 100644 --- a/project/at_start_f437/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvprojx +++ b/project/at_start_f437/examples/usb_host/hid_demo/mdk_v5/hid_demo.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -639,4 +639,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_host/hid_demo/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_host/hid_demo/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_host/hid_demo/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_host/hid_demo/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_host/hid_demo/src/main.c b/project/at_start_f437/examples/usb_host/hid_demo/src/main.c index 53cedd70..29d1cf03 100644 --- a/project/at_start_f437/examples/usb_host/hid_demo/src/main.c +++ b/project/at_start_f437/examples/usb_host/hid_demo/src/main.c @@ -250,7 +250,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_host/msc_only_fat32/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_host/msc_only_fat32/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_host/msc_only_fat32/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_host/msc_only_fat32/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_host/msc_only_fat32/inc/usb_conf.h b/project/at_start_f437/examples/usb_host/msc_only_fat32/inc/usb_conf.h index c36e6d71..0a448a6d 100644 --- a/project/at_start_f437/examples/usb_host/msc_only_fat32/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_host/msc_only_fat32/inc/usb_conf.h @@ -119,7 +119,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvoptx b/project/at_start_f437/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvoptx index ca3f1e0f..0fb8fcab 100644 --- a/project/at_start_f437/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvoptx +++ b/project/at_start_f437/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvprojx b/project/at_start_f437/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvprojx index 42ce76e9..f6f9e400 100644 --- a/project/at_start_f437/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvprojx +++ b/project/at_start_f437/examples/usb_host/msc_only_fat32/mdk_v5/msc_only_fat32.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -649,4 +649,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_host/msc_only_fat32/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_host/msc_only_fat32/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_host/msc_only_fat32/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_host/msc_only_fat32/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_host/msc_only_fat32/src/main.c b/project/at_start_f437/examples/usb_host/msc_only_fat32/src/main.c index a4d613b0..e55b1431 100644 --- a/project/at_start_f437/examples/usb_host/msc_only_fat32/src/main.c +++ b/project/at_start_f437/examples/usb_host/msc_only_fat32/src/main.c @@ -204,7 +204,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/usb_host/two_otg_host_demo/inc/at32f435_437_conf.h b/project/at_start_f437/examples/usb_host/two_otg_host_demo/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/usb_host/two_otg_host_demo/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/usb_host/two_otg_host_demo/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/usb_host/two_otg_host_demo/inc/usb_conf.h b/project/at_start_f437/examples/usb_host/two_otg_host_demo/inc/usb_conf.h index df756378..7ac69e0a 100644 --- a/project/at_start_f437/examples/usb_host/two_otg_host_demo/inc/usb_conf.h +++ b/project/at_start_f437/examples/usb_host/two_otg_host_demo/inc/usb_conf.h @@ -112,7 +112,7 @@ extern "C" { #define OTG2_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG2_PIN_ID GPIO_PINS_12 -#define OTG2_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG2_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG2_PIN_SOF_GPIO GPIOA #define OTG2_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/project/at_start_f437/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvoptx b/project/at_start_f437/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvoptx index 798faad0..7376092b 100644 --- a/project/at_start_f437/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvoptx +++ b/project/at_start_f437/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvprojx b/project/at_start_f437/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvprojx index 213bfec3..5746cf9f 100644 --- a/project/at_start_f437/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvprojx +++ b/project/at_start_f437/examples/usb_host/two_otg_host_demo/mdk_v5/two_otg_host_demo.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -664,4 +664,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/usb_host/two_otg_host_demo/src/at32f435_437_clock.c b/project/at_start_f437/examples/usb_host/two_otg_host_demo/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/usb_host/two_otg_host_demo/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/usb_host/two_otg_host_demo/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/usb_host/two_otg_host_demo/src/main.c b/project/at_start_f437/examples/usb_host/two_otg_host_demo/src/main.c index 4f07f9b1..88d0471e 100644 --- a/project/at_start_f437/examples/usb_host/two_otg_host_demo/src/main.c +++ b/project/at_start_f437/examples/usb_host/two_otg_host_demo/src/main.c @@ -215,7 +215,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/project/at_start_f437/examples/wdt/wdt_reset/inc/at32f435_437_conf.h b/project/at_start_f437/examples/wdt/wdt_reset/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/wdt/wdt_reset/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/wdt/wdt_reset/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvoptx b/project/at_start_f437/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvoptx index 2859827e..4d2dc3f2 100644 --- a/project/at_start_f437/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvoptx +++ b/project/at_start_f437/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvprojx b/project/at_start_f437/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvprojx index 6d21a419..ef7fd933 100644 --- a/project/at_start_f437/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvprojx +++ b/project/at_start_f437/examples/wdt/wdt_reset/mdk_v5/wdt_reset.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/wdt/wdt_reset/src/at32f435_437_clock.c b/project/at_start_f437/examples/wdt/wdt_reset/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/wdt/wdt_reset/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/wdt/wdt_reset/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/wdt/wdt_standby/inc/at32f435_437_conf.h b/project/at_start_f437/examples/wdt/wdt_standby/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/wdt/wdt_standby/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/wdt/wdt_standby/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvoptx b/project/at_start_f437/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvoptx index 9521e82c..658ae658 100644 --- a/project/at_start_f437/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvoptx +++ b/project/at_start_f437/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvprojx b/project/at_start_f437/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvprojx index b5f84846..b3cba512 100644 --- a/project/at_start_f437/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvprojx +++ b/project/at_start_f437/examples/wdt/wdt_standby/mdk_v5/wdt_standby.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/wdt/wdt_standby/src/at32f435_437_clock.c b/project/at_start_f437/examples/wdt/wdt_standby/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/wdt/wdt_standby/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/wdt/wdt_standby/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/wwdt/wwdt_reset/inc/at32f435_437_conf.h b/project/at_start_f437/examples/wwdt/wwdt_reset/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/wwdt/wwdt_reset/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/wwdt/wwdt_reset/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvoptx b/project/at_start_f437/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvoptx index b20489a7..0b7c4846 100644 --- a/project/at_start_f437/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvoptx +++ b/project/at_start_f437/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvprojx b/project/at_start_f437/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvprojx index e0d34c7d..3a87f01c 100644 --- a/project/at_start_f437/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvprojx +++ b/project/at_start_f437/examples/wwdt/wwdt_reset/mdk_v5/wwdt_rest.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/wwdt/wwdt_reset/src/at32f435_437_clock.c b/project/at_start_f437/examples/wwdt/wwdt_reset/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/wwdt/wwdt_reset/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/wwdt/wwdt_reset/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/xmc/lcd_8bit/inc/at32f435_437_conf.h b/project/at_start_f437/examples/xmc/lcd_8bit/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/xmc/lcd_8bit/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/xmc/lcd_8bit/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvoptx b/project/at_start_f437/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvoptx index c0b1b28d..4758c26f 100644 --- a/project/at_start_f437/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvoptx +++ b/project/at_start_f437/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvprojx b/project/at_start_f437/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvprojx index 3de73ff6..d837c7e7 100644 --- a/project/at_start_f437/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvprojx +++ b/project/at_start_f437/examples/xmc/lcd_8bit/mdk_v5/lcd_8bit.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/xmc/lcd_8bit/src/at32f435_437_clock.c b/project/at_start_f437/examples/xmc/lcd_8bit/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/xmc/lcd_8bit/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/xmc/lcd_8bit/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/xmc/lcd_touch_16bit/inc/at32f435_437_conf.h b/project/at_start_f437/examples/xmc/lcd_touch_16bit/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/xmc/lcd_touch_16bit/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/xmc/lcd_touch_16bit/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvoptx b/project/at_start_f437/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvoptx index cd55ee71..6dc1d752 100644 --- a/project/at_start_f437/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvoptx +++ b/project/at_start_f437/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvprojx b/project/at_start_f437/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvprojx index bc574aee..8d0ad956 100644 --- a/project/at_start_f437/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvprojx +++ b/project/at_start_f437/examples/xmc/lcd_touch_16bit/mdk_v5/lcd_touch_16bit.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -493,6 +493,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/xmc/lcd_touch_16bit/src/at32f435_437_clock.c b/project/at_start_f437/examples/xmc/lcd_touch_16bit/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/xmc/lcd_touch_16bit/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/xmc/lcd_touch_16bit/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/xmc/nand_flash/ecc/inc/at32f435_437_conf.h b/project/at_start_f437/examples/xmc/nand_flash/ecc/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/xmc/nand_flash/ecc/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/xmc/nand_flash/ecc/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvoptx b/project/at_start_f437/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvoptx index 94151ec4..c880fdeb 100644 --- a/project/at_start_f437/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvoptx +++ b/project/at_start_f437/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvprojx b/project/at_start_f437/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvprojx index 08f74684..c448c0e7 100644 --- a/project/at_start_f437/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvprojx +++ b/project/at_start_f437/examples/xmc/nand_flash/ecc/mdk_v5/ecc.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -948,6 +948,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/xmc/nand_flash/ecc/src/at32f435_437_clock.c b/project/at_start_f437/examples/xmc/nand_flash/ecc/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/xmc/nand_flash/ecc/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/xmc/nand_flash/ecc/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/xmc/nand_flash/nand/inc/at32f435_437_conf.h b/project/at_start_f437/examples/xmc/nand_flash/nand/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/xmc/nand_flash/nand/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/xmc/nand_flash/nand/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/xmc/nand_flash/nand/mdk_v5/nand.uvoptx b/project/at_start_f437/examples/xmc/nand_flash/nand/mdk_v5/nand.uvoptx index b478fab8..85acb2fc 100644 --- a/project/at_start_f437/examples/xmc/nand_flash/nand/mdk_v5/nand.uvoptx +++ b/project/at_start_f437/examples/xmc/nand_flash/nand/mdk_v5/nand.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/xmc/nand_flash/nand/mdk_v5/nand.uvprojx b/project/at_start_f437/examples/xmc/nand_flash/nand/mdk_v5/nand.uvprojx index abac3410..ae11ffb1 100644 --- a/project/at_start_f437/examples/xmc/nand_flash/nand/mdk_v5/nand.uvprojx +++ b/project/at_start_f437/examples/xmc/nand_flash/nand/mdk_v5/nand.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -948,6 +948,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/xmc/nand_flash/nand/src/at32f435_437_clock.c b/project/at_start_f437/examples/xmc/nand_flash/nand/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/xmc/nand_flash/nand/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/xmc/nand_flash/nand/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/xmc/nor_flash/inc/at32f435_437_conf.h b/project/at_start_f437/examples/xmc/nor_flash/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/xmc/nor_flash/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/xmc/nor_flash/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/xmc/nor_flash/mdk_v5/nor_flash.uvoptx b/project/at_start_f437/examples/xmc/nor_flash/mdk_v5/nor_flash.uvoptx index 12ede9c4..47e076de 100644 --- a/project/at_start_f437/examples/xmc/nor_flash/mdk_v5/nor_flash.uvoptx +++ b/project/at_start_f437/examples/xmc/nor_flash/mdk_v5/nor_flash.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/xmc/nor_flash/mdk_v5/nor_flash.uvprojx b/project/at_start_f437/examples/xmc/nor_flash/mdk_v5/nor_flash.uvprojx index 8011d387..66425b87 100644 --- a/project/at_start_f437/examples/xmc/nor_flash/mdk_v5/nor_flash.uvprojx +++ b/project/at_start_f437/examples/xmc/nor_flash/mdk_v5/nor_flash.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/xmc/nor_flash/src/at32f435_437_clock.c b/project/at_start_f437/examples/xmc/nor_flash/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/xmc/nor_flash/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/xmc/nor_flash/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/xmc/pc_card/inc/at32f435_437_clock.h b/project/at_start_f437/examples/xmc/pc_card/inc/at32f435_437_clock.h new file mode 100644 index 00000000..9a636f09 --- /dev/null +++ b/project/at_start_f437/examples/xmc/pc_card/inc/at32f435_437_clock.h @@ -0,0 +1,44 @@ +/** + ************************************************************************** + * @file at32f435_437_clock.h + * @brief header file of clock program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AT32F435_437_CLOCK_H +#define __AT32F435_437_CLOCK_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437.h" + +/* exported functions ------------------------------------------------------- */ +void system_clock_config(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/project/at_start_f437/examples/xmc/pc_card/inc/at32f435_437_conf.h b/project/at_start_f437/examples/xmc/pc_card/inc/at32f435_437_conf.h new file mode 100644 index 00000000..12638db0 --- /dev/null +++ b/project/at_start_f437/examples/xmc/pc_card/inc/at32f435_437_conf.h @@ -0,0 +1,173 @@ +/** + ************************************************************************** + * @file at32f435_437_conf.h + * @brief at32f435_437 config header file + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AT32F435_437_CONF_H +#define __AT32F435_437_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief in the following line adjust the value of high speed exernal crystal (hext) + * used in your application + * + * tip: to avoid modifying this file each time you need to use different hext, you + * can define the hext value in your toolchain compiler preprocessor. + * + */ +#if !defined HEXT_VALUE +#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed exernal crystal in hz */ +#endif + +/** + * @brief in the following line adjust the high speed exernal crystal (hext) startup + * timeout value + */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ + +/* module define -------------------------------------------------------------*/ +#define CRM_MODULE_ENABLED +#define TMR_MODULE_ENABLED +#define ERTC_MODULE_ENABLED +#define GPIO_MODULE_ENABLED +#define I2C_MODULE_ENABLED +#define USART_MODULE_ENABLED +#define PWC_MODULE_ENABLED +#define CAN_MODULE_ENABLED +#define ADC_MODULE_ENABLED +#define DAC_MODULE_ENABLED +#define SPI_MODULE_ENABLED +#define EDMA_MODULE_ENABLED +#define DMA_MODULE_ENABLED +#define DEBUG_MODULE_ENABLED +#define FLASH_MODULE_ENABLED +#define CRC_MODULE_ENABLED +#define WWDT_MODULE_ENABLED +#define WDT_MODULE_ENABLED +#define EXINT_MODULE_ENABLED +#define SDIO_MODULE_ENABLED +#define XMC_MODULE_ENABLED +#define USB_MODULE_ENABLED +#define ACC_MODULE_ENABLED +#define MISC_MODULE_ENABLED +#define QSPI_MODULE_ENABLED +#define DVP_MODULE_ENABLED +#define SCFG_MODULE_ENABLED +#define EMAC_MODULE_ENABLED + +/* includes ------------------------------------------------------------------*/ +#ifdef CRM_MODULE_ENABLED +#include "at32f435_437_crm.h" +#endif +#ifdef TMR_MODULE_ENABLED +#include "at32f435_437_tmr.h" +#endif +#ifdef ERTC_MODULE_ENABLED +#include "at32f435_437_ertc.h" +#endif +#ifdef GPIO_MODULE_ENABLED +#include "at32f435_437_gpio.h" +#endif +#ifdef I2C_MODULE_ENABLED +#include "at32f435_437_i2c.h" +#endif +#ifdef USART_MODULE_ENABLED +#include "at32f435_437_usart.h" +#endif +#ifdef PWC_MODULE_ENABLED +#include "at32f435_437_pwc.h" +#endif +#ifdef CAN_MODULE_ENABLED +#include "at32f435_437_can.h" +#endif +#ifdef ADC_MODULE_ENABLED +#include "at32f435_437_adc.h" +#endif +#ifdef DAC_MODULE_ENABLED +#include "at32f435_437_dac.h" +#endif +#ifdef SPI_MODULE_ENABLED +#include "at32f435_437_spi.h" +#endif +#ifdef DMA_MODULE_ENABLED +#include "at32f435_437_dma.h" +#endif +#ifdef DEBUG_MODULE_ENABLED +#include "at32f435_437_debug.h" +#endif +#ifdef FLASH_MODULE_ENABLED +#include "at32f435_437_flash.h" +#endif +#ifdef CRC_MODULE_ENABLED +#include "at32f435_437_crc.h" +#endif +#ifdef WWDT_MODULE_ENABLED +#include "at32f435_437_wwdt.h" +#endif +#ifdef WDT_MODULE_ENABLED +#include "at32f435_437_wdt.h" +#endif +#ifdef EXINT_MODULE_ENABLED +#include "at32f435_437_exint.h" +#endif +#ifdef SDIO_MODULE_ENABLED +#include "at32f435_437_sdio.h" +#endif +#ifdef XMC_MODULE_ENABLED +#include "at32f435_437_xmc.h" +#endif +#ifdef ACC_MODULE_ENABLED +#include "at32f435_437_acc.h" +#endif +#ifdef MISC_MODULE_ENABLED +#include "at32f435_437_misc.h" +#endif +#ifdef EDMA_MODULE_ENABLED +#include "at32f435_437_edma.h" +#endif +#ifdef QSPI_MODULE_ENABLED +#include "at32f435_437_qspi.h" +#endif +#ifdef SCFG_MODULE_ENABLED +#include "at32f435_437_scfg.h" +#endif +#ifdef EMAC_MODULE_ENABLED +#include "at32f435_437_emac.h" +#endif +#ifdef DVP_MODULE_ENABLED +#include "at32f435_437_dvp.h" +#endif +#ifdef USB_MODULE_ENABLED +#include "at32f435_437_usb.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/project/at_start_f437/examples/xmc/pc_card/inc/at32f435_437_int.h b/project/at_start_f437/examples/xmc/pc_card/inc/at32f435_437_int.h new file mode 100644 index 00000000..bc319dcd --- /dev/null +++ b/project/at_start_f437/examples/xmc/pc_card/inc/at32f435_437_int.h @@ -0,0 +1,56 @@ +/** + ************************************************************************** + * @file at32f435_437_int.h + * @brief header file of main interrupt service routines. + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AT32F435_437_INT_H +#define __AT32F435_437_INT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437.h" + +/* exported types ------------------------------------------------------------*/ +/* exported constants --------------------------------------------------------*/ +/* exported macro ------------------------------------------------------------*/ +/* exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/project/at_start_f437/examples/xmc/pc_card/mdk_v5/pc_card.uvoptx b/project/at_start_f437/examples/xmc/pc_card/mdk_v5/pc_card.uvoptx new file mode 100644 index 00000000..36f674da --- /dev/null +++ b/project/at_start_f437/examples/xmc/pc_card/mdk_v5/pc_card.uvoptx @@ -0,0 +1,380 @@ + + + + 1.0 + +

                                      ### uVision Project, (C) Keil Software
                                      + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + pc_card + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0AT32F437_4032 -FS08000000 -FL03F0000 -FP0($$Device:-AT32F437ZMT7$Flash\AT32F437_4032.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + user + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\src\at32f435_437_clock.c + at32f435_437_clock.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\src\at32f435_437_int.c + at32f435_437_int.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\src\main.c + main.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\PC_card\cf.c + cf.c + 0 + 0 + + + + + bsp + 0 + 0 + 0 + 0 + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\at32f435_437_board\at32f435_437_board.c + at32f435_437_board.c + 0 + 0 + + + + + firmware + 0 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_crm.c + at32f435_437_crm.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_gpio.c + at32f435_437_gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_misc.c + at32f435_437_misc.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_xmc.c + at32f435_437_xmc.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_usart.c + at32f435_437_usart.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_edma.c + at32f435_437_edma.c + 0 + 0 + + + + + cmsis + 0 + 0 + 0 + 0 + + 4 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\system_at32f435_437.c + system_at32f435_437.c + 0 + 0 + + + 4 + 13 + 2 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\startup\mdk\startup_at32f435_437.s + startup_at32f435_437.s + 0 + 0 + + + + + readme + 0 + 0 + 0 + 0 + + 5 + 14 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + diff --git a/project/at_start_f437/examples/xmc/pc_card/mdk_v5/pc_card.uvprojx b/project/at_start_f437/examples/xmc/pc_card/mdk_v5/pc_card.uvprojx new file mode 100644 index 00000000..07888095 --- /dev/null +++ b/project/at_start_f437/examples/xmc/pc_card/mdk_v5/pc_card.uvprojx @@ -0,0 +1,502 @@ + + + + 2.1 + +
                                      ### uVision Project, (C) Keil Software
                                      + + + + pc_card + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + -AT32F437ZMT7 + ArteryTek + ArteryTek.AT32F435_437_DFP.2.0.1 + IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0AT32F437_4032 -FS08000000 -FL03F0000 -FP0($$Device:-AT32F437ZMT7$Flash\AT32F437_4032.FLM)) + 0 + $$Device:- + + + + + + + + + + $$Device:-AT32F437ZMT7$SVD\AT32F437xx_v2.svd + 0 + 0 + + + + AT32F437ZMT7$Device\Include\at32f435_437.h\ + AT32F437ZMT7$Device\Include\at32f435_437.h\ + + 0 + 0 + 0 + 0 + 1 + + .\objects\ + pc_card + 1 + 0 + 1 + 1 + 1 + .\listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x8000000 + 0x3f0000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x3f0000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + AT32F437ZMT7,USE_STDPERIPH_DRIVER,AT_START_F437_V1 + + ..\..\..\..\..\..\libraries\drivers\inc;..\..\..\..\..\..\libraries\cmsis\cm4\core_support;..\..\..\..\..\..\libraries\cmsis\cm4\device_support;..\inc;..\..\..\..\..\at32f435_437_board;..\pc_card + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + user + + + at32f435_437_clock.c + 1 + ..\src\at32f435_437_clock.c + + + at32f435_437_int.c + 1 + ..\src\at32f435_437_int.c + + + main.c + 1 + ..\src\main.c + + + cf.c + 1 + ..\PC_card\cf.c + + + + + bsp + + + at32f435_437_board.c + 1 + ..\..\..\..\..\at32f435_437_board\at32f435_437_board.c + + + + + firmware + + + at32f435_437_crm.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_crm.c + + + at32f435_437_gpio.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_gpio.c + + + at32f435_437_misc.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_misc.c + + + at32f435_437_xmc.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_xmc.c + + + at32f435_437_usart.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_usart.c + + + at32f435_437_edma.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_edma.c + + + + + cmsis + + + system_at32f435_437.c + 1 + ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\system_at32f435_437.c + + + startup_at32f435_437.s + 2 + ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\startup\mdk\startup_at32f435_437.s + + + + + readme + + + readme.txt + 5 + ..\readme.txt + + + + + + + + + + + + + + + + + sram + + + + + + 0 + 1 + + + + +                                       diff --git a/project/at_start_f437/examples/xmc/pc_card/pc_card/cf.c b/project/at_start_f437/examples/xmc/pc_card/pc_card/cf.c new file mode 100644 index 00000000..a64730e8 --- /dev/null +++ b/project/at_start_f437/examples/xmc/pc_card/pc_card/cf.c @@ -0,0 +1,2592 @@ +/** + ************************************************************************** + * @file cf.c + * @brief xmc pc card program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "cf.h" +#include "at32f435_437.h" +#include "at32f435_437_board.h" +#include +#include +#include + +/** @addtogroup AT32F437_periph_examples + * @{ + */ + +/** @addtogroup XMC_CF_CARD + * @{ + */ + +edma_init_type EDMA_InitStructure; +u16 DMA1_MEM_LEN; +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PCCARD_Private_Constants PCCARD Private Constants + * @{ + */ + +#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFF +#define PCCARD_TIMEOUT_SECTOR (uint32_t)0x0000FFFF +#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000 + +#define PCCARD_STATUS_OK (uint8_t)0x58 +#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions + * @{ + */ + +/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### PCCARD Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize + the PCCARD memory + +@endverbatim + * @{ + */ + /** + * @brief DMA configuration + * @param EDMA_CHx: pointer to a EDMA_Channel_Type structure + * @param cpar_src: the Memory 1 addr + * @param cmar_dst: the Memory 2 addr + * @param cndtr: transfer size + * @param Transfer_Type: + * @arg Read_Transfer: from Memory 1 to Memory 2 + * @arg Write_Transfer: from Memory 2 to Memory 1 + * @param Transfer_Width: BYTE or HALFWORD + * @retval None + */ +void MYDMA_Config(edma_stream_type* DMAy_Streamx, uint32_t cpar_src, uint32_t cmar_dst, uint32_t cndtr, uint8_t Transfer_Type, uint8_t Transfer_Width) +{ + edma_init_type EDMA_InitStruct; + crm_periph_clock_enable(CRM_EDMA_PERIPH_CLOCK, TRUE); + + edma_reset(DMAy_Streamx); + + if(Transfer_Type == Read_Transfer) + { + EDMA_InitStruct.peripheral_inc_enable = FALSE; + EDMA_InitStruct.memory_inc_enable = TRUE; + } + else + { + EDMA_InitStruct.peripheral_inc_enable = TRUE; + EDMA_InitStruct.memory_inc_enable = FALSE; + } + + if(Transfer_Width == Enable_8_bit_Transfer) + { + EDMA_InitStruct.peripheral_data_width = EDMA_PERIPHERAL_DATA_WIDTH_BYTE; + EDMA_InitStruct.memory_data_width = EDMA_MEMORY_DATA_WIDTH_BYTE; + } + else + { + EDMA_InitStruct.peripheral_data_width = EDMA_PERIPHERAL_DATA_WIDTH_HALFWORD; + EDMA_InitStruct.memory_data_width = EDMA_MEMORY_DATA_WIDTH_HALFWORD; + } + + EDMA_InitStruct.direction = EDMA_DIR_MEMORY_TO_MEMORY; + EDMA_InitStruct.buffer_size = cndtr; + EDMA_InitStruct.peripheral_base_addr = cpar_src; + + EDMA_InitStruct.peripheral_burst_mode = EDMA_PERIPHERAL_SINGLE; + EDMA_InitStruct.memory0_base_addr = cmar_dst; + + EDMA_InitStruct.memory_burst_mode = EDMA_MEMORY_SINGLE; + EDMA_InitStruct.loop_mode_enable = FALSE; + EDMA_InitStruct.fifo_mode_enable = TRUE; + EDMA_InitStruct.fifo_threshold = EDMA_FIFO_THRESHOLD_FULL; + EDMA_InitStruct.priority = EDMA_PRIORITY_MEDIUM; + edma_init(DMAy_Streamx,&EDMA_InitStruct); + + + edma_stream_enable(DMAy_Streamx, TRUE); +} +/** + * @brief XMC InitCtrl + * @param Device: pointer to a XMC_Bank4_Type structure + * @param Init: pointer to a XMC_PCCARDInitType structure + * @param Set_reg_8_bit: choose 8/16bit + * @retval STATUS_OK or STATUS_ERROR + */ +StatusType XMC_PCCARD_InitCtrl(xmc_bank4_type *Device, xmc_pccard_init_type *Init, uint8_t Set_reg_8_bit) +{ + if(Set_reg_8_bit == 1) + { + Device->bk4ctrl_bit.extmdbw = XMC_MEM_WIDTH_8; + } + else + { + Device->bk4ctrl_bit.extmdbw = XMC_MEM_WIDTH_16; + } + + Device->bk4ctrl_bit.tar = Init->delay_time_ar; + Device->bk4ctrl_bit.tcr = Init->delay_time_cr; + + return STATUS_OK; + +} +/** + * @brief XMC Enable Wait Feature + * @param Device: pointer to a XMC_Bank4_Type structure + * @param Init: pointer to a XMC_PCCARDInitType structure + * @retval STATUS_OK or STATUS_ERROR + */ +StatusType XMC_Enable_Wait_Feature(xmc_bank4_type *Device, xmc_pccard_init_type *Init) +{ + + Device->bk4ctrl_bit.nwen = Init->enable_wait; + + return STATUS_OK; +} +/** + * @brief Set 16bit_Feature + * @param Device: pointer to a XMC_Bank4_Type structure + * @param Init: pointer to a XMC_PCCARDInitType structure + * @param Set_reg_8_bit: choose 8/16bit + * @retval HAL status + */ +StatusType XMC_Enable_16bit_Feature(xmc_bank4_type *Device, xmc_pccard_init_type *Init, uint8_t Set_reg_8_bit) +{ + if(Set_reg_8_bit == 1) + { + Device->bk4ctrl_bit.extmdbw = XMC_MEM_WIDTH_8; + } + else + { + Device->bk4ctrl_bit.extmdbw = XMC_MEM_WIDTH_16; + } + + return STATUS_OK; +} +/** + * @brief Init CommonSpace Timing + * @param Device: pointer to a XMC_Bank4_Type structure + * @param Timing: pointer to a Common space timing structure + * @retval HAL status + */ +StatusType XMC_PCCARD_InitCommonSpaceTiming(xmc_bank4_type *Device, xmc_nand_pccard_timinginit_type *Timing) +{ + Device->bk4tmgmem_bit.cmdhizt = Timing->mem_hiz_time; + Device->bk4tmgmem_bit.cmht = Timing->mem_hold_time; + Device->bk4tmgmem_bit.cmst = Timing->mem_setup_time; + Device->bk4tmgmem_bit.cmwt = Timing->mem_waite_time; + + return STATUS_OK; +} +/** + * @brief Init AttributeSpace Timing + * @param Device: pointer to a XMC_Bank4_Type structure + * @param Timing: pointer to a Attribute space timing structure + * @retval HAL status + */ +StatusType XMC_PCCARD_InitAttributeSpaceTiming(xmc_bank4_type *Device, xmc_nand_pccard_timinginit_type *Timing) +{ + Device->bk4tmgatt_bit.amdhizt = Timing->mem_hiz_time; + Device->bk4tmgatt_bit.amht = Timing->mem_hold_time; + Device->bk4tmgatt_bit.amst = Timing->mem_setup_time; + Device->bk4tmgatt_bit.amwt = Timing->mem_waite_time; + return STATUS_OK; +} +/*****************************************************************/ +/** + * @brief Init IOSpace Timing + * @param Device: pointer to a XMC_Bank4_Type structure + * @param Timing: pointer to a IO space timing structure + * @retval HAL status + */ +StatusType XMC_PCCARD_InitIOSpaceTiming(xmc_bank4_type *Device, xmc_nand_pccard_timinginit_type *Timing) +{ + + Device->bk4tmgio_bit.iohizt = Timing->mem_hiz_time; + Device->bk4tmgio_bit.ioht = Timing->mem_hold_time; + Device->bk4tmgio_bit.iost = Timing->mem_setup_time; + Device->bk4tmgio_bit.iowt = Timing->mem_waite_time; + + return STATUS_OK; +} +/*****************************************************************/ +/** + * @brief Perform the PCCARD memory Initialization sequence + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param ComSpaceTiming: Common space timing structure + * @param AttSpaceTiming: Attribute space timing structure + * @param IOSpaceTiming: IO space timing structure + * @retval HAL status + */ +StatusType PCCARD_Init(PCCARD_HandleType *hpccard, xmc_nand_pccard_timinginit_type *ComSpaceTiming, xmc_nand_pccard_timinginit_type *AttSpaceTiming, xmc_nand_pccard_timinginit_type *IOSpaceTiming) +{ + gpio_init_type GPIO_InitStructure; + uint8_t Set_reg_8_bit; + + /* Check the PCCARD controller state */ + if(hpccard == NULL) + { + return STATUS_ERROR; + } + + if(hpccard->CF.Enable_8_bit_mode == TRUE) + Set_reg_8_bit = 1; + else + Set_reg_8_bit = 0; + + + if(hpccard->State == PCCARD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpccard->Lock = UNLOCKED; + + } + + /* Initialize the PCCARD state */ + hpccard->State = PCCARD_STATE_BUSY; + + + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK,TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK,TRUE); + crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK,TRUE); + crm_periph_clock_enable(CRM_GPIOE_PERIPH_CLOCK,TRUE); + crm_periph_clock_enable(CRM_GPIOF_PERIPH_CLOCK,TRUE); + crm_periph_clock_enable(CRM_GPIOG_PERIPH_CLOCK,TRUE); + /* address line:PF0 PF1 PF2 PF3 PF4 PF5 PF12 PF13 PF14 PF15 PD5 PG1 PG2 PG3 PG4 PG5 PD11 PD12 PD13 PE3 PE4 PE5 PE6 PE2 PG13 PG14 */ + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE0, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE1, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE2, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE3, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE4, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE5, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE12, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE13, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE14, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE15, GPIO_MUX_12); + + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_0|GPIO_PINS_1|GPIO_PINS_2|GPIO_PINS_3|GPIO_PINS_4|GPIO_PINS_5|GPIO_PINS_12|GPIO_PINS_13|GPIO_PINS_14|GPIO_PINS_15; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOF, &GPIO_InitStructure); + + gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE5, GPIO_MUX_10); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_11|GPIO_PINS_12|GPIO_PINS_13|GPIO_PINS_5; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOD, &GPIO_InitStructure); + + /* data line: PB14 PC6 PC11 PC12 PE7 PA3 PA4 PA5 PE11 PE12 PE13 PE14 PE15 PB12 PD9 PD10 */ + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE14, GPIO_MUX_14); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE12, GPIO_MUX_14); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_14|GPIO_PINS_12; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOB, &GPIO_InitStructure); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE6, GPIO_MUX_14); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE11, GPIO_MUX_14); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE12, GPIO_MUX_14); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_6|GPIO_PINS_11|GPIO_PINS_12; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOC, &GPIO_InitStructure); + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE3, GPIO_MUX_14); + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE4, GPIO_MUX_14); + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE5, GPIO_MUX_14); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_2|GPIO_PINS_3|GPIO_PINS_4|GPIO_PINS_5; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOA, &GPIO_InitStructure); + gpio_pin_mux_config(GPIOE, GPIO_PINS_SOURCE7, GPIO_MUX_12); + gpio_pin_mux_config(GPIOE, GPIO_PINS_SOURCE11, GPIO_MUX_12); + gpio_pin_mux_config(GPIOE, GPIO_PINS_SOURCE12, GPIO_MUX_12); + gpio_pin_mux_config(GPIOE, GPIO_PINS_SOURCE13, GPIO_MUX_12); + gpio_pin_mux_config(GPIOE, GPIO_PINS_SOURCE14, GPIO_MUX_12); + gpio_pin_mux_config(GPIOE, GPIO_PINS_SOURCE15, GPIO_MUX_12); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_11|GPIO_PINS_12|GPIO_PINS_13|GPIO_PINS_14|GPIO_PINS_15|GPIO_PINS_7; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOE, &GPIO_InitStructure); + gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE9, GPIO_MUX_12); + gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE10, GPIO_MUX_12); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_9|GPIO_PINS_10; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOD, &GPIO_InitStructure); + /* XMC_NCE4_1/XMC_NCE4_2:PG10/PG11 XMC_NOE:PD4 XMC_NWE:PC2 XMC_NBL0:PE0 XMC_NBL1:PE1 XMC_NADV:PB7 XMC_NWAIT:PD6 */ + /* XMC_NIORD:PF6 XMC_NIOWR:PF8 XMC_NREG:PF7 XMC_INTR:PF10 XMC_CD:PF9 */ + gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE4, GPIO_MUX_12); + gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE6, GPIO_MUX_12); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_4|GPIO_PINS_6; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_UP; + gpio_init(GPIOD, &GPIO_InitStructure); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE2, GPIO_MUX_14); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_2; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_UP; + gpio_init(GPIOC, &GPIO_InitStructure); + + gpio_pin_mux_config(GPIOG, GPIO_PINS_SOURCE10, GPIO_MUX_12); + gpio_pin_mux_config(GPIOG, GPIO_PINS_SOURCE11, GPIO_MUX_12); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_10|GPIO_PINS_11; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOG, &GPIO_InitStructure); + + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE9, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE6, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE7, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE8, GPIO_MUX_12); + gpio_pin_mux_config(GPIOF, GPIO_PINS_SOURCE10, GPIO_MUX_12); + gpio_default_para_init(&GPIO_InitStructure); + GPIO_InitStructure.gpio_pins = GPIO_PINS_9|GPIO_PINS_6|GPIO_PINS_7|GPIO_PINS_8|GPIO_PINS_10; + GPIO_InitStructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE; + GPIO_InitStructure.gpio_mode = GPIO_MODE_MUX; + GPIO_InitStructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + GPIO_InitStructure.gpio_pull = GPIO_PULL_NONE; + gpio_init(GPIOF, &GPIO_InitStructure); + + /* Initialize PCCARD control Interface */ + XMC_PCCARD_InitCtrl(hpccard->Instance, &(hpccard->Init), Set_reg_8_bit); + + /* Init PCCARD common space timing Interface */ + XMC_PCCARD_InitCommonSpaceTiming(hpccard->Instance, ComSpaceTiming); + + /* Init PCCARD attribute space timing Interface */ + XMC_PCCARD_InitAttributeSpaceTiming(hpccard->Instance, AttSpaceTiming); + + /* Init PCCARD IO space timing Interface */ + XMC_PCCARD_InitIOSpaceTiming(hpccard->Instance, IOSpaceTiming); + + /* Enable the PCCARD device */ + xmc_pccard_enable(TRUE); + + /* Update the PCCARD state */ + hpccard->State = PCCARD_STATE_READY; + + return STATUS_OK; + +} +/** + * @brief Enable Wait Feature + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval STATUS_OK or STATUS_ERROR + */ +StatusType Enable_Wait_Feature(PCCARD_HandleType *hpccard) +{ + /* Check the PCCARD controller state */ + if(hpccard == NULL) + { + return STATUS_ERROR; + } + + if(hpccard->State == PCCARD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpccard->Lock = UNLOCKED; + } + + /* Initialize the PCCARD state */ + hpccard->State = PCCARD_STATE_BUSY; + + XMC_Enable_Wait_Feature(hpccard->Instance, &(hpccard->Init)); + + hpccard->State = PCCARD_STATE_READY; + + return STATUS_OK; +} + +/** + * @brief Perform the PCCARD memory De-initialization sequence + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval HAL status + */ +StatusType PCCARD_DeInit(PCCARD_HandleType *hpccard) +{ + + /* Configure the PCCARD registers with their reset values */ + xmc_pccard_reset(); + + /* Update the PCCARD controller state */ + hpccard->State = PCCARD_STATE_RESET; + return STATUS_OK; +} + + +/** + * @} + */ + +/** @defgroup PCCARD_Exported_Functions_Group2 Input Output and memory functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### PCCARD Input Output and memory functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the PCCARD memory + +@endverbatim + * @{ + */ +/** + * @brief Identify + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Identify(PCCARD_HandleType *hpccard) +{ + uint8_t Reg; + + Reg = hpccard->CF.CFAddr.Drv; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + if(!CF_SendCommand(hpccard, ATA_IDENTIFY_DRIVE_CMD)) + { + return FALSE; + } + + return TRUE; +} + + +/** + * @brief Read Compact Flash's ID. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param CompactFlash_ID: Compact flash ID structure. + * @retval HAL status + * + */ +BOOL PCCARD_Read_ID(PCCARD_HandleType *hpccard) +{ + uint8_t CardInfo[PCCARD_SECTOR_SIZE * sizeof(uint8_t)] = {0}; + + memset(CardInfo, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + PCCARD_Read_STATUS_REG(hpccard); + + if(PCCARD_Identify(hpccard)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + /* Read CF ID bytes */ + + Read_Sector(hpccard, CardInfo, PCCARD_SECTOR_SIZE); + + break; + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + printf("\r\nCommand Pass, but ERR bit is high"); + printf("\r\nCF Status Reg=%#x", PCCARD_Read_STATUS_REG(hpccard)); + printf("\r\nCF Error Reg=%#x", PCCARD_Read_ERROR_REG(hpccard)); + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + printf("\r\nSend Command Failed"); + printf("\r\nCF Status Reg=%#x", PCCARD_Read_STATUS_REG(hpccard)); + printf("\r\nCF Error Reg=%#x", PCCARD_Read_ERROR_REG(hpccard)); + return FALSE; + } + } + } + +#if 1 + + printf("\r\n===============================================================\n"); + printf("\r\n\nIdentify Drive Information : "); + printf("\r\n%s%#x", "Signature : ", ((uint16_t)CardInfo[0] | (uint16_t)CardInfo[1] << 8)); + printf("\r\n%s%u", "Default number of cylinders : ", ((uint16_t)CardInfo[2] | (uint16_t)CardInfo[3] << 8)); + printf("\r\n%s%u", "Default number of heads : ", ((uint16_t)CardInfo[6] | (uint16_t)CardInfo[7] << 8)); + printf("\r\n%s%u", "Number of unformatted bytes per tract : ", ((uint16_t)CardInfo[8] | (uint16_t)CardInfo[9] << 8)); + printf("\r\n%s%u", "Number of unformatted bytes per sector : ", ((uint16_t)CardInfo[10] | (uint16_t)CardInfo[11] << 8)); + printf("\r\n%s%u", "Default number of sectors per track : ", ((uint16_t)CardInfo[12] | (uint16_t)CardInfo[13] << 8)); + printf("\r\n%s%u", "Number of sectors per card : ", (uint32_t)((uint16_t)CardInfo[16] | (uint16_t)CardInfo[17] << 8) | ((uint32_t)((uint16_t)CardInfo[14] | (uint16_t)CardInfo[15] << 8) << 16)); + printf("\r\n%s%u", "Vendor Unique : ", ((uint16_t)CardInfo[18] | (uint16_t)CardInfo[19] << 8)); + printf("\r\n%s%#x", "Buffer type : ", ((uint16_t)CardInfo[40] | (uint16_t)CardInfo[41] << 8)); + printf("\r\n%s%u", "Buffer size in 512 byte increments : ", ((uint16_t)CardInfo[42] | (uint16_t)CardInfo[43] << 8)); + printf("\r\n%s%u", "#of ECC bytes passed on Read/Write Long Commands : ", ((uint16_t)CardInfo[44] | (uint16_t)CardInfo[45] << 8)); + printf("\r\n%s%u", "Maximum number of sectors on Read/Write Multiple command : ", ((uint16_t)CardInfo[94] | (uint16_t)CardInfo[95] << 8)); + printf("\r\n%s%u", "Double Word not supported : ", ((uint16_t)CardInfo[96] | (uint16_t)CardInfo[97] << 8)); + printf("\r\n%s%u", "Capabilities : ", ((uint16_t)CardInfo[98] | (uint16_t)CardInfo[99] << 8)); + printf("\r\n%s%u", "PIO data transfer cycle timing mode : ", ((uint16_t)CardInfo[102] | (uint16_t)CardInfo[103] << 8)); + printf("\r\n%s%u", "DMA data transfer cycle timing mode: ", ((uint16_t)CardInfo[104] | (uint16_t)CardInfo[105] << 8)); + printf("\r\n%s%u", "Translation parameters are valid : ", ((uint16_t)CardInfo[106] | (uint16_t)CardInfo[107] << 8)); + printf("\r\n%s%u", "Current numbers of cylinders : ", ((uint16_t)CardInfo[108] | (uint16_t)CardInfo[109] << 8)); + printf("\r\n%s%u", "Current numbers of heads : ", ((uint16_t)CardInfo[110] | (uint16_t)CardInfo[111] << 8)); + printf("\r\n%s%u", "Current sectors per track : ", ((uint16_t)CardInfo[112] | (uint16_t)CardInfo[113] << 8)); + printf("\r\n%s%u", "Current capacity in sectors : ", (uint32_t)((uint16_t)CardInfo[116] | (uint16_t)CardInfo[117] << 8) | ((uint32_t)((uint16_t)CardInfo[114] | (uint16_t)CardInfo[115] << 8) << 16)); + printf("\r\n%s%#x", "Multiple sector setting : ", ((uint16_t)CardInfo[118] | (uint16_t)CardInfo[119] << 8)); + printf("\r\n%s%u", "Total number of sectors addressable in LBA Mode : ", (uint32_t)((uint16_t)CardInfo[120] | (uint16_t)CardInfo[121] << 8) | ((uint32_t)((uint16_t)CardInfo[122] | (uint16_t)CardInfo[123] << 8) << 16)); + printf("\r\n%s%#x", "Security status : ", ((uint16_t)CardInfo[256] | (uint16_t)CardInfo[257] << 8)); + printf("\r\n%s%#x", "Power requirement description : ", ((uint16_t)CardInfo[320] | (uint16_t)CardInfo[321] << 8)); + printf("\r\n==============================================================="); + +#endif + + /* signature of CF storage */ + if(((uint16_t)CardInfo[0] | (uint16_t)CardInfo[1] << 8) == 0x848A) + { + hpccard->CF.CFCardInfo.Default_Cylinder = ((uint16_t)CardInfo[2] | (uint16_t)CardInfo[3] << 8); + hpccard->CF.CFCardInfo.Default_Head = ((uint16_t)CardInfo[6] | (uint16_t)CardInfo[7] << 8); + hpccard->CF.CFCardInfo.Default_Sector = ((uint16_t)CardInfo[12] | (uint16_t)CardInfo[13] << 8); + hpccard->CF.CFCardInfo.Current_Cylinder = ((uint16_t)CardInfo[108] | (uint16_t)CardInfo[109] << 8); + hpccard->CF.CFCardInfo.Current_Head = ((uint16_t)CardInfo[110] | (uint16_t)CardInfo[111] << 8); + hpccard->CF.CFCardInfo.Current_Sector = ((uint16_t)CardInfo[112] | (uint16_t)CardInfo[113] << 8); + + hpccard->CF.CFCardInfo.Total_Sector = (uint32_t)((uint16_t)CardInfo[16] | (uint16_t)CardInfo[17] << 8) | ((uint32_t)((uint16_t)CardInfo[14] | (uint16_t)CardInfo[15] << 8) << 16); + hpccard->CF.CFCardInfo.Total_LBA_Sector = (uint32_t)((uint16_t)CardInfo[120] | (uint16_t)CardInfo[121] << 8) | ((uint32_t)((uint16_t)CardInfo[122] | (uint16_t)CardInfo[123] << 8) << 16); + hpccard->CF.CFCardInfo.Max_Mutiple_Sector = ((uint16_t)CardInfo[94] | (uint16_t)CardInfo[95] << 8); + hpccard->CF.CFCardInfo.Mutiple_Sector_Setting = ((uint16_t)CardInfo[118] | (uint16_t)CardInfo[119] << 8); + } + else + { + + return FALSE; + } + + return TRUE; +} + +/** + * @brief Read sector from PCCARD memory + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to destination read buffer + * @param Sector_Address: Sector address to read + * @retval HAL status + */ +BOOL PCCARD_Read_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = (uint8_t)hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_READ_SECTOR_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + pBuffer = Read_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + printf("Error Code=%X\n", PCCARD_Read_STATUS_REG(hpccard)); + return FALSE; + } + } + } + } + + return TRUE; +} + + +/** + * @brief Write sector to PCCARD memory + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to source write buffer + * @param Sector_Address: Sector address to write + * @retval HAL status + */ +BOOL PCCARD_Write_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + // Set the parameters to write a sector // + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + //*(__IO uint16_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = hpccard->CF.CFAddr.Cylinder; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = (uint8_t)hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_WRITE_SECTOR_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + pBuffer = Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if (PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + printf("Error Code=%X\n", PCCARD_Read_STATUS_REG(hpccard)); + return FALSE; + } + } + } + } + + return TRUE; +} + + +/** + * @brief Erase sector from PCCARD memory + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Address: Sector address to erase + * @retval HAL status + */ +BOOL PCCARD_Erase_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint8_t Reg; + uint16_t Count = 0; + + while (Count < Sector_Count) + { + + Translate_CHSAddr(hpccard, Sector_Address, 0, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_ERASE_SECTOR_CMD)) + { + Count += hpccard->CF.CFAddr.Sector_Count; + Sector_Address += hpccard->CF.CFAddr.Sector_Count; + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief Diagnostic + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Diagnostic(PCCARD_HandleType *hpccard) +{ + uint8_t ERROR_REG; + + /* Set the parameters */ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_EXECUTE_DRIVE_DIAG_CMD)) + { + return FALSE; + } + + ERROR_REG = PCCARD_Read_ERROR_REG(hpccard); + + if((ERROR_REG == 0x01) || (ERROR_REG == 0x02) || (ERROR_REG == 0x03) || (ERROR_REG == 0x04) || (ERROR_REG == 0x05) || (ERROR_REG == 0x80)) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Check Power Mode + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Check_Power_Mode(PCCARD_HandleType *hpccard) +{ + uint8_t SECTOR_COUNT_REG; + /* set sector_count register 0x80, after check_power_mode */ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = 0x80; + /* the register will be change to 0x00 or 0xFF */ + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_CHECK_POWER_MODE_CMD)) + { + return FALSE; + } + + SECTOR_COUNT_REG = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT); + + if(SECTOR_COUNT_REG == 0xFF || SECTOR_COUNT_REG == 0x00) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Set idle + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Idle(PCCARD_HandleType *hpccard, uint32_t Sector_Count) +{ + uint8_t SECTOR_COUNT_REG; + + hpccard->CF.CFAddr.Sector_Count = Sector_Count; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_IDLE_CMD)) + { + return FALSE; + } + + + /* Check Power Mode */ + if(!PCCARD_Check_Power_Mode(hpccard)) + { + printf("Compact Flash Check Power Mode Failed \n"); + return FALSE; + } + + SECTOR_COUNT_REG = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT); + + if(SECTOR_COUNT_REG == 0xFF) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Idle immediate + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Idle_Immediate(PCCARD_HandleType *hpccard) +{ + uint8_t SECTOR_COUNT_REG; + /* set sector_count register 0x80, after check_power_mode */ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = 0x80; + /* the register will be change to 0x00 or 0xFF */ + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_IDLE_IMMEDIATE_CMD)) + { + return FALSE; + } + + /* Check Power Mode */ + if(!PCCARD_Check_Power_Mode(hpccard)) + { + printf("Compact Flash Check Power Mode Failed \n"); + return FALSE; + } + + SECTOR_COUNT_REG = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT); + + if(SECTOR_COUNT_REG == 0xFF) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Set sleep mode + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Set_Sleep_Mode(PCCARD_HandleType *hpccard) +{ + uint8_t SECTOR_COUNT_REG; + /* set sector_count register 0x80, after check_power_mode */ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = 0x80; + /* the register will be change to 0x00 or 0xFF */ + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_SET_SLEEP_MODE_CMD)) + { + return FALSE; + } + + /* Check Power Mode */ + if(!PCCARD_Check_Power_Mode(hpccard)) + { + printf("Compact Flash Check Power Mode Failed \n"); + return FALSE; + } + + SECTOR_COUNT_REG = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT); + + if(SECTOR_COUNT_REG == 0x00) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Set Standby + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Standby(PCCARD_HandleType *hpccard) +{ + uint8_t SECTOR_COUNT_REG; + /* set sector_count register 0x80, after check_power_mode */ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = 0x80; + /* the register will be change to 0x00 or 0xFF */ + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_STANDBY_CMD)) + { + return FALSE; + } + + /* Check Power Mode */ + if(!PCCARD_Check_Power_Mode(hpccard)) + { + printf("Compact Flash Check Power Mode Failed \n"); + return FALSE; + } + + SECTOR_COUNT_REG = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT); + + if(SECTOR_COUNT_REG == 0x00) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Standby Immediate + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Standby_Immediate(PCCARD_HandleType *hpccard) +{ + uint8_t SECTOR_COUNT_REG; + /* set sector_count register 0x80, after check_power_mode */ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = 0x80; + /* the register will be change to 0x00 or 0xFF */ + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_STANDBY_IMMEDIATE_CMD)) + { + return FALSE; + } + + /* Check Power Mode */ + if(!PCCARD_Check_Power_Mode(hpccard)) + { + printf("Compact Flash Check Power Mode Failed \n"); + return FALSE; + } + + SECTOR_COUNT_REG = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT); + + if(SECTOR_COUNT_REG == 0x00) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Reuqest Sense the pccard + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Reuqest_Sense(PCCARD_HandleType *hpccard) +{ + uint8_t Reg, ERROR_REG; + + Reg = hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(!CF_SendCommand(hpccard, ATA_REQUEST_SENSE_CMD)) + { + return FALSE; + } + + ERROR_REG = PCCARD_Read_ERROR_REG(hpccard); + + if((ERROR_REG == 0x2F) || (ERROR_REG == 0x21)) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Recalibrate the pccard + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Recalibrate(PCCARD_HandleType *hpccard) +{ + uint8_t Reg, ERROR_REG; + + Reg = hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(!CF_SendCommand(hpccard, ATA_RECALIBRATE_CMD)) + { + return FALSE; + } + + ERROR_REG = PCCARD_Read_ERROR_REG(hpccard); + + if((0x00 == ERROR_REG)) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief Init drive para + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Count: the sector count + * @param Head_Count: the head count. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Init_Drive_Para(PCCARD_HandleType *hpccard, uint16_t Sector_Count, uint8_t Head_Count) +{ + uint8_t Reg; + + hpccard->CF.CFAddr.Head = (uint8_t)Head_Count; + hpccard->CF.CFAddr.Sector_Count = (uint8_t)Sector_Count; + + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(!CF_SendCommand(hpccard, ATA_INIT_DRIVE_PARA_CMD)) + { + return FALSE; + } + + return TRUE; +} +/** + * @brief seek pccard + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Head_Count: the head count. + * @param Cylinder_Count: the cylinder count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Seek(PCCARD_HandleType *hpccard, uint8_t Head_Count, uint16_t Cylinder_Count) +{ + uint8_t Reg, ERROR_REG; + + hpccard->CF.CFAddr.Head = (uint8_t)Head_Count; + hpccard->CF.CFAddr.Cylinder = (uint16_t)Cylinder_Count; + + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + + /* This command should return false */ + if(CF_SendCommand(hpccard, ATA_SEEK_CMD)) + { + return FALSE; + } + + ERROR_REG = PCCARD_Read_ERROR_REG(hpccard); + + if((ERROR_REG != 0x00)) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief format track + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Format_Track(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + /* Set the parameters to write a sector */ + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_FORMAT_TRACK_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + // Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if (PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief read Verify Sector + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Read_Verify_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint16_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_READ_VERIFY_SECTOR_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == DRQ_BIT) // DRQ_BIT should not be assert in this command + { + return FALSE; + } + else + { + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief write Verify + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Write_Verify(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + // Set the parameters to write a sector // + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_WRITE_VERIFY_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if (PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief set multiple mode + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Set_Multiple_Mode(PCCARD_HandleType *hpccard, uint32_t Sector_Count) +{ + hpccard->CF.CFAddr.Sector_Count = Sector_Count; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(!CF_SendCommand(hpccard, ATA_SET_MULTIPLE_MODE_CMD)) + { + return FALSE; + } + + return TRUE; +} +/** + * @brief set features + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Count: the sector count + * @param Feature: Feature val + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Set_Features(PCCARD_HandleType *hpccard, uint32_t Sector_Count, uint8_t Feature) +{ + hpccard->CF.CFAddr.Sector_Count = Sector_Count; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_FEATURE_REG) = Feature; + + if(!CF_SendCommand(hpccard, ATA_SET_FEATURE_CMD)) + { + return FALSE; + } + + return TRUE; +} +/** + * @brief read buffer + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Read_Buffer(PCCARD_HandleType *hpccard, uint8_t *pBuffer) +{ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(CF_SendCommand(hpccard, ATA_READ_BUFFER_CMD)) + { + if (TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Read_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + + return TRUE; +} +/** + * @brief write buffer + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Write_Buffer(PCCARD_HandleType *hpccard, uint8_t *pBuffer) +{ + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = hpccard->CF.CFAddr.Drv; + + if(CF_SendCommand(hpccard, ATA_WRITE_BUFFER_CMD)) + { + if (TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + + return TRUE; +} +/** + * @brief Translate sector + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Address: the sector addr + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Translate_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address) +{ + uint32_t Total_Cylinder; + uint8_t Reg; + + Total_Cylinder = (uint32_t)(hpccard->CF.CFCardInfo.Default_Head * hpccard->CF.CFCardInfo.Default_Sector); // The total sectors in one cylinder + + hpccard->CF.CFAddr.Cylinder = (uint16_t)(Sector_Address / Total_Cylinder); + hpccard->CF.CFAddr.Head = (uint8_t)((Sector_Address % Total_Cylinder) / hpccard->CF.CFCardInfo.Default_Sector); + hpccard->CF.CFAddr.Sector = (uint8_t)((Sector_Address % Total_Cylinder) % hpccard->CF.CFCardInfo.Default_Sector) + 1; + + /* Set the parameters to write a sector */ + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(!CF_SendCommand(hpccard, ATA_TRANSLATE_SECTOR_CMD)) + { + return FALSE; + } + + return TRUE; +} +/** + * @brief write sector WO_ERASE + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Write_Sector_WO_ERASE(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + /* Set the parameters to write a sector */ + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_WRITE_SECTOR_WO_ERASE_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if (PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief write Multiple + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Write_Multiple(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + /* Set the parameters to write a sector */ + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_WRITE_MULTIPLE_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if (PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief read Multiple + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Read_Multiple(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_READ_MULTIPLE_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Read_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief write Multiple WO_ERASE + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Sector_Address: the sector addr + * @param Sector_Count: the sector count + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Write_Multiple_WO_ERASE(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count) +{ + uint16_t Count = 0; + uint8_t Reg; + + if(Sector_Count == 0) + { + Sector_Count = 256; + } + + while(Count < Sector_Count) + { + /* Set the parameters to write a sector */ + Translate_CHSAddr(hpccard, Sector_Address, Count, Sector_Count); + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_WRITE_MULTIPLE_WO_ERASE_CMD)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + Sector_Address += 1; + Count += 1; + + if (Count == Sector_Count) + { + break; + } + + if (Count <= (Sector_Count / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector) + if (Count % hpccard->CF.CFAddr.Sector_Count == 0) + { + break; + } + } + else if (PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + } + + return TRUE; +} +/** + * @brief read long sector + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Address: the sector addr + * @param pBuffer: pointer to the data buffer. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Read_Long_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint8_t *pBuffer) +{ + uint32_t index = 0, Total_Cylinder; + uint8_t Reg; + BOOL command_vaild = TRUE; + + Total_Cylinder = (uint32_t)(hpccard->CF.CFCardInfo.Default_Head * hpccard->CF.CFCardInfo.Default_Sector); // The total sectors in one cylinder + + hpccard->CF.CFAddr.Cylinder = (uint16_t)(Sector_Address / Total_Cylinder); + hpccard->CF.CFAddr.Head = (uint8_t)((Sector_Address % Total_Cylinder) / hpccard->CF.CFCardInfo.Default_Sector); + hpccard->CF.CFAddr.Sector = (uint8_t)((Sector_Address % Total_Cylinder) % hpccard->CF.CFCardInfo.Default_Sector) + 1; + hpccard->CF.CFAddr.Sector_Count = 1; // some CF storage card implement the read long sector command as read sector commend + // set sector count to 1, after read 512 byte data, if the DRQ_BIT still high, means the + // read long sector command work well, because it shoult return 516 byte data (ECC). + + + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_READ_LONG_SECTOR_CMD)) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Read_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + if(PCCARD_Read_STATUS_REG(hpccard) & DRQ_BIT) + { + for(index = 0; index < 4; index++) + { + *(uint8_t *)pBuffer++ = *(uint8_t *)(hpccard->CF.IOAddr); + } + } + else + { + command_vaild = FALSE; + } + + if(PCCARD_Read_STATUS_REG(hpccard) & DRQ_BIT) + { + command_vaild = FALSE; + } + + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + + if(command_vaild == TRUE) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief write long sector + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Address: the sector addr + * @param pBuffer: pointer to the data buffer. + * @retval TRUE or FALSE. + */ +BOOL PCCARD_Write_Long_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint8_t *pBuffer) +{ + uint32_t index = 0, Total_Cylinder; + uint8_t Reg; + BOOL command_vaild = TRUE; + + Total_Cylinder = (uint32_t)(hpccard->CF.CFCardInfo.Default_Head * hpccard->CF.CFCardInfo.Default_Sector); // The total sectors in one cylinder + + hpccard->CF.CFAddr.Cylinder = (uint16_t)(Sector_Address / Total_Cylinder); + hpccard->CF.CFAddr.Head = (uint8_t)((Sector_Address % Total_Cylinder) / hpccard->CF.CFCardInfo.Default_Sector); + hpccard->CF.CFAddr.Sector = (uint8_t)((Sector_Address % Total_Cylinder) % hpccard->CF.CFCardInfo.Default_Sector) + 1; + hpccard->CF.CFAddr.Sector_Count = 1; // some CF storage card implement the read long sector command as read sector commend + // set sector count to 1, after read 512 byte data, if the DRQ_BIT still high, means the + // read long sector command is work well, because it shoult return 516 byte data (ECC). + + + Reg = hpccard->CF.CFAddr.Head | hpccard->CF.CFAddr.Drv | 0xA0; + + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_HIGH) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder >> 8); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CYLINDER_LOW) = (uint8_t)(0xFF & hpccard->CF.CFAddr.Cylinder); + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_NUMBER) = hpccard->CF.CFAddr.Sector; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_SECTOR_COUNT) = hpccard->CF.CFAddr.Sector_Count; + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_CARD_HEAD) = Reg; + + if(CF_SendCommand(hpccard, ATA_WRITE_LONG_SECTOR_CMD)) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Write_Sector(hpccard, pBuffer, PCCARD_SECTOR_SIZE); + + if(PCCARD_Read_STATUS_REG(hpccard) & DRQ_BIT) + { + for(index = 0; index < 4; index++) + { + *(uint8_t *)(hpccard->CF.IOAddr) = *(uint8_t *)pBuffer++; + } + } + else + { + command_vaild = FALSE; + } + + if(PCCARD_Read_STATUS_REG(hpccard) & DRQ_BIT) + { + command_vaild = FALSE; + } + + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT)) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + return FALSE; + } + } + } + + if(command_vaild == TRUE) + { + return TRUE; + } + else + { + return FALSE; + } +} +/** + * @brief read sector + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Transfer_Size: the data length. + * @retval pointer to the data buffer after read. + */ +uint8_t *Read_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Transfer_Size) +{ + uint32_t index = 0; + + XMC_Enable_16bit_Feature(hpccard->Instance, &(hpccard->Init), hpccard->CF.Enable_8_bit_mode); + + if(hpccard->CF.DMAEnable == TRUE) + { + if(hpccard->CF.Enable_8_bit_mode) + { + MYDMA_Config(EDMA_STREAM1, (uint32_t)hpccard->CF.IOAddr, (uint32_t)pBuffer, Transfer_Size, Read_Transfer, Enable_8_bit_Transfer); + } + else + { + MYDMA_Config(EDMA_STREAM1, (uint32_t)hpccard->CF.IOAddr, (uint32_t)pBuffer, (Transfer_Size / 2), Read_Transfer, Enable_16_bit_Transfer); + } + + while(1) + { + if(edma_flag_get(EDMA_FDT1_FLAG) != RESET) + { + edma_flag_clear(EDMA_FDT1_FLAG); + break; + } + } + + pBuffer += 512; + } + else + { + if(hpccard->CF.Enable_8_bit_mode) + { + for(; index < (Transfer_Size) ; index++) + { + *(uint8_t *)pBuffer++ = *(uint8_t *)(hpccard->CF.IOAddr); + } + } + else + { + for(; index < (Transfer_Size / 2); index++) + { + *(uint16_t *)pBuffer = *(uint16_t *)(hpccard->CF.IOAddr); + /* offset to next 16 bit */ + pBuffer += 2; + } + } + } + + XMC_Enable_16bit_Feature(hpccard->Instance, &(hpccard->Init), 1); + return pBuffer; +} +/** + * @brief write sector + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param pBuffer: pointer to the data buffer. + * @param Transfer_Size: the data length. + * @retval pointer to the data buffer after write. + */ +uint8_t *Write_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Transfer_Size) +{ + uint32_t index = 0; + + XMC_Enable_16bit_Feature(hpccard->Instance, &(hpccard->Init), hpccard->CF.Enable_8_bit_mode); + + if(hpccard->CF.DMAEnable == TRUE) + { + if(hpccard->CF.Enable_8_bit_mode) + { + MYDMA_Config(EDMA_STREAM1, (uint32_t)pBuffer, (uint32_t)hpccard->CF.IOAddr, Transfer_Size, Write_Transfer, Enable_8_bit_Transfer); + } + else + { + MYDMA_Config(EDMA_STREAM1, (uint32_t)pBuffer, (uint32_t)hpccard->CF.IOAddr, (Transfer_Size / 2), Write_Transfer, Enable_16_bit_Transfer); + } + + while(1) + { + if(edma_flag_get(EDMA_FDT1_FLAG) != RESET) + { + edma_flag_clear(EDMA_FDT1_FLAG); + break; + } + } + + pBuffer += 512; + } + else + { + if(hpccard->CF.Enable_8_bit_mode) + { + for(; index < (Transfer_Size); index++) + { + *(uint8_t *)(hpccard->CF.IOAddr) = *(uint8_t *)pBuffer++; + } + } + else + { + for(; index < (Transfer_Size / 2); index++) + { + *(uint16_t *)(hpccard->CF.IOAddr) = *(uint16_t *)pBuffer; + /* offset to next 16 bit */ + pBuffer += 2; // offset to next 16 bit + } + } + } + + XMC_Enable_16bit_Feature(hpccard->Instance, &(hpccard->Init), 1); + return pBuffer; +} + +/** + * @brief Reset the PCCARD memory + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval HAL status + */ +BOOL PCCARD_Reset(PCCARD_HandleType *hpccard) +{ + /* Provide an SW reset and Read and verify the: + - CF Configuration Option Register at address 0x98000200 --> 0x80 + - Card Configuration and Status Register at address 0x98000202 --> 0x00 + - Pin Replacement Register at address 0x98000204 --> 0x0C + - Socket and Copy Register at address 0x98000206 --> 0x00 + */ + + uint8_t config_option_reg; + + /* Set up the Reset bit in config option register */ + *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | CONFIG_OPTION_REG) = 0x80; + delay_ms(100); + /* Clear the Reset bit in config option register */ + *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | CONFIG_OPTION_REG) = 0x00; + delay_ms(100); + /* Set the PC card I/O configurations */ + *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | CONFIG_OPTION_REG) = hpccard->CF.Protocol; + delay_ms(100); + + config_option_reg = *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | CONFIG_OPTION_REG); + + if(config_option_reg == hpccard->CF.Protocol) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + * Translate_CHSAddr: + * translate DISK sector number to C.H.S address. + * input : CFCard + * Start (Start sector number) + * Sector_Count (sector count which read from CF card) + * Sector_Limit (maximum sector number) + * output : None + */ +void Translate_CHSAddr(PCCARD_HandleType *hpccard, uint32_t Start, uint16_t Sector_Count, uint16_t Sector_Limit) +{ + uint32_t Total_Cylinder; + uint16_t Prev_Count; + + Prev_Count = (Sector_Limit / hpccard->CF.CFCardInfo.Default_Sector) * hpccard->CF.CFCardInfo.Default_Sector; + + Total_Cylinder = (uint32_t)(hpccard->CF.CFCardInfo.Default_Head * hpccard->CF.CFCardInfo.Default_Sector); // The total sectors in one cylinder + + hpccard->CF.CFAddr.Cylinder = (uint16_t)(Start / Total_Cylinder); + hpccard->CF.CFAddr.Head = (uint8_t)((Start % Total_Cylinder) / hpccard->CF.CFCardInfo.Default_Sector); + hpccard->CF.CFAddr.Sector = (uint8_t)((Start % Total_Cylinder) % hpccard->CF.CFCardInfo.Default_Sector) + 1; + + if ((Prev_Count <= Sector_Count) && (Sector_Count <= Sector_Limit)) + { + hpccard->CF.CFAddr.Sector_Count = (uint8_t)(Sector_Limit % hpccard->CF.CFCardInfo.Default_Sector); + } + else + { + hpccard->CF.CFAddr.Sector_Count = (uint8_t)hpccard->CF.CFCardInfo.Default_Sector; + } +} + +/** + * @brief Read CIS Information. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL ReadCFCardCISInformation(PCCARD_HandleType *hpccard) +{ + uint8_t CIS_1, CIS_2, CIS_3; + + CIS_1 = *(uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | 0x0); + CIS_2 = *(uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | 0x2); + CIS_3 = *(uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | 0x4); + + if(CIS_1 == 0x1 && CIS_2 == 0x4 && CIS_3 == 0xdf) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + * @brief Send command. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Cmd: the command value + * @retval TRUE or FALSE. + */ +BOOL CF_SendCommand(PCCARD_HandleType *hpccard, uint8_t Cmd) +{ + uint8_t Reg; + + do + { + *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_STATUS_CMD) = Cmd; + + while(!TaskFileRegIsValid(hpccard)) ; + + Reg = PCCARD_Read_STATUS_REG(hpccard); + + if ((Reg & ERR_BIT) != 0) + { + return FALSE; + } + } + while((Reg & RDY_BIT) == 0); + + return TRUE; +} +/** + * @brief Check the PCCARD TaskFileReg valid. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval TRUE or FALSE. + */ +BOOL TaskFileRegIsValid(PCCARD_HandleType *hpccard) +{ + uint8_t status = 0; + + status = PCCARD_Read_STATUS_REG(hpccard); + + if(status & BUSY_BIT) + { + return FALSE; + } + + return TRUE; +} +/** + * @brief Check the PCCARD info valid. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @param Sector_Count: sector count + * @param Head_Count:head count + * @retval TRUE or FALSE. + */ +BOOL Vaild_Init_Drive_Para(PCCARD_HandleType *hpccard, uint16_t Sector_Count, uint8_t Head_Count) +{ + uint8_t CardInfo[PCCARD_SECTOR_SIZE * sizeof(uint8_t)] = {0}; + + memset(CardInfo, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(PCCARD_Identify(hpccard)) + { + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | DRQ_BIT)) + { + Read_Sector(hpccard, CardInfo, PCCARD_SECTOR_SIZE); + break; + } + else if(PCCARD_Read_STATUS_REG(hpccard) == (RDY_BIT | DSC_BIT | ERR_BIT)) + { + printf("\r\nCommand Pass, but ERR bit is high"); + printf("\r\nCF Status Reg=%#x", PCCARD_Read_STATUS_REG(hpccard)); + printf("\r\nCF Error Reg=%#x", PCCARD_Read_ERROR_REG(hpccard)); + return FALSE; + } + } + } + } + + while(1) + { + if(TaskFileRegIsValid(hpccard)) + { + if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x50) + { + break; + } + else if((PCCARD_Read_STATUS_REG(hpccard) & (RDY_BIT | DSC_BIT | ERR_BIT)) == 0x51) + { + printf("\r\nSend Command Failed"); + printf("\r\nCF Status Reg=%#x", PCCARD_Read_STATUS_REG(hpccard)); + printf("\r\nCF Error Reg=%#x", PCCARD_Read_ERROR_REG(hpccard)); + return FALSE; + } + } + } + + if (((uint16_t)CardInfo[0] | (uint16_t)CardInfo[1] << 8) == 0x848A && ((uint16_t)CardInfo[110] | \ + (uint16_t)CardInfo[111] << 8) == Head_Count && ((uint16_t)CardInfo[112] | (uint16_t)CardInfo[113] << 8) == Sector_Count ) + { + return TRUE; + } + else + { + return FALSE; + } + +} +/** + * @brief printf the verification result. + * @param result: pointer to a verification_result structure that contains + * various kinds of verification. + * @retval None. + */ +void show_verification_result(verification_result_struct *result) +{ + printf("\r\n"); + printf("\r\n----------------------------------------------------------------------"); + printf("\r\n%s %-6s ", "ATTRIBUTE_RW_PASS ", ((result->ATTRIBUTE_RW_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n%s %-6s ", "READ_ATTRIBUTE_CIS ", ((result->CIS_READ_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n%s %-6s ", "IDENTIFY_DRIVE ", ((result->ATA_IDENTIFY_DRIVE_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n%s %-6s ", "EXECUTE_DRIVE_DIAG ", ((result->ATA_EXECUTE_DRIVE_DIAG_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n%s %-6s ", "WRITE_SECTOR ", ((result->ATA_WRITE_SECTOR_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n%s %-6s ", "READ_SECTOR ", ((result->ATA_READ_SECTOR_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n%s %-6s ", "ACESS_25_SECTORS ", ((result->ACESS_25_SECTORS_PASS) ? " PASS" : "FAILED *****")); + printf("\r\n----------------------------------------------------------------------"); + printf("\r\n\r\n"); +} + + +/** + * @brief This function handles PCCARD device interrupt request. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval HAL status + */ +void PCCARD_IRQHandler(PCCARD_HandleType *hpccard) +{ +} + + +/** + * @} + */ + +/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### PCCARD Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the PCCARD controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief return the PCCARD controller state + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval HAL state + */ +PCCARD_StateType PCCARD_GetState(PCCARD_HandleType *hpccard) +{ + return hpccard->State; +} +/** + * @brief Get the PCCARD error reg value. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval reg: error reg value. + */ +uint8_t PCCARD_Read_ERROR_REG(PCCARD_HandleType *hpccard) +{ + uint8_t Reg = 0; + + /* Read ERROR Reg operation */ + Reg = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_ERROR_REG); + CF_print(ERR_REG_INFO, ("\r\nCF card ERROR Register value is %#x", Reg)); + return Reg; +} +/** + * @brief Get the PCCARD status reg value. + * @param hpccard: pointer to a PCCARD_HandleType structure that contains + * the configuration information for PCCARD module. + * @retval reg: status reg value. + */ +uint8_t PCCARD_Read_STATUS_REG(PCCARD_HandleType *hpccard) +{ + uint8_t Reg = 0; + + /* Read STATUS Reg operation */ + Reg = *(__IO uint8_t *)(hpccard->CF.IOAddr | ATA_STATUS_CMD); + CF_print(STS_REG_INFO, ("\r\nCF card STATUS Register value is %#x", Reg)); + + return Reg; +} + + +void XMC_IRQHandler(void) +{ + __nop(); +} + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + + + + + + + + + + + + diff --git a/project/at_start_f437/examples/xmc/pc_card/pc_card/cf.h b/project/at_start_f437/examples/xmc/pc_card/pc_card/cf.h new file mode 100644 index 00000000..b7644d1c --- /dev/null +++ b/project/at_start_f437/examples/xmc/pc_card/pc_card/cf.h @@ -0,0 +1,491 @@ +/** + ****************************************************************************** + * @file cf.h + * @brief header file for the cf configuration. + ****************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ +#ifndef __CF_H +#define __CF_H + +/* Includes ------------------------------------------------------------------*/ +#include "stdint.h" +#include "at32f435_437.h" +/** @addtogroup AT32F437_periph_examples + * @{ + */ + +/** @addtogroup XMC_CF_CARD + * @{ + */ +#ifdef __cplusplus +extern "C" { +#endif + + + /* Exported typedef ----------------------------------------------------------*/ + /** @defgroup PCCARD_Exported_Constant PCCARD Exported Constant + * @{ + */ +#define FALSE 0 +#define TRUE 1 +#define XMC_BASE ((uint32_t)0xA8000000) /*!< XMC base address */ +#define XMC_BANK4_ (XMC_BASE + 0x0000000) /*!< XMC Bank4 base address */ +#define PCCARD_DEVICE_ADDRESS XMC_BANK4_ /* 0x9000 0000 */ +#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */ +#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(XMC_BANK4_ + 0x4000000)) /* Attribute space size to @0x9BFF FFFF */ +#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(XMC_BANK4_ + 0x6000000)) /* IO space size to @0x9FFF FFFF */ + +// In XMC document page 545/1128, the XMC is not supported True IDE mode. // +#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(XMC_BANK4_ + PCCARD_IO_SPACE_ADDRESS + 0x1F0)) /* IO space size to @0x9FFF FFFF */ +#define PCCARD_IO_SPACE_SECONDARY_ADDR ((uint32_t)(XMC_BANK4_ + PCCARD_IO_SPACE_ADDRESS + 0x170)) /* IO space size to @0x9FFF FFFF */ + + /* Compact Flash-ATA registers description */ +#define ATA_DATA ((uint8_t)0x00) /* Data register */ +#define ATA_ERROR_REG ((uint8_t)0x01) /* Error register */ +#define ATA_FEATURE_REG ((uint8_t)0x01) /* Feature register */ +#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */ +#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */ +#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */ +#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */ +#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */ +#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */ +#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */ +#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */ + +// CFA spec. page 19 +// The configuration of the CompactFlash Card will be controlled using the standard +// PCMCIA configuration registers starting at address 200h in the Attribute Memory space + /* attribute memory space register description */ +#define ATTRIBUTE_MEM_BASE 0 +#define ATTRIBUTE_MEM_CONFIG_BASE 0x200 +#define CONFIG_OPTION_REG ATTRIBUTE_MEM_CONFIG_BASE + 0x00 +#define CARD_CONFIG_STATUS_REG ATTRIBUTE_MEM_CONFIG_BASE + 0x02 +#define PIN_REPLACE_REG ATTRIBUTE_MEM_CONFIG_BASE + 0x04 +#define SOCKET_COPY_REG ATTRIBUTE_MEM_CONFIG_BASE + 0x06 +// #define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */ + + /* configuration option register */ +#define CONF0_BIT 0x01 +#define CONF1_BIT 0x02 +#define CONF2_BIT 0x04 +#define CONF3_BIT 0x08 +#define CONF4_BIT 0x10 +#define CONF5_BIT 0x20 +#define LEVLREQ_BIT 0x40 +#define SRESET_BIT 0x80 + +#define CF_MEM_MAP_MODE 0x00 +#define CF_IO_16_MODE 0x01 +#define CF_IO_PRICH_MODE 0x02 // the XMC is not supported True IDE mode. +#define CF_IO_SECCH_MODE 0x03 // the XMC is not supported True IDE mode. + + /* Compact Flash-ATA commands */ +#define ATA_CHECK_POWER_MODE_CMD ((uint8_t)0xE5) +#define ATA_EXECUTE_DRIVE_DIAG_CMD ((uint8_t)0x90) +#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0) +#define ATA_FORMAT_TRACK_CMD ((uint8_t)0x50) +#define ATA_IDENTIFY_DRIVE_CMD ((uint8_t)0xEC) +#define ATA_IDLE_CMD ((uint8_t)0xE3) +#define ATA_IDLE_IMMEDIATE_CMD ((uint8_t)0xE1) +#define ATA_INIT_DRIVE_PARA_CMD ((uint8_t)0x91) +#define ATA_READ_BUFFER_CMD ((uint8_t)0xE4) +#define ATA_READ_LONG_SECTOR_CMD ((uint8_t)0x22) +#define ATA_READ_MULTIPLE_CMD ((uint8_t)0xC4) +#define ATA_READ_SECTOR_CMD ((uint8_t)0x20) +#define ATA_READ_VERIFY_SECTOR_CMD ((uint8_t)0x40) +#define ATA_RECALIBRATE_CMD ((uint8_t)0x10) +#define ATA_REQUEST_SENSE_CMD ((uint8_t)0x03) +#define ATA_SECURITY_DISABLE_PASSWORD_CMD ((uint8_t)0xF6) +#define ATA_SECURITY_EREASE_PREPARE_CMD ((uint8_t)0xF3) +#define ATA_SECURITY_ERASE_UNIT_CMD ((uint8_t)0xF4) +#define ATA_SECURITY_FREEZE_LOCK_CMD ((uint8_t)0xF5) +#define ATA_SECURITY_SET_PASSWORD_CMD ((uint8_t)0xF1) +#define ATA_SECURITY_UNLOCK_CMD ((uint8_t)0xF2) +#define ATA_SEEK_CMD ((uint8_t)0x70) +#define ATA_SET_FEATURE_CMD ((uint8_t)0xEF) +#define ATA_SET_MULTIPLE_MODE_CMD ((uint8_t)0xC6) +#define ATA_SET_SLEEP_MODE_CMD ((uint8_t)0xE6) +#define ATA_STANDBY_CMD ((uint8_t)0xE2) +#define ATA_STANDBY_IMMEDIATE_CMD ((uint8_t)0xE0) +#define ATA_TRANSLATE_SECTOR_CMD ((uint8_t)0x87) +#define ATA_WEAR_LEVEL_CMD ((uint8_t)0xF5) +#define ATA_WRITE_BUFFER_CMD ((uint8_t)0xE8) +#define ATA_WRITE_LONG_SECTOR_CMD ((uint8_t)0x32) +#define ATA_WRITE_MULTIPLE_CMD ((uint8_t)0xC5) +#define ATA_WRITE_MULTIPLE_WO_ERASE_CMD ((uint8_t)0xCD) +#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30) +#define ATA_WRITE_SECTOR_WO_ERASE_CMD ((uint8_t)0x38) +#define ATA_WRITE_VERIFY_CMD ((uint8_t)0x3C) + + /* feature command */ +#define ENABLE_8BIT_MODE 0x01 +#define ENABLE_PWR_LV1 0x0a +#define DISABLE_READ_LOOK_AHEAD 0x55 +#define DISABLE_POR 0x66 +#define NOP 0x69 +#define DISABLE_8BIT_MODE 0x81 +#define DISABLE_PWR_LV1 0x8a +#define SET_HOST_CUR_SOURCE_CAP 0x9a +#define APPLY_4BYTE_DATA_RW_LONG_CMD 0xbb +#define ENABLE_POR 0xcc + + /* status register */ +#define BUSY_BIT 0x80 +#define RDY_BIT 0x40 +#define DWF_BIT 0x20 +#define DSC_BIT 0x10 +#define DRQ_BIT 0x08 +#define CORR_BIT 0x04 +#define ERR_BIT 0x01 + + /* error register */ +#define BBK_BIT 0x80 +#define UNC_BIT 0x40 +#define IDNF_BIT 0x10 +#define ABRT_BIT 0x04 +#define AMNF_BIT 0x01 + + /* Compact Flash status */ +#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60) +#define PCCARD_BUSY ((uint8_t)0x80) +#define PCCARD_PROGR ((uint8_t)0x01) +#define PCCARD_READY ((uint8_t)0x40) + +//#define PCCARD_SECTOR_SIZE ((uint32_t)255) /* In half words */ +#define PCCARD_SECTOR_SIZE ((uint32_t)512) +#define PCCARD_LONG_SECTOR_SIZE ((uint32_t)516) +#define PCCARD_25_SECTORS_SIZES ((uint32_t)(512*25)) + /* CF CIS information */ +#define CISTPL_DEVICE 0x01 +#define CISTPL_DEVICE_OC 0x1c +#define CISTPL_JEDEC_C 0x18 +#define CISTPL_MANFID 0x20 +#define CISTPL_VERS_1 0x15 +#define CISTPL_FUNCID 0x21 +#define CISTPL_FUNCE 0x22 +#define CISTPL_CONFIG 0x1a +#define CISTPL_CFTABLE_ENTRY 0x1b +#define CISTPL_NO_LINK 0x14 +#define CISTPL_END 0xff +#define TPL_LINK_LOC 16 +#define MAX_CIS_LEN 0x200 + + /* Compact Flash redefinition */ + +#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS +#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS +#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS +#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS +#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR + +#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR +#define CF_BUSY PCCARD_BUSY +#define CF_PROGR PCCARD_PROGR +#define CF_READY PCCARD_READY + +#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE +#define Read_Transfer 1 +#define Write_Transfer 0 +#define Enable_8_bit_Transfer 1 +#define Enable_16_bit_Transfer 0 + +#define CF_print( cond, _x_) \ + if ( cond ) { \ + printf _x_ ; \ + } + + /* For print message level */ +#define ERR_REG_INFO 0 +#define STS_REG_INFO 0 +#define PRT_INIT_INFO 1 +#define PRT_CMD_INFO 0 +#define PRT_ERR_INFO 0 + + /** + * @} + */ + + /* Exported typedef ----------------------------------------------------------*/ + /** @defgroup PCCARD_Exported_Types PCCARD Exported Types + * @{ + */ + + typedef unsigned char BOOL; + typedef enum + { + UNLOCKED = 0x00, + LOCKED = 0x01 + } LockType; + typedef enum + { + STATUS_OK = 0x00, + STATUS_ERROR = 0x01, + } StatusType; + + /** + * @brief HAL PCCARD State structures definition + */ + typedef enum + { + PCCARD_STATE_RESET = 0x00, /*!< PCCARD peripheral not yet initialized or disabled */ + PCCARD_STATE_READY = 0x01, /*!< PCCARD peripheral ready */ + PCCARD_STATE_BUSY = 0x02, /*!< PCCARD peripheral busy */ + PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */ + } PCCARD_StateType; + + + /* CF type */ + typedef struct + { + uint16_t Default_Cylinder; + uint8_t Default_Head; + uint16_t Default_Sector; + uint16_t Current_Cylinder; + uint8_t Current_Head; + uint16_t Current_Sector; + uint32_t Total_Sector; + uint32_t Total_LBA_Sector; + uint16_t Max_Mutiple_Sector; + uint16_t Mutiple_Sector_Setting; + } CFCardInfoStruct; + + /* CF address struct */ + typedef struct + { + uint16_t Sector_Count; + uint16_t Cylinder; + uint8_t Head; + uint8_t Sector; + uint8_t Drv; + uint32_t SectorSize; + } CFCardAddrStruct; + + /* CF card structure */ + typedef struct + { + uint32_t IOAddr; + BOOL DMAEnable; + BOOL Enable_8_bit_mode; + CFCardInfoStruct CFCardInfo; + CFCardAddrStruct CFAddr; + uint16_t Protocol; + + /* Drive Name */ + uint32_t Drive; + + } CFCardStruct; + + /* ATA-Command verification result */ + typedef struct + { + BOOL ATA_CHECK_POWER_MODE_PASS; + BOOL ATA_EXECUTE_DRIVE_DIAG_PASS; + BOOL ATA_ERASE_SECTOR_PASS; + BOOL ATA_FORMAT_TRACK_PASS; + BOOL ATA_IDENTIFY_DRIVE_PASS; + BOOL ATA_IDLE_PASS; + BOOL ATA_IDLE_IMMEDIATE_PASS; + BOOL ATA_INIT_DRIVE_PARA_PASS; + BOOL ATA_READ_BUFFER_PASS; + BOOL ATA_READ_LONG_SECTOR_PASS; + BOOL ATA_READ_MULTIPLE_PASS; + BOOL ATA_READ_SECTOR_PASS; + BOOL ATA_READ_VERIFY_SECTOR_PASS; + BOOL ATA_RECALIBRATE_PASS; + BOOL ATA_REQUEST_SENSE_PASS; + BOOL ATA_SECURITY_DISABLE_PASSWORD_PASS; + BOOL ATA_SECURITY_EREASE_PREPARE_PASS; + BOOL ATA_SECURITY_ERASE_UNIT_PASS; + BOOL ATA_SECURITY_FREEZE_LOCK_PASS; + BOOL ATA_SECURITY_SET_PASSWORD_PASS; + BOOL ATA_SECURITY_UNLOCK_PASS; + BOOL ATA_SEEK_PASS; + BOOL ATA_SET_FEATURE_PASS; + BOOL ATA_SET_MULTIPLE_MODE_PASS; + BOOL ATA_SET_SLEEP_MODE_PASS; + BOOL ATA_STANDBY_PASS; + BOOL ATA_STANDBY_IMMEDIATE_PASS; + BOOL ATA_TRANSLATE_SECTOR_PASS; + BOOL ATA_WEAR_LEVEL_PASS; + BOOL ATA_WRITE_BUFFER_PASS; + BOOL ATA_WRITE_LONG_SECTOR_PASS; + BOOL ATA_WRITE_MULTIPLE_PASS; + BOOL ATA_WRITE_MULTIPLE_WO_ERASE_PASS; + BOOL ATA_WRITE_SECTOR_PASS; + BOOL ATA_WRITE_SECTOR_WO_ERASE_PASS; + BOOL ATA_WRITE_VERIFY_PASS; + BOOL ACESS_25_SECTORS_PASS; + BOOL CIS_READ_PASS; + BOOL ATTRIBUTE_RW_PASS; + + } verification_result_struct; + + /** + * @brief XMC_PCCARD handle Structure definition + */ + typedef struct + { + xmc_bank4_type *Instance; /*!< Register base address for PCCARD device */ + + xmc_pccard_init_type Init; /*!< PCCARD device control configuration parameters */ + + __IO PCCARD_StateType State; /*!< PCCARD device access state */ + + LockType Lock; /*!< PCCARD Lock */ + + CFCardStruct CF; + + } PCCARD_HandleType; + /** + * @} + */ + + /* Exported constants --------------------------------------------------------*/ + /* Exported macro ------------------------------------------------------------*/ + /** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros + * @{ + */ + + /** @brief Reset PCCARD handle state + * @param __HANDLE__: specifies the PCCARD handle. + * @retval None + */ +#define __PCCARD_Reset_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = PCCARD_STATE_RESET) + /** + * @} + */ + + /* Exported functions --------------------------------------------------------*/ + /** @addtogroup PCCARD_Exported_Functions PCCARD Exported Functions + * @{ + */ + + /** @addtogroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + /* Initialization/de-initialization functions **********************************/ + StatusType PCCARD_Init(PCCARD_HandleType *hpccard, xmc_nand_pccard_timinginit_type *ComSpaceTiming, xmc_nand_pccard_timinginit_type *AttSpaceTiming, xmc_nand_pccard_timinginit_type *IOSpaceTiming); + StatusType PCCARD_DeInit(PCCARD_HandleType *hpccard); + StatusType Enable_Wait_Feature(PCCARD_HandleType *hpccard); + /** + * @} + */ + + /** @addtogroup PCCARD_Exported_Functions_Group2 Input Output and memory functions + * @{ + */ + /* IO operation functions *****************************************************/ + + BOOL PCCARD_Read_ID(PCCARD_HandleType *hpccard); + BOOL PCCARD_Identify(PCCARD_HandleType *hpccard); + BOOL PCCARD_Write_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Read_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Erase_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Diagnostic(PCCARD_HandleType *hpccard); + BOOL PCCARD_Reset(PCCARD_HandleType *hpccard); + BOOL PCCARD_Check_Power_Mode(PCCARD_HandleType *hpccard); + BOOL PCCARD_Idle(PCCARD_HandleType *hpccard, uint32_t Sector_Count); + BOOL PCCARD_Idle_Immediate(PCCARD_HandleType *hpccard); + BOOL PCCARD_Set_Sleep_Mode(PCCARD_HandleType *hpccard); + BOOL PCCARD_Standby(PCCARD_HandleType *hpccard); + BOOL PCCARD_Standby_Immediate(PCCARD_HandleType *hpccard); + BOOL PCCARD_Reuqest_Sense(PCCARD_HandleType *hpccard); + BOOL PCCARD_Read_Buffer(PCCARD_HandleType *hpccard, uint8_t *pBuffer); + BOOL PCCARD_Write_Buffer(PCCARD_HandleType *hpccard, uint8_t *pBuffer); + BOOL PCCARD_Recalibrate(PCCARD_HandleType *hpccard); + BOOL PCCARD_Init_Drive_Para(PCCARD_HandleType *hpccard, uint16_t Sector_Count, uint8_t Head_Count); + BOOL PCCARD_Seek(PCCARD_HandleType *hpccard, uint8_t Head_Count, uint16_t Cylinder_Count); + BOOL PCCARD_Translate_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address); + BOOL PCCARD_Read_Long_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint8_t *pBuffer); + BOOL PCCARD_Write_Long_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint8_t *pBuffer); + BOOL PCCARD_Write_Sector_WO_ERASE(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Format_Track(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Read_Verify_Sector(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint16_t Sector_Count); + BOOL PCCARD_Write_Verify(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Set_Multiple_Mode(PCCARD_HandleType *hpccard, uint32_t Sector_Count); + BOOL PCCARD_Set_Features(PCCARD_HandleType *hpccard, uint32_t Sector_Count, uint8_t Feature); + BOOL PCCARD_Write_Multiple(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Read_Multiple(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + BOOL PCCARD_Write_Multiple_WO_ERASE(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Sector_Address, uint32_t Sector_Count); + + BOOL ReadCFCardCISInformation(PCCARD_HandleType *hpccard); + BOOL CF_SendCommand(PCCARD_HandleType *hpccard, uint8_t Cmd); + BOOL TaskFileRegIsValid(PCCARD_HandleType *hpccard); + BOOL Vaild_Init_Drive_Para(PCCARD_HandleType *hpccard, uint16_t Sector_Count, uint8_t Head_Count); + + void Translate_CHSAddr(PCCARD_HandleType *hpccard, uint32_t Sector_Address, uint16_t Sector_Count, uint16_t Sector_Limit); + void PCCARD_IRQHandler(PCCARD_HandleType *hpccard); + void PCCARD_ITCallback(PCCARD_HandleType *hpccard); + void show_verification_result(verification_result_struct *result); + uint8_t *Read_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Transfer_Size); + uint8_t *Write_Sector(PCCARD_HandleType *hpccard, uint8_t *pBuffer, uint32_t Transfer_Size); + + /** + * @} + */ + + /** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions + * @{ + */ + /* PCCARD State functions *******************************************************/ + PCCARD_StateType PCCARD_GetState(PCCARD_HandleType *hpccard); + uint8_t PCCARD_Read_ERROR_REG(PCCARD_HandleType *hpccard); + uint8_t PCCARD_Read_STATUS_REG(PCCARD_HandleType *hpccard); + + +#define __XMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->BK4STS &(__FLAG__)) == (__FLAG__)) +#define __XMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) BIT_CLEAR((__INSTANCE__)->BK4STS, (__FLAG__)) + + StatusType XMC_PCCARD_InitCtrl(xmc_bank4_type *Device, xmc_pccard_init_type *Init, uint8_t Set_reg_8_bit); + StatusType XMC_Enable_Wait_Feature(xmc_bank4_type *Device, xmc_pccard_init_type *Init); + StatusType XMC_Enable_16bit_Feature(xmc_bank4_type *Device, xmc_pccard_init_type *Init, uint8_t Set_reg_8_bit); + StatusType XMC_PCCARD_InitCommonSpaceTiming(xmc_bank4_type *Device, xmc_nand_pccard_timinginit_type *Timing); + StatusType XMC_PCCARD_InitAttributeSpaceTiming(xmc_bank4_type *Device, xmc_nand_pccard_timinginit_type *Timing); + StatusType XMC_PCCARD_InitIOSpaceTiming(xmc_bank4_type *Device, xmc_nand_pccard_timinginit_type *Timing); + + +#define XMC_BKxCTRL_DEV_PCCARD ((uint32_t)0x00000000) +#define BKxTMGMEM_CLEAR_MASK ((uint32_t)(XMC_BK4TMGMEM_STP | XMC_BK4TMGMEM_OP |\ + XMC_BK4TMGMEM_HLD | XMC_BK4TMGMEM_WRSTP)) + +#define BKxTMGATT_CLEAR_MASK ((uint32_t)(XMC_BK4TMGATT_STP | XMC_BK4TMGATT_OP |\ + XMC_BK4TMGATT_HLD | XMC_BK4TMGATT_WRSTP)) + +#define BK4TMGIO_CLEAR_MASK ((uint32_t)(XMC_BK4TMGIO_STP | XMC_BK4TMGIO_OP | \ + XMC_BK4TMGIO_HLD | XMC_BK4TMGIO_WRSTP)) +#endif + /** + * @} + */ + /** + * @} + */ +#ifdef __cplusplus +} +#endif + + /** + * @} + */ + /** + * @} + */ + + diff --git a/project/at_start_f437/examples/xmc/pc_card/readme.txt b/project/at_start_f437/examples/xmc/pc_card/readme.txt new file mode 100644 index 00000000..18d53dd5 --- /dev/null +++ b/project/at_start_f437/examples/xmc/pc_card/readme.txt @@ -0,0 +1,56 @@ +/** + ************************************************************************** + * @file readme.txt + * @brief readme + ************************************************************************** + */ + + this example provides a basic example of how to use the xmc firmware library and + an associate driver to perform read/write operations on the sandisk compactflash + memory. + usart1 using pa9 to printf the result. + + the pin to pin with compactflash and xmc: + - xmc_a0 pf0 ---> a0 + - xmc_a1 pf1 ---> a1 + - xmc_a2 pf2 ---> a2 + - xmc_a3 pf3 ---> a3 + - xmc_a4 pf4 ---> a4 + - xmc_a5 pf5 ---> a5 + - xmc_a6 pf12 ---> a6 + - xmc_a7 pf13 ---> a7 + - xmc_a8 pf14 ---> a8 + - xmc_a9 pf15 ---> a9 + - xmc_a10 pd5 ---> a10 + + - xmc_d0 pb14 ---> data[0] + - xmc_d1 pc6 ---> data[1] + - xmc_d2 pc11 ---> data[2] + - xmc_d3 pc12 ---> data[3] + - xmc_d4 pe7 ---> data[4] + - xmc_d5 pa3 ---> data[5] + - xmc_d6 pa4 ---> data[6] + - xmc_d7 pa5 ---> data[7] + - xmc_d8 pe11 ---> data[8] + - xmc_d9 pe12 ---> data[9] + - xmc_d10 pe13 ---> data[10] + - xmc_d11 pe14 ---> data[11] + - xmc_d12 pe15 ---> data[12] + - xmc_d13 pb12 ---> data[13] + - xmc_d14 pd9 ---> data[14] + - xmc_d15 pd10 ---> data[15] + + - xmc_nce4_1 pg10 ---> CE1 + - xmc_nce4_2 pg11 ---> CE2 + - xmc_noe pd4 ---> NOE + - xmc_nwe pc2 ---> NWE + - xmc_nwait pd6 ---> WAIT + - xmc_intr pf10 ---> INTR + - xmc_cd pf9 ---> CD + - xmc_nreg pf7 ---> REG + - xmc_niowr pf8 ---> IOWR + - xmc_niord pf6 ---> IORD + + + + diff --git a/project/at_start_f437/examples/xmc/pc_card/src/at32f435_437_clock.c b/project/at_start_f437/examples/xmc/pc_card/src/at32f435_437_clock.c new file mode 100644 index 00000000..5fcdf0aa --- /dev/null +++ b/project/at_start_f437/examples/xmc/pc_card/src/at32f435_437_clock.c @@ -0,0 +1,119 @@ +/** + ************************************************************************** + * @file at32f435_437_clock.c + * @brief system clock config program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437_clock.h" + +/** + * @brief system clock config program + * @note the system clock is configured as follow: + * - system clock = (hext * pll_ns)/(pll_ms * pll_fr) + * - system clock source = pll (hext) + * - hext = 8000000 + * - sclk = 288000000 + * - ahbdiv = 1 + * - ahbclk = 288000000 + * - apb2div = 2 + * - apb2clk = 144000000 + * - apb1div = 2 + * - apb1clk = 144000000 + * - pll_ns = 144 + * - pll_ms = 1 + * - pll_fr = 4 + * @param none + * @retval none + */ +void system_clock_config(void) +{ + /* enable pwc periph clock */ + crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); + + /* config ldo voltage */ + pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3); + + /* set the flash clock divider */ + flash_clock_divider_set(FLASH_CLOCK_DIV_3); + + /* reset crm */ + crm_reset(); + + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); + + /* wait till hext is ready */ + while(crm_hext_stable_wait() == ERROR) + { + } + + /* config pll clock resource + common frequency config list: pll source selected hick or hext(8mhz) + _________________________________________________________________________________________________ + | | | | | | | | | | | + |pll(mhz)| 288 | 252 | 216 | 192 | 180 | 144 | 108 | 72 | 36 | + |________|_________|_________|_________|_________|_________|_________|_________|_________________| + | | | | | | | | | | | + |pll_ns | 144 | 126 | 108 | 96 | 90 | 72 | 108 | 72 | 72 | + | | | | | | | | | | | + |pll_ms | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | + | | | | | | | | | | | + |pll_fr | FR_4 | FR_4 | FR_4 | FR_4 | FR_4 | FR_4 | FR_8 | FR_8 | FR_16| + |________|_________|_________|_________|_________|_________|_________|_________|________|________| + + if pll clock source selects hext with other frequency values, or configure pll to other + frequency values, please use the at32 new clock configuration tool for configuration. */ + crm_pll_config(CRM_PLL_SOURCE_HEXT, 144, 1, CRM_PLL_FR_4); + + /* enable pll */ + crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); + + /* wait till pll is ready */ + while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) + { + } + + /* config ahbclk */ + crm_ahb_div_set(CRM_AHB_DIV_1); + + /* config apb2clk, the maximum frequency of APB1/APB2 clock is 144 MHz */ + crm_apb2_div_set(CRM_APB2_DIV_2); + + /* config apb1clk, the maximum frequency of APB1/APB2 clock is 144 MHz */ + crm_apb1_div_set(CRM_APB1_DIV_2); + + /* enable auto step mode */ + crm_auto_step_mode_enable(TRUE); + + /* select pll as system clock source */ + crm_sysclk_switch(CRM_SCLK_PLL); + + /* wait till pll is used as system clock source */ + while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) + { + } + + /* disable auto step mode */ + crm_auto_step_mode_enable(FALSE); + + /* update system_core_clock global variable */ + system_core_clock_update(); +} diff --git a/project/at_start_f437/examples/xmc/pc_card/src/at32f435_437_int.c b/project/at_start_f437/examples/xmc/pc_card/src/at32f435_437_int.c new file mode 100644 index 00000000..9d557976 --- /dev/null +++ b/project/at_start_f437/examples/xmc/pc_card/src/at32f435_437_int.c @@ -0,0 +1,139 @@ +/** + ************************************************************************** + * @file at32f435_437_int.c + * @brief main interrupt service routines. + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437_int.h" + +/** @addtogroup AT32F437_periph_examples + * @{ + */ + +/** @addtogroup 437_XMC_sram + * @{ + */ + +/** + * @brief this function handles nmi exception. + * @param none + * @retval none + */ +void NMI_Handler(void) +{ +} + +/** + * @brief this function handles hard fault exception. + * @param none + * @retval none + */ +void HardFault_Handler(void) +{ + /* go to infinite loop when hard fault exception occurs */ + while (1) + { + } +} + +/** + * @brief this function handles memory manage exception. + * @param none + * @retval none + */ +void MemManage_Handler(void) +{ + /* go to infinite loop when memory manage exception occurs */ + while (1) + { + } +} + +/** + * @brief this function handles bus fault exception. + * @param none + * @retval none + */ +void BusFault_Handler(void) +{ + /* go to infinite loop when bus fault exception occurs */ + while (1) + { + } +} + +/** + * @brief this function handles usage fault exception. + * @param none + * @retval none + */ +void UsageFault_Handler(void) +{ + /* go to infinite loop when usage fault exception occurs */ + while (1) + { + } +} + +/** + * @brief this function handles svcall exception. + * @param none + * @retval none + */ +void SVC_Handler(void) +{ +} + +/** + * @brief this function handles debug monitor exception. + * @param none + * @retval none + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief this function handles pendsv_handler exception. + * @param none + * @retval none + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief this function handles systick handler. + * @param none + * @retval none + */ +void SysTick_Handler(void) +{ +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/project/at_start_f437/examples/xmc/pc_card/src/main.c b/project/at_start_f437/examples/xmc/pc_card/src/main.c new file mode 100644 index 00000000..9fefa1c0 --- /dev/null +++ b/project/at_start_f437/examples/xmc/pc_card/src/main.c @@ -0,0 +1,707 @@ +/** + ************************************************************************** + * @file main.c + * @brief main program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ +#include +#include +#include +#include "at32f435_437_board.h" +#include "at32f435_437_clock.h" +#include "cf.h" + + +/** @addtogroup AT32F437_periph_examples + * @{ + */ + +/** @addtogroup 437_XMC_pc_card + * @{ + */ + +typedef enum +{ + FAILED = 0, + PASSED = 1 +} TestStatus; + +/* Private define ------------------------------------------------------------*/ +#define Start_Sector 0 + +/* Private variables ---------------------------------------------------------*/ +PCCARD_HandleType pccardHandle; +xmc_nand_pccard_timinginit_type PCCARD_PMEM4_Timing; +xmc_nand_pccard_timinginit_type PCCARD_PATT4_Timing; +xmc_nand_pccard_timinginit_type PCCARD_PIO4_Timing; +verification_result_struct verification_result; +/* 0 -> Memory/PIO mode, 1 -> IO/PIO mode, 2 -> Memory/DMA mode, 3 -> IO/DMA mode */ +uint8_t Test_Mode = 0; +uint8_t pccard_TxBuffer[PCCARD_SECTOR_SIZE * sizeof(uint8_t)] __attribute__ ((aligned (4))); +uint8_t pccard_RxBuffer[PCCARD_SECTOR_SIZE * sizeof(uint8_t)] __attribute__ ((aligned (4))); +uint8_t pccard_25_Sectors_TxBuffer[PCCARD_25_SECTORS_SIZES * sizeof(uint8_t)] __attribute__ ((aligned (4))); +uint8_t pccard_25_Sectors_RxBuffer[PCCARD_25_SECTORS_SIZES * sizeof(uint8_t)] __attribute__ ((aligned (4))); +uint8_t orig_default_Sector; +uint8_t orig_default_head; +uint32_t u32i; +/* Private function prototypes -----------------------------------------------*/ +static void Fill_Buffer(uint8_t *pBuffer, uint32_t BufferLenght, uint32_t Offset); +static TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint32_t BufferLength); + +/** + * @brief main function. + * @param none + * @retval none + */ +int main(void) +{ + system_clock_config(); + + at32_board_init(); + + uart_print_init(115200); + + crm_periph_clock_enable(CRM_XMC_PERIPH_CLOCK, TRUE); + + pccardHandle.Instance = XMC_BANK4; + PCCARD_PMEM4_Timing.mem_setup_time = 12; + PCCARD_PMEM4_Timing.mem_waite_time = 61; + PCCARD_PMEM4_Timing.mem_hold_time = 14 ; + PCCARD_PMEM4_Timing.mem_hiz_time = 0; + + PCCARD_PATT4_Timing.mem_setup_time = 12; + PCCARD_PATT4_Timing.mem_waite_time = 99; + PCCARD_PATT4_Timing.mem_hold_time = 12; + PCCARD_PATT4_Timing.mem_hiz_time = 1; + + PCCARD_PIO4_Timing.mem_setup_time = 24; + PCCARD_PIO4_Timing.mem_waite_time = 61; + PCCARD_PIO4_Timing.mem_hold_time = 8; + PCCARD_PIO4_Timing.mem_hiz_time = 1; + + + pccardHandle.Init.enable_wait = 1; + pccardHandle.Init.delay_time_cr = 0; + pccardHandle.Init.delay_time_ar = 0; + memset(&verification_result, 0, sizeof(verification_result)); + + + while(Test_Mode < 4) + { + /* 0 -> 16-bit Memory/PIO mode + * 2 -> 16-bit IO/PIO mode + * 4 -> 16-bit Memory/DMA mode + * 6 -> 16-bit IO/DMA mode + */ + switch(Test_Mode) + { + case 0: + pccardHandle.CF.Protocol = CF_MEM_MAP_MODE; + pccardHandle.CF.IOAddr = PCCARD_COMMON_SPACE_ADDRESS; + pccardHandle.CF.DMAEnable = FALSE; + pccardHandle.CF.Enable_8_bit_mode = FALSE; + printf("\r\n16-bit Memory/PIO mode Start... "); + break; + + case 1: + pccardHandle.CF.Protocol = CF_IO_16_MODE; + pccardHandle.CF.IOAddr = PCCARD_IO_SPACE_ADDRESS; + pccardHandle.CF.DMAEnable = FALSE; + pccardHandle.CF.Enable_8_bit_mode = FALSE; + printf("\r\n16-bit IO/PIO mode Start... "); + break; + + case 2: + pccardHandle.CF.Protocol = CF_MEM_MAP_MODE; + pccardHandle.CF.IOAddr = PCCARD_COMMON_SPACE_ADDRESS; + pccardHandle.CF.DMAEnable = TRUE; + pccardHandle.CF.Enable_8_bit_mode = FALSE; + printf("\r\n16-bit Memory/DMA mode Start... "); + break; + + case 3: + pccardHandle.CF.Protocol = CF_IO_16_MODE; + pccardHandle.CF.IOAddr = PCCARD_IO_SPACE_ADDRESS; + pccardHandle.CF.DMAEnable = TRUE; + pccardHandle.CF.Enable_8_bit_mode = FALSE; + printf("\r\n16-bit IO/DMA mode Start... "); + break; + + + default: + printf("\r\nSelect Test Mode Failed"); + break; + } + + pccardHandle.CF.Drive = 0; + + /* Init Compact Flash Controller */ + CF_print(PRT_INIT_INFO, ("\r\nInit Compact Flash Card...")); + + if(PCCARD_Init(&pccardHandle, &PCCARD_PMEM4_Timing, &PCCARD_PATT4_Timing, &PCCARD_PIO4_Timing) != STATUS_OK) + { + printf("\r\nCompact Flash card Init Failed"); + break; + } + + /* Reset Compact Flash card */ + CF_print(PRT_INIT_INFO, ("\r\nReset Compact Flash Card...")); + + if(PCCARD_Reset(&pccardHandle)) + { + verification_result.ATTRIBUTE_RW_PASS = TRUE; + } + + CF_print(PRT_INIT_INFO, ("\r\nSet Wait Feature...")); + + if(Enable_Wait_Feature(&pccardHandle) != STATUS_OK) + { + printf("\r\nCompact Flash card Set Wait Feature Failed"); + break; + } + + /* Read CF Card CIS from CF card's attribute memory */ + if(ReadCFCardCISInformation(&pccardHandle)) + { + verification_result.CIS_READ_PASS = TRUE; + } + + /* CF-ATA Command Set Test Started */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_IDENTIFY_DRIVE...")); + + /* Read Compact Flash Card ID (CF_ATA_IDENTIFY_DRIVE) */ + if(PCCARD_Read_ID(&pccardHandle)) + { + verification_result.ATA_IDENTIFY_DRIVE_PASS = TRUE; + } + + /* Execute Drive Diagnostic */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_EXECUTE_DRIVE_DIAG...")); + + if(PCCARD_Diagnostic(&pccardHandle)) + { + verification_result.ATA_EXECUTE_DRIVE_DIAG_PASS = TRUE; + } + + /* Write Compact Flash Card Sector */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_WRITE_SECTOR...")); + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); + if(!PCCARD_Write_Sector(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Secor Failed"); + break; + } + + /* Read Compact Flash Card Sector */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_READ_SECTOR...")); + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Sector(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Secor Failed"); + break; + } + /* Checking data integrity */ + if(Buffercmp(pccard_TxBuffer, pccard_RxBuffer, PCCARD_SECTOR_SIZE) == PASSED) + { + verification_result.ATA_READ_SECTOR_PASS = TRUE; + verification_result.ATA_WRITE_SECTOR_PASS = TRUE; + } + else + { + verification_result.ATA_READ_SECTOR_PASS = FALSE; + verification_result.ATA_WRITE_SECTOR_PASS = FALSE; + } + + + /* Write Compact Flash Card Buffer */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_WRITE_BUFFER...")); + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); + + if(!PCCARD_Write_Buffer(&pccardHandle, pccard_TxBuffer)) + { + printf("\r\nCompact Flash card Write Buffer Failed"); + break; + } + + /* Read Compact Flash Card Buffer */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_READ_BUFFER...")); + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Buffer(&pccardHandle, pccard_RxBuffer)) + { + printf("\r\nCompact Flash card Read Buffer Failed"); + break; + } + /* Checking data integrity */ + if(Buffercmp(pccard_TxBuffer, pccard_RxBuffer, PCCARD_SECTOR_SIZE) == PASSED) + { + verification_result.ATA_READ_BUFFER_PASS = TRUE; + verification_result.ATA_WRITE_BUFFER_PASS = TRUE; + } + else + { + verification_result.ATA_READ_BUFFER_PASS = FALSE; + verification_result.ATA_WRITE_BUFFER_PASS = FALSE; + } + + /* Recalibrate */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_RECALIBRATE...")); + + if(PCCARD_Recalibrate(&pccardHandle)) + { + verification_result.ATA_RECALIBRATE_PASS = TRUE; + } + + /* Initialize Drive Parameters */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_Init_Drive_Para...")); + orig_default_Sector = pccardHandle.CF.CFCardInfo.Current_Sector; + orig_default_head = pccardHandle.CF.CFCardInfo.Current_Head; + + + pccardHandle.CF.CFCardInfo.Current_Sector -= 1; + pccardHandle.CF.CFCardInfo.Current_Head -= 1; + + if(!PCCARD_Init_Drive_Para(&pccardHandle, pccardHandle.CF.CFCardInfo.Current_Sector, pccardHandle.CF.CFCardInfo.Current_Head - 1)) + { + printf("\r\nInit Drive Para fail"); + break; + } + /* check the command is vailded */ + if(Vaild_Init_Drive_Para(&pccardHandle, pccardHandle.CF.CFCardInfo.Current_Sector, pccardHandle.CF.CFCardInfo.Current_Head)) + { + verification_result.ATA_INIT_DRIVE_PARA_PASS = TRUE; + } + + pccardHandle.CF.CFCardInfo.Current_Sector = orig_default_Sector; + pccardHandle.CF.CFCardInfo.Current_Head = orig_default_head; + + if(!PCCARD_Init_Drive_Para(&pccardHandle, orig_default_Sector, orig_default_head - 1)) + { + printf("\r\nInit Drive Para fail"); + break; + } + /* check restore is vailded */ + if(!Vaild_Init_Drive_Para(&pccardHandle, pccardHandle.CF.CFCardInfo.Current_Sector, pccardHandle.CF.CFCardInfo.Current_Head)) + { + verification_result.ATA_INIT_DRIVE_PARA_PASS = FALSE; + } + + /* Seek */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_SEEK...")); + + if(PCCARD_Seek(&pccardHandle, pccardHandle.CF.CFCardInfo.Default_Head - 1, pccardHandle.CF.CFCardInfo.Default_Cylinder + 1)) + { + verification_result.ATA_SEEK_PASS = TRUE; + } + + /* Erase Compact Flash Card Sector */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_ERASE_SECTOR...")); + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); + + if(!PCCARD_Write_Sector(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Secor Failed"); + break; + } + + if(!PCCARD_Erase_Sector(&pccardHandle, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Erase Secor Failed"); + break; + } + + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Sector(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Secor Failed"); + break; + } + else + { + verification_result.ATA_ERASE_SECTOR_PASS = TRUE; + + for(u32i = 0; u32i < PCCARD_SECTOR_SIZE; u32i++) + { + if(*(pccard_RxBuffer + u32i) != 0x0) + { + verification_result.ATA_ERASE_SECTOR_PASS = FALSE; + CF_print(PRT_ERR_INFO, ("\r\nErase sector error at address offset 0x%0.2x:(0x%0.2x)", u32i, *(pccard_RxBuffer + u32i))); + break; + } + } + } + + /* Write Compact Flash Card Write Sector Without Erase */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_WRITE_SECTOR_WO_ERASE...")); + + if(!PCCARD_Erase_Sector(&pccardHandle, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Erase Secor Failed"); + break; + } + + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); + + if(!PCCARD_Write_Sector_WO_ERASE(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Secor Without Erase Failed"); + break; + } + + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Sector(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Secor Failed"); + break; + } + /* Checking data integrity */ + if(Buffercmp(pccard_TxBuffer, pccard_RxBuffer, PCCARD_SECTOR_SIZE) == PASSED) + { + verification_result.ATA_WRITE_SECTOR_WO_ERASE_PASS = TRUE; + } + else + { + verification_result.ATA_WRITE_SECTOR_WO_ERASE_PASS = FALSE; + } + + /* Format Track */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_FORMAT_TRACK...")); + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); + + if(!PCCARD_Write_Sector(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Secor Failed"); + break; + } + + + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Sector(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Secor Failed"); + break; + } + else + { + verification_result.ATA_FORMAT_TRACK_PASS = TRUE; + + for(u32i = 0; u32i < PCCARD_SECTOR_SIZE; u32i++) + { + if(!(*(pccard_RxBuffer + u32i) == 0xff || *(pccard_RxBuffer + u32i) == 0x0)) + { + verification_result.ATA_FORMAT_TRACK_PASS = FALSE; + CF_print(PRT_ERR_INFO, ("\r\nFormat track error at address offset 0x%0.2x:(0x%0.2x)", u32i, *(pccard_RxBuffer + u32i))); + break; + } + } + } + + /* Read Verify Sector */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_READ_VERIFY_SECTOR...")); + + if(PCCARD_Read_Verify_Sector(&pccardHandle, Start_Sector, 1)) + { + verification_result.ATA_READ_VERIFY_SECTOR_PASS = TRUE; + } + + /* Write verify */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_WRITE_VERIFY...")); + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); // Fill the buffer to write + + if(!PCCARD_Write_Verify(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Verify Failed"); + break; + } + + /* Read Compact Flash Card Sector */ + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Sector(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Secor Failed"); + break; + } + /* Checking data integrity */ + if(Buffercmp(pccard_TxBuffer, pccard_RxBuffer, PCCARD_SECTOR_SIZE) == PASSED) + { + verification_result.ATA_WRITE_VERIFY_PASS = TRUE; + } + else + { + verification_result.ATA_WRITE_VERIFY_PASS = FALSE; + } + + /* Translate Sector */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_TRANSLATE_SECTOR...")); + + if(!PCCARD_Translate_Sector(&pccardHandle, Start_Sector)) + { + printf("\r\nCompact Flash card Translate Sector Failed"); + break; + } + + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Buffer(&pccardHandle, pccard_RxBuffer)) + { + printf("\r\nCompact Flash card Read Buffer Failed"); + break; + } + + if((pccard_RxBuffer[1]) == pccardHandle.CF.CFAddr.Cylinder && + (pccard_RxBuffer[2]) == pccardHandle.CF.CFAddr.Head && + (pccard_RxBuffer[3]) == pccardHandle.CF.CFAddr.Sector) + { + verification_result.ATA_TRANSLATE_SECTOR_PASS = TRUE; + } + + /* Set Multiple Mode */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_SET_MULTIPLE_MODE...")); + PCCARD_Set_Multiple_Mode(&pccardHandle, pccardHandle.CF.CFCardInfo.Max_Mutiple_Sector + 1); + + if(PCCARD_Read_ERROR_REG(&pccardHandle) & ABRT_BIT) + { + verification_result.ATA_SET_MULTIPLE_MODE_PASS = TRUE; + } + + PCCARD_Set_Multiple_Mode(&pccardHandle, pccardHandle.CF.CFCardInfo.Max_Mutiple_Sector); + + if(PCCARD_Read_ERROR_REG(&pccardHandle)) + { + verification_result.ATA_SET_MULTIPLE_MODE_PASS = FALSE; + } + + /* Set Feature */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_SET_FEATURE...")); + + // send a valid feature to CF card, we expect there are no bit will be assert in Error register . + PCCARD_Set_Features(&pccardHandle, 0, NOP); + + if(PCCARD_Read_ERROR_REG(&pccardHandle)) + { + verification_result.ATA_SET_FEATURE_PASS = FALSE; + } + else + { + verification_result.ATA_SET_FEATURE_PASS = TRUE; + } + + /* Write Multiple */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_WRITE_MULTIPLE...")); + /* Note that the maximun number of sectors on Read/Write Multiple command in our CF test card is 1, + so it will work same as Read/Write Sector command. */ + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); // Fill the buffer to write + + if(!PCCARD_Write_Multiple(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Multiple Secors Failed"); + break; + } + + /* Read Multiple */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_READ_MULTIPLE...")); + /* Note that the maximun number of sectors on Read/Write Multiple command in our CF test card is 1, + so it will work same as Read/Write Sector command. */ + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Multiple(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Multiple Secors Failed"); + break; + } + /* Checking data integrity */ + if(Buffercmp(pccard_TxBuffer, pccard_RxBuffer, PCCARD_SECTOR_SIZE) == PASSED) + { + verification_result.ATA_READ_MULTIPLE_PASS = TRUE; + verification_result.ATA_WRITE_MULTIPLE_PASS = TRUE; + } + else + { + verification_result.ATA_READ_MULTIPLE_PASS = FALSE; + verification_result.ATA_WRITE_MULTIPLE_PASS = FALSE; + } + + /* Write Multiple Without Erase */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying CF_ATA_WRITE_MULTIPLE_WO_ERASE...")); + + /* Note that the maximun number of sectors on Read/Write Multiple command in our CF test card is 1, + so it will work same as Read/Write Sector command. */ + if(!PCCARD_Erase_Sector(&pccardHandle, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Erase Secor Failed"); + break; + } + + memset(pccard_TxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_TxBuffer, PCCARD_SECTOR_SIZE, 0x00); + + if(!PCCARD_Write_Multiple_WO_ERASE(&pccardHandle, pccard_TxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Write Multiple Secors Without Erase Failed"); + break; + } + + memset(pccard_RxBuffer, 0, PCCARD_SECTOR_SIZE * sizeof(uint8_t)); + + if(!PCCARD_Read_Multiple(&pccardHandle, pccard_RxBuffer, Start_Sector, 1)) + { + printf("\r\nCompact Flash card Read Multiple Secors Failed"); + break; + } + + if(Buffercmp(pccard_TxBuffer, pccard_RxBuffer, PCCARD_SECTOR_SIZE) == PASSED) // Checking data integrity + { + verification_result.ATA_WRITE_MULTIPLE_WO_ERASE_PASS = TRUE; + } + else + { + verification_result.ATA_WRITE_MULTIPLE_WO_ERASE_PASS = FALSE; + } + + + /* disable the Read/Write Multiple command, we expect Abort bit in Error register will be assert. */ + if(!PCCARD_Set_Multiple_Mode(&pccardHandle, 0)) + { + printf("\r\nSet multiple mode to 0 Failed"); + break; + } + + /* Test Read/Write 50 sectors */ + CF_print(PRT_CMD_INFO, ("\r\nVerifying Test Read/Write 50 sectors...")); + + memset(pccard_25_Sectors_TxBuffer, 0, PCCARD_25_SECTORS_SIZES * sizeof(uint8_t)); + /* Fill the buffer to write */ + Fill_Buffer(pccard_25_Sectors_TxBuffer, PCCARD_25_SECTORS_SIZES, 0x78); + + + + if(!PCCARD_Write_Sector(&pccardHandle, pccard_25_Sectors_TxBuffer, Start_Sector, 25)) + { + printf("\r\nCompact Flash card Write 50 Secors Failed"); + break; + } + + memset(pccard_25_Sectors_RxBuffer, 0, PCCARD_25_SECTORS_SIZES * sizeof(uint8_t)); + + if(!PCCARD_Read_Sector(&pccardHandle, pccard_25_Sectors_RxBuffer, Start_Sector, 25)) + { + printf("\r\nCompact Flash card Read 50 Secors Failed"); + break; + } + /* Checking data integrity */ + if(Buffercmp(pccard_25_Sectors_TxBuffer, pccard_25_Sectors_RxBuffer, PCCARD_25_SECTORS_SIZES) == PASSED) + { + verification_result.ACESS_25_SECTORS_PASS = TRUE; + } + else + { + verification_result.ACESS_25_SECTORS_PASS = FALSE; + } + + /* Show the Compact Flash Storage Card Test results */ + show_verification_result(&verification_result); + + Test_Mode++; + } + + printf("\r\nCompact Flash Storage Card Test End"); + + /* Infinite loop */ + while(1) + { + } + + +} + + +/** + * @brief Fills buffer with user predefined data. + * @param pBuffer: pointer on the buffer to fill + * @param uwBufferLenght: size of the buffer to fill + * @param uwOffset: first value to fill on the buffer + * @retval None + */ +static void Fill_Buffer(uint8_t *pBuffer, uint32_t uwBufferLenght, uint32_t uwOffset) +{ + uint32_t index = 0; + + /* Put in global buffer same values */ + for (index = 0; index < uwBufferLenght; index++ ) + { + pBuffer[index] = index + uwOffset; + } +} + +/** + * @brief Compares two buffers. + * @param pBuffer: pointer to the buffers. + * @param pBuffer1: pointer to the buffers1. + * @param uwBufferLenght: Compared buffer's length + * @retval 1: pBuffer identical to pBuffer1 + * 0: pBuffer differs from pBuffer1 + */ +static TestStatus Buffercmp(uint8_t* pBuffer, uint8_t* pBuffer1, uint32_t uwBufferLenght) +{ + uint32_t counter = 0; + + while(uwBufferLenght--) + { + if(*pBuffer != *pBuffer1) + { + printf("\r\nFormat track error at address offset 0x%0.2x:(0x%0.2x) <-> (0x%0.2x)", counter, *(pBuffer), *(pBuffer1)); + return FAILED; + } + + pBuffer++; + pBuffer1++; + counter++; + } + return PASSED; +} + +/** + * @} + */ + +/** + * @} + */ + diff --git a/project/at_start_f437/examples/xmc/psram/inc/at32f435_437_conf.h b/project/at_start_f437/examples/xmc/psram/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/xmc/psram/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/xmc/psram/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/xmc/psram/mdk_v5/psram.uvoptx b/project/at_start_f437/examples/xmc/psram/mdk_v5/psram.uvoptx index 8ad00b8b..0ae6e8f3 100644 --- a/project/at_start_f437/examples/xmc/psram/mdk_v5/psram.uvoptx +++ b/project/at_start_f437/examples/xmc/psram/mdk_v5/psram.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/xmc/psram/mdk_v5/psram.uvprojx b/project/at_start_f437/examples/xmc/psram/mdk_v5/psram.uvprojx index 43c915dd..c310e07e 100644 --- a/project/at_start_f437/examples/xmc/psram/mdk_v5/psram.uvprojx +++ b/project/at_start_f437/examples/xmc/psram/mdk_v5/psram.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/xmc/psram/src/at32f435_437_clock.c b/project/at_start_f437/examples/xmc/psram/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/xmc/psram/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/xmc/psram/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/xmc/sdram_basic/inc/at32f435_437_conf.h b/project/at_start_f437/examples/xmc/sdram_basic/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/xmc/sdram_basic/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/xmc/sdram_basic/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvoptx b/project/at_start_f437/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvoptx index 0eec8c43..466bba3a 100644 --- a/project/at_start_f437/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvoptx +++ b/project/at_start_f437/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvprojx b/project/at_start_f437/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvprojx index 90c77c2a..dad7c147 100644 --- a/project/at_start_f437/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvprojx +++ b/project/at_start_f437/examples/xmc/sdram_basic/mdk_v5/sdram_basic.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -479,4 +479,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/xmc/sdram_basic/src/at32f435_437_clock.c b/project/at_start_f437/examples/xmc/sdram_basic/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/xmc/sdram_basic/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/xmc/sdram_basic/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/xmc/sdram_dma/inc/at32f435_437_conf.h b/project/at_start_f437/examples/xmc/sdram_dma/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/xmc/sdram_dma/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/xmc/sdram_dma/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvoptx b/project/at_start_f437/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvoptx index f49eccd3..44f1dba3 100644 --- a/project/at_start_f437/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvoptx +++ b/project/at_start_f437/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvprojx b/project/at_start_f437/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvprojx index 916e5e75..797f8f8b 100644 --- a/project/at_start_f437/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvprojx +++ b/project/at_start_f437/examples/xmc/sdram_dma/mdk_v5/sdram_dma.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -484,4 +484,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/project/at_start_f437/examples/xmc/sdram_dma/src/at32f435_437_clock.c b/project/at_start_f437/examples/xmc/sdram_dma/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/xmc/sdram_dma/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/xmc/sdram_dma/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/examples/xmc/sram/inc/at32f435_437_conf.h b/project/at_start_f437/examples/xmc/sram/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/project/at_start_f437/examples/xmc/sram/inc/at32f435_437_conf.h +++ b/project/at_start_f437/examples/xmc/sram/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/examples/xmc/sram/mdk_v5/sram.uvoptx b/project/at_start_f437/examples/xmc/sram/mdk_v5/sram.uvoptx index 0e37644f..e2c137c5 100644 --- a/project/at_start_f437/examples/xmc/sram/mdk_v5/sram.uvoptx +++ b/project/at_start_f437/examples/xmc/sram/mdk_v5/sram.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/examples/xmc/sram/mdk_v5/sram.uvprojx b/project/at_start_f437/examples/xmc/sram/mdk_v5/sram.uvprojx index c8d44ead..ae505b4b 100644 --- a/project/at_start_f437/examples/xmc/sram/mdk_v5/sram.uvprojx +++ b/project/at_start_f437/examples/xmc/sram/mdk_v5/sram.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -483,6 +483,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/examples/xmc/sram/src/at32f435_437_clock.c b/project/at_start_f437/examples/xmc/sram/src/at32f435_437_clock.c index 5fcdf0aa..b9f2063e 100644 --- a/project/at_start_f437/examples/xmc/sram/src/at32f435_437_clock.c +++ b/project/at_start_f437/examples/xmc/sram/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437/templates/inc/at32f435_437_conf.h b/project/at_start_f437/templates/inc/at32f435_437_conf.h index 93748281..8153f3f5 100644 --- a/project/at_start_f437/templates/inc/at32f435_437_conf.h +++ b/project/at_start_f437/templates/inc/at32f435_437_conf.h @@ -55,8 +55,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/project/at_start_f437/templates/mdk_v5/template.uvoptx b/project/at_start_f437/templates/mdk_v5/template.uvoptx index 1f6a74f5..d4966943 100644 --- a/project/at_start_f437/templates/mdk_v5/template.uvoptx +++ b/project/at_start_f437/templates/mdk_v5/template.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/project/at_start_f437/templates/mdk_v5/template.uvprojx b/project/at_start_f437/templates/mdk_v5/template.uvprojx index c5f50e8b..c31bc5a5 100644 --- a/project/at_start_f437/templates/mdk_v5/template.uvprojx +++ b/project/at_start_f437/templates/mdk_v5/template.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -593,6 +593,11 @@ <Project Info> + + + + + 0 1 diff --git a/project/at_start_f437/templates/src/at32f435_437_clock.c b/project/at_start_f437/templates/src/at32f435_437_clock.c index 953a68b5..aaa7e8ef 100644 --- a/project/at_start_f437/templates/src/at32f435_437_clock.c +++ b/project/at_start_f437/templates/src/at32f435_437_clock.c @@ -54,6 +54,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -63,9 +66,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/project/at_start_f437_Example_list.htm b/project/at_start_f437_Example_list.htm index 883023a6..886a8007 100644 --- a/project/at_start_f437_Example_list.htm +++ b/project/at_start_f437_Example_list.htm @@ -13,17 +13,19 @@ {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4;} @font-face - {font-family:Calibri; - panose-1:2 15 5 2 2 2 4 3 2 4;} + {font-family:; + panose-1:2 1 6 0 3 1 1 1 1 1;} @font-face {font-family:; panose-1:2 1 6 9 6 1 1 1 1 1;} @font-face - {font-family:"\@"; - panose-1:2 1 6 9 6 1 1 1 1 1;} + {font-family:"\@";} @font-face {font-family:"\@"; panose-1:2 1 6 0 3 1 1 1 1 1;} +@font-face + {font-family:"\@"; + panose-1:2 1 6 0 3 1 1 1 1 1;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {margin:0cm; @@ -31,9 +33,9 @@ text-align:justify; text-justify:inter-ideograph; font-size:10.5pt; - font-family:"Calibri","sans-serif";} + font-family:;} .MsoChpDefault - {font-family:"Calibri","sans-serif";} + {font-family:;} /* Page Definitions */ @page WordSection1 {size:595.3pt 841.9pt; @@ -378,8 +380,8 @@ div.WordSection1 -

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                                      pc_card

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                                      PC Card洢д

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                                      - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - - - + - - diff --git a/project/at_surf_f437_board/at_surf_f437_board_qspi_flash.c b/project/at_surf_f437_board/at_surf_f437_board_qspi_flash.c index 31653477..83f9682c 100644 --- a/project/at_surf_f437_board/at_surf_f437_board_qspi_flash.c +++ b/project/at_surf_f437_board/at_surf_f437_board_qspi_flash.c @@ -252,19 +252,16 @@ void qspi_flash_data_read(uint32_t addr, uint8_t* buf, uint32_t total_len) */ void qspi_flash_data_write(uint32_t addr, uint8_t* buf, uint32_t total_len) { - uint32_t i, len = total_len; + uint32_t i, len; do { qspi_flash_write_enable(); - if(total_len >= QSPI_FLASH_PAGE_SIZE) - { - len = QSPI_FLASH_PAGE_SIZE; - } - else - { + /* send up to 256 bytes at one time, and only one page */ + len = (addr / QSPI_FLASH_PAGE_SIZE + 1) * QSPI_FLASH_PAGE_SIZE - addr; + if(total_len < len) len = total_len; - } + qspi_flash_cmd_write_config(&qspi_flash_cmd_config, addr, len); qspi_cmd_operation_kick(QSPI_FLASH_QSPIx, &qspi_flash_cmd_config); diff --git a/utilities/at32f435_437_freertos_demo/inc/at32f435_437_conf.h b/utilities/at32f435_437_freertos_demo/inc/at32f435_437_conf.h index 16bb0a03..e95fd305 100644 --- a/utilities/at32f435_437_freertos_demo/inc/at32f435_437_conf.h +++ b/utilities/at32f435_437_freertos_demo/inc/at32f435_437_conf.h @@ -53,8 +53,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f435_437_freertos_demo/mdk_v5/freertos_demo.uvoptx b/utilities/at32f435_437_freertos_demo/mdk_v5/freertos_demo.uvoptx index 70864844..933ff21c 100644 --- a/utilities/at32f435_437_freertos_demo/mdk_v5/freertos_demo.uvoptx +++ b/utilities/at32f435_437_freertos_demo/mdk_v5/freertos_demo.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a**.obj; *.o*.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc*.plm - *.cpp; *.cc; *.cxx + *.cpp0 @@ -22,7 +22,7 @@ - at_start_f435 + at_start_f435_ac5 0x4 ARM-ADS @@ -170,7 +170,289 @@ - at_start_f437 + at_start_f437_ac5 + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 0 + + 0 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + -1 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + at_start_f435_ac6 + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 0 + + 0 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + -1 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + at_start_f437_ac6 0x4 ARM-ADS @@ -352,6 +634,18 @@ 0 0 + + 1 + 4 + 1 + 0 + 0 + 0 + ..\src\include_port.c + include_port.c + 0 + 0 + @@ -362,7 +656,7 @@ 0 2 - 4 + 5 1 0 0 @@ -382,7 +676,7 @@ 0 3 - 5 + 6 1 0 0 @@ -394,7 +688,7 @@ 3 - 6 + 7 1 0 0 @@ -406,7 +700,7 @@ 3 - 7 + 8 1 0 0 @@ -418,7 +712,7 @@ 3 - 8 + 9 1 0 0 @@ -430,7 +724,7 @@ 3 - 9 + 10 1 0 0 @@ -442,7 +736,7 @@ 3 - 10 + 11 1 0 0 @@ -454,7 +748,7 @@ 3 - 11 + 12 1 0 0 @@ -466,7 +760,7 @@ 3 - 12 + 13 1 0 0 @@ -478,7 +772,7 @@ 3 - 13 + 14 1 0 0 @@ -490,7 +784,7 @@ 3 - 14 + 15 1 0 0 @@ -502,7 +796,7 @@ 3 - 15 + 16 1 0 0 @@ -514,7 +808,7 @@ 3 - 16 + 17 1 0 0 @@ -526,7 +820,7 @@ 3 - 17 + 18 1 0 0 @@ -538,7 +832,7 @@ 3 - 18 + 19 1 0 0 @@ -550,7 +844,7 @@ 3 - 19 + 20 1 0 0 @@ -562,7 +856,7 @@ 3 - 20 + 21 1 0 0 @@ -574,7 +868,7 @@ 3 - 21 + 22 1 0 0 @@ -586,7 +880,7 @@ 3 - 22 + 23 1 0 0 @@ -598,7 +892,7 @@ 3 - 23 + 24 1 0 0 @@ -610,7 +904,7 @@ 3 - 24 + 25 1 0 0 @@ -622,7 +916,7 @@ 3 - 25 + 26 1 0 0 @@ -634,7 +928,7 @@ 3 - 26 + 27 1 0 0 @@ -646,7 +940,7 @@ 3 - 27 + 28 1 0 0 @@ -658,7 +952,7 @@ 3 - 28 + 29 1 0 0 @@ -670,7 +964,7 @@ 3 - 29 + 30 1 0 0 @@ -682,7 +976,7 @@ 3 - 30 + 31 1 0 0 @@ -694,7 +988,7 @@ 3 - 31 + 32 1 0 0 @@ -706,7 +1000,7 @@ 3 - 32 + 33 1 0 0 @@ -726,7 +1020,7 @@ 0 4 - 33 + 34 1 0 0 @@ -738,7 +1032,7 @@ 4 - 34 + 35 2 0 0 @@ -758,7 +1052,7 @@ 0 5 - 35 + 36 1 0 0 @@ -770,7 +1064,7 @@ 5 - 36 + 37 1 0 0 @@ -782,7 +1076,7 @@ 5 - 37 + 38 1 0 0 @@ -794,7 +1088,7 @@ 5 - 38 + 39 1 0 0 @@ -806,7 +1100,7 @@ 5 - 39 + 40 1 0 0 @@ -818,7 +1112,7 @@ 5 - 40 + 41 1 0 0 @@ -830,7 +1124,7 @@ 5 - 41 + 42 1 0 0 @@ -842,7 +1136,7 @@ 5 - 42 + 43 1 0 0 @@ -852,18 +1146,6 @@ 0 0 - - 5 - 43 - 1 - 0 - 0 - 0 - ..\..\..\middlewares\freertos\source\portable\rvds\ARM_CM4F\port.c - port.c - 0 - 0 - diff --git a/utilities/at32f435_437_freertos_demo/mdk_v5/freertos_demo.uvprojx b/utilities/at32f435_437_freertos_demo/mdk_v5/freertos_demo.uvprojx index 41a282ec..2fbec029 100644 --- a/utilities/at32f435_437_freertos_demo/mdk_v5/freertos_demo.uvprojx +++ b/utilities/at32f435_437_freertos_demo/mdk_v5/freertos_demo.uvprojx @@ -7,16 +7,16 @@ - at_start_f435 + at_start_f435_ac5 0x4 ARM-ADS - 5060061::V5.06 update 1 (build 61)::ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC 0 -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -48,7 +48,7 @@ 1 .\objects\ - at32f435_freertos + at32f435_freertos_ac5 1 0 1 @@ -327,8 +327,8 @@ 0 0 0 - 1 - 1 + 3 + 3 1 1 0 @@ -397,6 +397,11 @@ 1 ..\src\main.c + + include_port.c + 1 + ..\src\include_port.c + @@ -612,11 +617,6 @@ 1 ..\..\..\middlewares\freertos\source\portable\memmang\heap_4.c - - port.c - 1 - ..\..\..\middlewares\freertos\source\portable\rvds\ARM_CM4F\port.c - @@ -632,16 +632,16 @@ - at_start_f437 + at_start_f437_ac5 0x4 ARM-ADS - 5060061::V5.06 update 1 (build 61)::ARMCC - 8 + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.0.0 + ArteryTek.AT32F435_437_DFP.2.1.0 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -673,7 +673,7 @@ 1 .\objects\ - at32f437_freertos + at32f437_freertos_ac5 1 0 1 @@ -1022,6 +1022,11 @@ 1 ..\src\main.c + + include_port.c + 1 + ..\src\include_port.c + @@ -1237,10 +1242,1255 @@ 1 ..\..\..\middlewares\freertos\source\portable\memmang\heap_4.c + + + + readme + - port.c + readme.txt + 5 + ..\readme.txt + + + + + + + at_start_f435_ac6 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + -AT32F435ZMT7 + ArteryTek + ArteryTek.AT32F435_437_DFP.2.1.0 + IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0AT32F435_4032 -FS08000000 -FL03F0000 -FP0($$Device:-AT32F435ZMT7$Flash\AT32F435_4032.FLM)) + 0 + $$Device:-AT32F435ZMT7$Device\Include\at32f435_437.h + + + + + + + + + + $$Device:-AT32F435ZMT7$SVD\AT32F435xx_v2.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\objects\ + at32f435_freertos_ac6 + 1 + 0 + 1 + 1 + 1 + .\listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x8000000 + 0x3f0000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x3f0000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + AT32F435ZMT7,USE_STDPERIPH_DRIVER,AT_START_F435_V1 + + ..\inc;..\..\..\libraries\drivers\inc;..\..\..\project\at32f435_437_board;..\..\..\libraries\cmsis\cm4\device_support;..\..\..\libraries\cmsis\cm4\core_support;..\..\..\middlewares\freertos\source\include;..\..\..\middlewares\freertos\source\portable\memmang;..\..\..\middlewares\freertos\source\portable\GCC\ARM_CM4F + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + user + + + at32f435_437_clock.c 1 - ..\..\..\middlewares\freertos\source\portable\rvds\ARM_CM4F\port.c + ..\src\at32f435_437_clock.c + + + at32f435_437_int.c + 1 + ..\src\at32f435_437_int.c + + + main.c + 1 + ..\src\main.c + + + include_port.c + 1 + ..\src\include_port.c + + + + + bsp + + + at32f435_437_board.c + 1 + ..\..\..\project\at32f435_437_board\at32f435_437_board.c + + + + + firmware + + + at32f435_437_acc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_acc.c + + + at32f435_437_adc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_adc.c + + + at32f435_437_can.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_can.c + + + at32f435_437_crc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_crc.c + + + at32f435_437_crm.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_crm.c + + + at32f435_437_dac.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_dac.c + + + at32f435_437_debug.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_debug.c + + + at32f435_437_dma.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_dma.c + + + at32f435_437_dvp.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_dvp.c + + + at32f435_437_edma.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_edma.c + + + at32f435_437_emac.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_emac.c + + + at32f435_437_ertc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_ertc.c + + + at32f435_437_exint.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_exint.c + + + at32f435_437_flash.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_flash.c + + + at32f435_437_gpio.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_gpio.c + + + at32f435_437_i2c.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_i2c.c + + + at32f435_437_misc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_misc.c + + + at32f435_437_pwc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_pwc.c + + + at32f435_437_qspi.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_qspi.c + + + at32f435_437_scfg.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_scfg.c + + + at32f435_437_sdio.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_sdio.c + + + at32f435_437_spi.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_spi.c + + + at32f435_437_tmr.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_tmr.c + + + at32f435_437_usart.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_usart.c + + + at32f435_437_usb.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_usb.c + + + at32f435_437_wdt.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_wdt.c + + + at32f435_437_wwdt.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_wwdt.c + + + at32f435_437_xmc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_xmc.c + + + + + cmsis + + + system_at32f435_437.c + 1 + ..\..\..\libraries\cmsis\cm4\device_support\system_at32f435_437.c + + + startup_at32f435_437.s + 2 + ..\..\..\libraries\cmsis\cm4\device_support\startup\mdk\startup_at32f435_437.s + + + + + freertos + + + croutine.c + 1 + ..\..\..\middlewares\freertos\source\croutine.c + + + event_groups.c + 1 + ..\..\..\middlewares\freertos\source\event_groups.c + + + list.c + 1 + ..\..\..\middlewares\freertos\source\list.c + + + queue.c + 1 + ..\..\..\middlewares\freertos\source\queue.c + + + stream_buffer.c + 1 + ..\..\..\middlewares\freertos\source\stream_buffer.c + + + tasks.c + 1 + ..\..\..\middlewares\freertos\source\tasks.c + + + timers.c + 1 + ..\..\..\middlewares\freertos\source\timers.c + + + heap_4.c + 1 + ..\..\..\middlewares\freertos\source\portable\memmang\heap_4.c + + + + + readme + + + readme.txt + 5 + ..\readme.txt + + + + + + + at_start_f437_ac6 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + -AT32F437ZMT7 + ArteryTek + ArteryTek.AT32F435_437_DFP.2.1.0 + IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0AT32F437_4032 -FS08000000 -FL03F0000 -FP0($$Device:-AT32F437ZMT7$Flash\AT32F437_4032.FLM)) + 0 + $$Device:-AT32F437ZMT7$Device\Include\at32f435_437.h + + + + + + + + + + $$Device:-AT32F437ZMT7$SVD\AT32F437xx_v2.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\objects\ + at32f437_freertos_ac6 + 1 + 0 + 1 + 1 + 1 + .\listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x8000000 + 0x3f0000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x3f0000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + AT32F437ZMT7,USE_STDPERIPH_DRIVER,AT_START_F437_V1 + + ..\inc;..\..\..\libraries\drivers\inc;..\..\..\project\at32f435_437_board;..\..\..\libraries\cmsis\cm4\device_support;..\..\..\libraries\cmsis\cm4\core_support;..\..\..\middlewares\freertos\source\include;..\..\..\middlewares\freertos\source\portable\memmang;..\..\..\middlewares\freertos\source\portable\GCC\ARM_CM4F + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + user + + + at32f435_437_clock.c + 1 + ..\src\at32f435_437_clock.c + + + at32f435_437_int.c + 1 + ..\src\at32f435_437_int.c + + + main.c + 1 + ..\src\main.c + + + include_port.c + 1 + ..\src\include_port.c + + + + + bsp + + + at32f435_437_board.c + 1 + ..\..\..\project\at32f435_437_board\at32f435_437_board.c + + + + + firmware + + + at32f435_437_acc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_acc.c + + + at32f435_437_adc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_adc.c + + + at32f435_437_can.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_can.c + + + at32f435_437_crc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_crc.c + + + at32f435_437_crm.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_crm.c + + + at32f435_437_dac.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_dac.c + + + at32f435_437_debug.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_debug.c + + + at32f435_437_dma.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_dma.c + + + at32f435_437_dvp.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_dvp.c + + + at32f435_437_edma.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_edma.c + + + at32f435_437_emac.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_emac.c + + + at32f435_437_ertc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_ertc.c + + + at32f435_437_exint.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_exint.c + + + at32f435_437_flash.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_flash.c + + + at32f435_437_gpio.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_gpio.c + + + at32f435_437_i2c.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_i2c.c + + + at32f435_437_misc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_misc.c + + + at32f435_437_pwc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_pwc.c + + + at32f435_437_qspi.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_qspi.c + + + at32f435_437_scfg.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_scfg.c + + + at32f435_437_sdio.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_sdio.c + + + at32f435_437_spi.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_spi.c + + + at32f435_437_tmr.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_tmr.c + + + at32f435_437_usart.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_usart.c + + + at32f435_437_usb.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_usb.c + + + at32f435_437_wdt.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_wdt.c + + + at32f435_437_wwdt.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_wwdt.c + + + at32f435_437_xmc.c + 1 + ..\..\..\libraries\drivers\src\at32f435_437_xmc.c + + + + + cmsis + + + system_at32f435_437.c + 1 + ..\..\..\libraries\cmsis\cm4\device_support\system_at32f435_437.c + + + startup_at32f435_437.s + 2 + ..\..\..\libraries\cmsis\cm4\device_support\startup\mdk\startup_at32f435_437.s + + + + + freertos + + + croutine.c + 1 + ..\..\..\middlewares\freertos\source\croutine.c + + + event_groups.c + 1 + ..\..\..\middlewares\freertos\source\event_groups.c + + + list.c + 1 + ..\..\..\middlewares\freertos\source\list.c + + + queue.c + 1 + ..\..\..\middlewares\freertos\source\queue.c + + + stream_buffer.c + 1 + ..\..\..\middlewares\freertos\source\stream_buffer.c + + + tasks.c + 1 + ..\..\..\middlewares\freertos\source\tasks.c + + + timers.c + 1 + ..\..\..\middlewares\freertos\source\timers.c + + + heap_4.c + 1 + ..\..\..\middlewares\freertos\source\portable\memmang\heap_4.c @@ -1264,4 +2514,19 @@ + + + + freertos_demo + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f435_437_freertos_demo/src/at32f435_437_clock.c b/utilities/at32f435_437_freertos_demo/src/at32f435_437_clock.c index 01cfc18a..44f42041 100644 --- a/utilities/at32f435_437_freertos_demo/src/at32f435_437_clock.c +++ b/utilities/at32f435_437_freertos_demo/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f435_437_freertos_demo/src/include_port.c b/utilities/at32f435_437_freertos_demo/src/include_port.c new file mode 100644 index 00000000..00c07b29 --- /dev/null +++ b/utilities/at32f435_437_freertos_demo/src/include_port.c @@ -0,0 +1,50 @@ +/** + ************************************************************************** + * @file include_port.c + * @brief include_port program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/** @addtogroup UTILITIES_examples + * @{ + */ + +/** @addtogroup FreeRTOS_demo + * @{ + */ + +/* support ac5 and ac6 compiler */ +#if (__ARMCC_VERSION > 6000000) + +#include "..\..\..\middlewares\freertos\source\portable\GCC\ARM_CM4F\port.c" + +#else + +#include "..\..\..\middlewares\freertos\source\portable\rvds\ARM_CM4F\port.c" + +#endif + +/** + * @} + */ + +/** + * @} + */ diff --git a/utilities/at32f435_437_gen_random_number_demo/inc/at32f435_437_conf.h b/utilities/at32f435_437_gen_random_number_demo/inc/at32f435_437_conf.h index 16bb0a03..e95fd305 100644 --- a/utilities/at32f435_437_gen_random_number_demo/inc/at32f435_437_conf.h +++ b/utilities/at32f435_437_gen_random_number_demo/inc/at32f435_437_conf.h @@ -53,8 +53,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f435_437_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvoptx b/utilities/at32f435_437_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvoptx index 807f8c32..1cd1ea98 100644 --- a/utilities/at32f435_437_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvoptx +++ b/utilities/at32f435_437_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f435_437_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvprojx b/utilities/at32f435_437_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvprojx index ee1e43e5..88f5fc5a 100644 --- a/utilities/at32f435_437_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvprojx +++ b/utilities/at32f435_437_gen_random_number_demo/mdk_v5/gen_ramdom_number.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -958,6 +958,11 @@ <Project Info> + + + + + 0 1 diff --git a/utilities/at32f435_437_gen_random_number_demo/src/at32f435_437_clock.c b/utilities/at32f435_437_gen_random_number_demo/src/at32f435_437_clock.c index 01cfc18a..44f42041 100644 --- a/utilities/at32f435_437_gen_random_number_demo/src/at32f435_437_clock.c +++ b/utilities/at32f435_437_gen_random_number_demo/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f435_437_qspi_algorithm_demo/iar_out/iar_v7.4/qspi_algorithm.eww b/utilities/at32f435_437_qspi_algorithm_demo/iar_out/iar_v7.4/qspi_algorithm.eww index ff0e5984..9e7921c6 100644 --- a/utilities/at32f435_437_qspi_algorithm_demo/iar_out/iar_v7.4/qspi_algorithm.eww +++ b/utilities/at32f435_437_qspi_algorithm_demo/iar_out/iar_v7.4/qspi_algorithm.eww @@ -4,39 +4,6 @@ $WS_DIR$\qspi_algorithm.ewp - - - ALL - - qspi_algorithm - Flash_AT32F435_USD_4KB - - - qspi_algorithm - Flash_AT32F435_USD_512B - - - qspi_algorithm - Flash_AT32F435_1024K - - - qspi_algorithm - Flash_AT32F435_192K - - - qspi_algorithm - Flash_AT32F435_256K - - - qspi_algorithm - Flash_AT32F435_4032K - - - qspi_algorithm - Flash_AT32F435_960K - - - diff --git a/utilities/at32f435_437_qspi_algorithm_demo/iar_out/inc/at32f435_437_conf.h b/utilities/at32f435_437_qspi_algorithm_demo/iar_out/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/utilities/at32f435_437_qspi_algorithm_demo/iar_out/inc/at32f435_437_conf.h +++ b/utilities/at32f435_437_qspi_algorithm_demo/iar_out/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/inc/at32f435_437_conf.h b/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/inc/at32f435_437_conf.h +++ b/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/mdk_v5/qspi_algorithm.FLM b/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/mdk_v5/qspi_algorithm.FLM index 3b52a90f..23cee801 100644 Binary files a/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/mdk_v5/qspi_algorithm.FLM and b/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/mdk_v5/qspi_algorithm.FLM differ diff --git a/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/mdk_v5/qspi_algorithm.uvoptx b/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/mdk_v5/qspi_algorithm.uvoptx index b3a1f252..c7e7cc52 100644 --- a/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/mdk_v5/qspi_algorithm.uvoptx +++ b/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/mdk_v5/qspi_algorithm.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/mdk_v5/qspi_algorithm.uvprojx b/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/mdk_v5/qspi_algorithm.uvprojx index b93f9964..65290f13 100644 --- a/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/mdk_v5/qspi_algorithm.uvprojx +++ b/utilities/at32f435_437_qspi_algorithm_demo/keil_flm/mdk_v5/qspi_algorithm.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -419,4 +419,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f435_437_slib_demo/project_l0/inc/at32f435_437_conf.h b/utilities/at32f435_437_slib_demo/project_l0/inc/at32f435_437_conf.h index 16bb0a03..e95fd305 100644 --- a/utilities/at32f435_437_slib_demo/project_l0/inc/at32f435_437_conf.h +++ b/utilities/at32f435_437_slib_demo/project_l0/inc/at32f435_437_conf.h @@ -53,8 +53,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f435_437_slib_demo/project_l0/mdk_v5/project_l0.uvoptx b/utilities/at32f435_437_slib_demo/project_l0/mdk_v5/project_l0.uvoptx index 65f178d3..2f8ea8e4 100644 --- a/utilities/at32f435_437_slib_demo/project_l0/mdk_v5/project_l0.uvoptx +++ b/utilities/at32f435_437_slib_demo/project_l0/mdk_v5/project_l0.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f435_437_slib_demo/project_l0/mdk_v5/project_l0.uvprojx b/utilities/at32f435_437_slib_demo/project_l0/mdk_v5/project_l0.uvprojx index 3be563a5..07a7ddcb 100644 --- a/utilities/at32f435_437_slib_demo/project_l0/mdk_v5/project_l0.uvprojx +++ b/utilities/at32f435_437_slib_demo/project_l0/mdk_v5/project_l0.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -1310,4 +1310,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f435_437_slib_demo/project_l0/src/at32f435_437_clock.c b/utilities/at32f435_437_slib_demo/project_l0/src/at32f435_437_clock.c index 01cfc18a..44f42041 100644 --- a/utilities/at32f435_437_slib_demo/project_l0/src/at32f435_437_clock.c +++ b/utilities/at32f435_437_slib_demo/project_l0/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f435_437_slib_demo/project_l1/inc/at32f435_437_conf.h b/utilities/at32f435_437_slib_demo/project_l1/inc/at32f435_437_conf.h index 16bb0a03..e95fd305 100644 --- a/utilities/at32f435_437_slib_demo/project_l1/inc/at32f435_437_conf.h +++ b/utilities/at32f435_437_slib_demo/project_l1/inc/at32f435_437_conf.h @@ -53,8 +53,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f435_437_slib_demo/project_l1/mdk_v5/project_l1.uvoptx b/utilities/at32f435_437_slib_demo/project_l1/mdk_v5/project_l1.uvoptx index 91548b85..43da4ced 100644 --- a/utilities/at32f435_437_slib_demo/project_l1/mdk_v5/project_l1.uvoptx +++ b/utilities/at32f435_437_slib_demo/project_l1/mdk_v5/project_l1.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f435_437_slib_demo/project_l1/mdk_v5/project_l1.uvprojx b/utilities/at32f435_437_slib_demo/project_l1/mdk_v5/project_l1.uvprojx index bf56f009..e5670002 100644 --- a/utilities/at32f435_437_slib_demo/project_l1/mdk_v5/project_l1.uvprojx +++ b/utilities/at32f435_437_slib_demo/project_l1/mdk_v5/project_l1.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -974,4 +974,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f435_437_slib_demo/project_l1/src/at32f435_437_clock.c b/utilities/at32f435_437_slib_demo/project_l1/src/at32f435_437_clock.c index 01cfc18a..44f42041 100644 --- a/utilities/at32f435_437_slib_demo/project_l1/src/at32f435_437_clock.c +++ b/utilities/at32f435_437_slib_demo/project_l1/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/inc/at32f435_437_conf.h b/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/inc/at32f435_437_conf.h index 16bb0a03..e95fd305 100644 --- a/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/inc/at32f435_437_conf.h +++ b/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/inc/at32f435_437_conf.h @@ -53,8 +53,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx b/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx index 2984f4ba..6c22391f 100644 --- a/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx +++ b/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx b/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx index 0be712f6..444fb454 100644 --- a/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx +++ b/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -974,4 +974,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/src/at32f435_437_clock.c b/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/src/at32f435_437_clock.c index 01cfc18a..44f42041 100644 --- a/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/src/at32f435_437_clock.c +++ b/utilities/at32f435_437_usart_iap_demo/source_code/app_led3_toggle/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/inc/at32f435_437_conf.h b/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/inc/at32f435_437_conf.h index 16bb0a03..e95fd305 100644 --- a/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/inc/at32f435_437_conf.h +++ b/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/inc/at32f435_437_conf.h @@ -53,8 +53,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx b/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx index 2984f4ba..6c22391f 100644 --- a/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx +++ b/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx b/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx index 7583dfb2..12fda5e5 100644 --- a/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx +++ b/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -974,4 +974,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/src/at32f435_437_clock.c b/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/src/at32f435_437_clock.c index 01cfc18a..44f42041 100644 --- a/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/src/at32f435_437_clock.c +++ b/utilities/at32f435_437_usart_iap_demo/source_code/app_led4_toggle/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/inc/at32f435_437_conf.h b/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/inc/at32f435_437_conf.h index 16bb0a03..e95fd305 100644 --- a/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/inc/at32f435_437_conf.h +++ b/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/inc/at32f435_437_conf.h @@ -53,8 +53,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx b/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx index a8b22c27..5cd8eed5 100644 --- a/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx +++ b/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx b/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx index d36e29bb..a5bdc8f7 100644 --- a/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx +++ b/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -984,4 +984,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/src/at32f435_437_clock.c b/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/src/at32f435_437_clock.c index 01cfc18a..44f42041 100644 --- a/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/src/at32f435_437_clock.c +++ b/utilities/at32f435_437_usart_iap_demo/source_code/bootloader/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f435_437_usart_iap_demo/tool_release/IAP_Programmer.exe b/utilities/at32f435_437_usart_iap_demo/tool_release/IAP_Programmer.exe index bba8fe7d..72860c2a 100644 Binary files a/utilities/at32f435_437_usart_iap_demo/tool_release/IAP_Programmer.exe and b/utilities/at32f435_437_usart_iap_demo/tool_release/IAP_Programmer.exe differ diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/inc/at32f435_437_conf.h b/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/inc/at32f435_437_conf.h +++ b/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/inc/usb_conf.h b/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/inc/usb_conf.h index 989ecd37..7839a7b4 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/inc/usb_conf.h +++ b/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx b/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx index a73f8dec..79705be4 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx +++ b/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx b/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx index 563cf09e..bfaabe53 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx +++ b/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -1054,4 +1054,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/src/at32f435_437_clock.c b/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/src/at32f435_437_clock.c index 5fbe1fe7..7a43eeba 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/src/at32f435_437_clock.c +++ b/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/src/main.c b/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/src/main.c index 02c6414d..f2fe42be 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/src/main.c +++ b/utilities/at32f435_437_usb_iap_demo/source_code/app_led3_toggle/src/main.c @@ -214,7 +214,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/inc/at32f435_437_conf.h b/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/inc/at32f435_437_conf.h +++ b/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/inc/usb_conf.h b/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/inc/usb_conf.h index 631a1b7a..93df3779 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/inc/usb_conf.h +++ b/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx b/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx index a73f8dec..79705be4 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx +++ b/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx b/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx index 1856839f..b8740594 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx +++ b/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/mdk_v5/app_led4_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -1054,4 +1054,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/src/at32f435_437_clock.c b/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/src/at32f435_437_clock.c index 5fbe1fe7..7a43eeba 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/src/at32f435_437_clock.c +++ b/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/src/main.c b/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/src/main.c index 5b20a18c..79dc00cb 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/src/main.c +++ b/utilities/at32f435_437_usb_iap_demo/source_code/app_led4_toggle/src/main.c @@ -214,7 +214,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/inc/at32f435_437_conf.h b/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/inc/at32f435_437_conf.h index bed01414..12638db0 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/inc/at32f435_437_conf.h +++ b/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/inc/at32f435_437_conf.h @@ -46,8 +46,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/inc/usb_conf.h b/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/inc/usb_conf.h index 8cc0ba8f..11ca16fc 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/inc/usb_conf.h +++ b/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/inc/usb_conf.h @@ -116,7 +116,7 @@ extern "C" { #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 #define OTG_PIN_ID GPIO_PINS_12 -#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 #define OTG_PIN_SOF_GPIO GPIOA #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx b/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx index a73f8dec..79705be4 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx +++ b/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx b/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx index 808e3bb7..6dbb90d2 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx +++ b/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx @@ -16,7 +16,7 @@ -AT32F435ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -1054,4 +1054,19 @@ + + + + <Project Info> + + + + + + 0 + 1 + + + + diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/src/at32f435_437_clock.c b/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/src/at32f435_437_clock.c index 5fbe1fe7..7a43eeba 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/src/at32f435_437_clock.c +++ b/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/src/at32f435_437_clock.c @@ -46,6 +46,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -55,9 +58,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/src/main.c b/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/src/main.c index 76816840..28f01466 100644 --- a/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/src/main.c +++ b/utilities/at32f435_437_usb_iap_demo/source_code/bootloader/src/main.c @@ -216,7 +216,7 @@ void usb_gpio_config(void) crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); gpio_init_struct.gpio_pins = OTG_PIN_SOF; gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); #endif /* otgfs use vbus pin */ diff --git a/utilities/at32f435_437_usb_iap_demo/tool_release/IAP_Programmer.exe b/utilities/at32f435_437_usb_iap_demo/tool_release/IAP_Programmer.exe index bba8fe7d..72860c2a 100644 Binary files a/utilities/at32f435_437_usb_iap_demo/tool_release/IAP_Programmer.exe and b/utilities/at32f435_437_usb_iap_demo/tool_release/IAP_Programmer.exe differ diff --git a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.eww b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.eww index 1efb72e9..7b2d3d73 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.eww +++ b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/iar_v8.2/app_led3_toggle.eww @@ -3,17 +3,4 @@ $WS_DIR$\app_led3_toggle.ewp - - - all - - app_led3_toggle - at_start_f403a - - - app_led3_toggle - at_start_f407 - - - diff --git a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/inc/at32f435_437_conf.h b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/inc/at32f435_437_conf.h index 193a8920..9ff97667 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/inc/at32f435_437_conf.h +++ b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/inc/at32f435_437_conf.h @@ -31,8 +31,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/inc/lwipopts.h b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/inc/lwipopts.h index e6303659..5b85d0db 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/inc/lwipopts.h +++ b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/inc/lwipopts.h @@ -101,4 +101,9 @@ /* Check lwip_stats.mem.illegal instead of asserting */ #define LWIP_MEM_ILLEGAL_FREE(msg) /* to nothing */ +/** + * LWIP_NOASSERT: Disable LWIP_ASSERT checks: + */ +#define LWIP_NOASSERT + #endif /* LWIP_HDR_LWIPOPTS_H */ diff --git a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/inc/netconf.h b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/inc/netconf.h index 1f612ad6..fb6ebb05 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/inc/netconf.h +++ b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/inc/netconf.h @@ -36,6 +36,7 @@ void tcpip_stack_init(void); void lwip_pkt_handle(void); void time_update(void); void lwip_periodic_handle(volatile uint32_t localtime); +void lwip_rx_loop_handler(void); #ifdef __cplusplus } diff --git a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx index c336d76b..8796fc36 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx +++ b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx index f521d3a4..f5878b93 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx +++ b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/mdk_v5/app_led3_toggle.uvprojx @@ -16,7 +16,7 @@ -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -728,6 +728,11 @@ <Project Info> + + + + + 0 1 diff --git a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/at32_emac.c b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/at32_emac.c index 53ccad3a..6f5bd24f 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/at32_emac.c +++ b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/at32_emac.c @@ -67,7 +67,7 @@ error_status emac_system_init(void) */ void emac_nvic_configuration(void) { - nvic_irq_enable(EMAC_IRQn, 1, 0); + /* nvic_irq_enable(EMAC_IRQn, 1, 0); */ } /** diff --git a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/at32f435_437_clock.c b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/at32f435_437_clock.c index 630fdbae..8c25d03d 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/at32f435_437_clock.c +++ b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/at32f435_437_clock.c @@ -29,6 +29,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -38,9 +41,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/at32f435_437_int.c b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/at32f435_437_int.c index b6ce599c..ca04c904 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/at32f435_437_int.c +++ b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/at32f435_437_int.c @@ -121,20 +121,3 @@ void TMR6_DAC_GLOBAL_IRQHandler(void) } } -/** - * @brief this function handles emac handler. - * @param none - * @retval none - */ -void EMAC_IRQHandler(void) -{ - /* handles all the received frames */ - while(emac_received_packet_size_get() != 0) - { - lwip_pkt_handle(); - } - - /* clear the emac dma rx it pending bits */ - emac_dma_flag_clear(EMAC_DMA_RI_FLAG); - emac_dma_flag_clear(EMAC_DMA_NIS_FLAG); -} diff --git a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/main.c b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/main.c index f65182f5..77db7da5 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/main.c +++ b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/main.c @@ -53,6 +53,8 @@ int main(void) system_clock_config(); at32_board_init(); + + uart_print_init(115200); /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -72,6 +74,8 @@ int main(void) while(1) { + lwip_rx_loop_handler(); + lwip_periodic_handle(local_time); } } diff --git a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/netconf.c b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/netconf.c index 34f0e0b6..e87a90f2 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/netconf.c +++ b/utilities/at32f437_emac_iap_demo/source_code/app_led3_toggle/src/netconf.c @@ -126,10 +126,18 @@ void tcpip_stack_init(void) void lwip_pkt_handle(void) { /* Read a received packet from the Ethernet buffers and send it to the lwIP for handling */ - if(ethernetif_input(&netif) != ERR_OK) - { - while(1); - } + ethernetif_input(&netif); +} + +/** + * @brief this function is receive handler. + * @param none + * @retval none + */ +void lwip_rx_loop_handler(void) +{ + /* handles all the received frames */ + lwip_pkt_handle(); } /** diff --git a/utilities/at32f437_emac_iap_demo/source_code/bootloader/iar_v8.2/bootloader.eww b/utilities/at32f437_emac_iap_demo/source_code/bootloader/iar_v8.2/bootloader.eww index 4805698d..76adff61 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/bootloader/iar_v8.2/bootloader.eww +++ b/utilities/at32f437_emac_iap_demo/source_code/bootloader/iar_v8.2/bootloader.eww @@ -3,13 +3,4 @@ $WS_DIR$\bootloader.ewp - - - all - - bootloader - bootloader - - - diff --git a/utilities/at32f437_emac_iap_demo/source_code/bootloader/inc/at32f435_437_conf.h b/utilities/at32f437_emac_iap_demo/source_code/bootloader/inc/at32f435_437_conf.h index 193a8920..9ff97667 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/bootloader/inc/at32f435_437_conf.h +++ b/utilities/at32f437_emac_iap_demo/source_code/bootloader/inc/at32f435_437_conf.h @@ -31,8 +31,9 @@ extern "C" { * @brief in the following line adjust the high speed exernal crystal (hext) startup * timeout value */ -#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ #define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */ /* module define -------------------------------------------------------------*/ #define CRM_MODULE_ENABLED diff --git a/utilities/at32f437_emac_iap_demo/source_code/bootloader/inc/lwipopts.h b/utilities/at32f437_emac_iap_demo/source_code/bootloader/inc/lwipopts.h index 666c2b43..6f2b398a 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/bootloader/inc/lwipopts.h +++ b/utilities/at32f437_emac_iap_demo/source_code/bootloader/inc/lwipopts.h @@ -101,4 +101,9 @@ /* Check lwip_stats.mem.illegal instead of asserting */ #define LWIP_MEM_ILLEGAL_FREE(msg) /* to nothing */ +/** + * LWIP_NOASSERT: Disable LWIP_ASSERT checks: + */ +#define LWIP_NOASSERT + #endif /* LWIP_HDR_LWIPOPTS_H */ diff --git a/utilities/at32f437_emac_iap_demo/source_code/bootloader/inc/netconf.h b/utilities/at32f437_emac_iap_demo/source_code/bootloader/inc/netconf.h index 207880a1..fb6ebb05 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/bootloader/inc/netconf.h +++ b/utilities/at32f437_emac_iap_demo/source_code/bootloader/inc/netconf.h @@ -36,7 +36,7 @@ void tcpip_stack_init(void); void lwip_pkt_handle(void); void time_update(void); void lwip_periodic_handle(volatile uint32_t localtime); - +void lwip_rx_loop_handler(void); #ifdef __cplusplus } diff --git a/utilities/at32f437_emac_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx b/utilities/at32f437_emac_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx index 219add8d..4db02827 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx +++ b/utilities/at32f437_emac_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvoptx @@ -10,9 +10,9 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc; *.md + *.txt; *.h; *.inc *.plm - *.cpp; *.cc; *.cxx + *.cpp 0 diff --git a/utilities/at32f437_emac_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx b/utilities/at32f437_emac_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx index 7a23ea2f..07370621 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx +++ b/utilities/at32f437_emac_iap_demo/source_code/bootloader/mdk_v5/bootloader.uvprojx @@ -10,13 +10,13 @@ bootloader 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC 0 -AT32F437ZMT7 ArteryTek - ArteryTek.AT32F435_437_DFP.2.1.0 + ArteryTek.AT32F435_437_DFP.2.0.1 IROM(0x08000000,0x3F0000) IRAM(0x20000000,0x60000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -48,7 +48,7 @@ 1 .\objects\ - telnet + bootloader 1 0 1 @@ -753,6 +753,11 @@ <Project Info> + + + + + 0 1 diff --git a/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/at32_emac.c b/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/at32_emac.c index cb2b9299..b5b53a60 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/at32_emac.c +++ b/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/at32_emac.c @@ -67,7 +67,7 @@ error_status emac_system_init(void) */ void emac_nvic_configuration(void) { - nvic_irq_enable(EMAC_IRQn, 1, 0); + /* nvic_irq_enable(EMAC_IRQn, 1, 0); */ } /** @@ -455,7 +455,6 @@ error_status emac_phy_init(emac_control_config_type *control_para) { return ERROR; } - emac_speed_config(mac_control_para.auto_nego, mac_control_para.duplex_mode, mac_control_para.fast_ethernet_speed); emac_control_config(control_para); return SUCCESS; diff --git a/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/at32f435_437_clock.c b/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/at32f435_437_clock.c index 630fdbae..8c25d03d 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/at32f435_437_clock.c +++ b/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/at32f435_437_clock.c @@ -29,6 +29,9 @@ */ void system_clock_config(void) { + /* reset crm */ + crm_reset(); + /* enable pwc periph clock */ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); @@ -38,9 +41,6 @@ void system_clock_config(void) /* set the flash clock divider */ flash_clock_divider_set(FLASH_CLOCK_DIV_3); - /* reset crm */ - crm_reset(); - crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* wait till hext is ready */ diff --git a/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/at32f435_437_int.c b/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/at32f435_437_int.c index b6ce599c..ca04c904 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/at32f435_437_int.c +++ b/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/at32f435_437_int.c @@ -121,20 +121,3 @@ void TMR6_DAC_GLOBAL_IRQHandler(void) } } -/** - * @brief this function handles emac handler. - * @param none - * @retval none - */ -void EMAC_IRQHandler(void) -{ - /* handles all the received frames */ - while(emac_received_packet_size_get() != 0) - { - lwip_pkt_handle(); - } - - /* clear the emac dma rx it pending bits */ - emac_dma_flag_clear(EMAC_DMA_RI_FLAG); - emac_dma_flag_clear(EMAC_DMA_NIS_FLAG); -} diff --git a/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/main.c b/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/main.c index 4067e14b..a62b93d8 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/main.c +++ b/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/main.c @@ -54,6 +54,8 @@ int main(void) uint32_t useraddr, sector_size; system_clock_config(); at32_board_init(); + + uart_print_init(115200); /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -110,6 +112,8 @@ int main(void) while(1) { + lwip_rx_loop_handler(); + lwip_periodic_handle(local_time); } } diff --git a/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/netconf.c b/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/netconf.c index 00c8a348..df867c2d 100644 --- a/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/netconf.c +++ b/utilities/at32f437_emac_iap_demo/source_code/bootloader/src/netconf.c @@ -128,10 +128,18 @@ void tcpip_stack_init(void) void lwip_pkt_handle(void) { /* Read a received packet from the Ethernet buffers and send it to the lwIP for handling */ - if(ethernetif_input(&netif) != ERR_OK) - { - while(1); - } + ethernetif_input(&netif); +} + +/** + * @brief this function is receive handler. + * @param none + * @retval none + */ +void lwip_rx_loop_handler(void) +{ + /* handles all the received frames */ + lwip_pkt_handle(); } /**
                                      -

                                      +

                                      +

                                      		-

                                      +

                                      Examples

                                      		 -

                                      +

                                      Examples
                                      -

                                      1

                                      +
                                      +

                                      1

                                      		 -

                                      lvgl_music_player

                                      +                                       		+

                                      lvgl_music_player

                                      		 -

                                      +

                                      ֲ
                                      -

                                      2

                                      +
                                      +

                                      2

                                      		 -

                                      audio

                                      +                                       		+

                                      audio

                                      		 -

                                      +

                                      ֲ
                                      -

                                      3

                                      +
                                      +

                                      3

                                      		 -

                                      buzz

                                      +                                       		+

                                      buzz

                                      		 -

                                      +

                                      -

                                      4

                                      +
                                      +

                                      4

                                      		 -

                                      calendar

                                      +                                       		+

                                      calendar

                                      		 -

                                      +

                                      -

                                      5

                                      +
                                      +

                                      5

                                      		 -

                                      camera

                                      +                                       		+

                                      camera

                                      		 -

                                      +

                                      ͷ
                                      -

                                      6

                                      +
                                      +

                                      6

                                      		 -

                                      can

                                      +                                       		+

                                      can

                                      		 -

                                      CAN +

                                      CANͨѶ
                                      -

                                      7

                                      +
                                      +

                                      7

                                      		 -

                                      dac

                                      +                                       		+

                                      dac

                                      		 -

                                      DAC +

                                      DACʹ
                                      -

                                      8

                                      +
                                      +

                                      8

                                      		 -

                                      eeprom

                                      +                                       		+

                                      eeprom

                                      		 -

                                      EEPROM +

                                      EEPROMʹ
                                      -

                                      9

                                      +
                                      +

                                      9

                                      		 -

                                      infrared_receiver

                                      +                                       		+

                                      infrared_receiver

                                      		 -

                                      +

                                      -

                                      10

                                      +
                                      +

                                      10

                                      		 -

                                      joystick

                                      +                                       		+

                                      joystick

                                      		 -

                                      +

                                      Ϸֱ
                                      -

                                      11

                                      +
                                      +

                                      11

                                      		 -

                                      key

                                      +                                       		+

                                      key

                                      		 -

                                      +

                                      -

                                      12

                                      +
                                      +

                                      12

                                      		 -

                                      low_power_mode

                                      +                                       		+

                                      low_power_mode

                                      		 -

                                      +

                                      ͹Ĺ
                                      -

                                      13

                                      +
                                      +

                                      13

                                      		 -

                                      otg

                                      +                                       		+

                                      otg

                                      		 -

                                      USB +

                                      USB⴮
                                      -

                                      14

                                      +
                                      +

                                      14

                                      		 -

                                      pwm_dac

                                      +                                       		+

                                      pwm_dac

                                      		 -

                                      PWM +

                                      PWMģDAC
                                      -

                                      15

                                      +
                                      +

                                      15

                                      		 -

                                      qspi_flash

                                      +                                       		+

                                      qspi_flash

                                      		 -

                                      QSPI FLASH +

                                      QSPI FLASHʹ
                                      -

                                      16

                                      +
                                      +

                                      16

                                      		 -

                                      qspi_sram

                                      +                                       		+

                                      qspi_sram

                                      		 -

                                      QSPI SRAM +

                                      QSPI SRAMʹ
                                      -

                                      17

                                      +
                                      +

                                      17

                                      		 -

                                      rgb_led

                                      +                                       		+

                                      rgb_led

                                      		 -

                                      RGB LED

                                      +                                       		+

                                      RGB LED
                                      -

                                      18

                                      +
                                      +

                                      18

                                      		 -

                                      rs485

                                      +                                       		+

                                      rs485

                                      		 -

                                      RS485 +

                                      RS485ͨѶ
                                      -

                                      19

                                      +
                                      +

                                      19

                                      		 -

                                      sdram

                                      +                                       		+

                                      sdram

                                      		 -

                                      SDRAM +

                                      SDRAMʹ
                                      -

                                      20

                                      +
                                      +

                                      20

                                      		 -

                                      sd_card

                                      +                                       		+

                                      sd_card

                                      		 -

                                      SD +

                                      SDʹ
                                      -

                                      21

                                      +
                                      +

                                      21

                                      		 -

                                      tcp_server

                                      +                                       		+

                                      tcp_server

                                      		 -

                                      TCP +

                                      TCP
                                      -

                                      22

                                      +
                                      +

                                      22

                                      		 -

                                      tft_lcd

                                      +                                       		+

                                      tft_lcd

                                      		 -

                                      +

                                      Һʾʹ
                                      -

                                      23

                                      +
                                      +

                                      23

                                      		 -

                                      touch

                                      +                                       		+

                                      touch

                                      		 -

                                      +

                                      ʹ
                                      -

                                      24

                                      +
                                      +

                                      24

                                      		 -

                                      usart_printf

                                      +                                       		+

                                      usart_printf

                                      		 -

                                      +

                                      ڴӡ
                                      -

                                      25

                                      +
                                      +

                                      25

                                      		 -

                                      variable_resistor

                                      +                                       		+

                                      variable_resistor

                                      		 -

                                      +

                                      ɵ