221 lines
6.4 KiB
C
221 lines
6.4 KiB
C
/**
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**************************************************************************
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* @file at32f435_437_scfg.c
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* @version v2.0.8
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* @date 2022-04-25
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* @brief contains all the functions for the system config firmware library
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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#include "at32f435_437_conf.h"
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/** @addtogroup AT32F435_437_periph_driver
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* @{
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*/
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/** @defgroup SCFG
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* @brief SCFG driver modules
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* @{
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*/
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#ifdef SCFG_MODULE_ENABLED
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/** @defgroup SCFG_private_functions
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* @{
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*/
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/**
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* @brief scfg reset
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* @param none
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* @retval none
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*/
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void scfg_reset(void)
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{
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crm_periph_reset(CRM_SCFG_PERIPH_RESET, TRUE);
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crm_periph_reset(CRM_SCFG_PERIPH_RESET, FALSE);
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}
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/**
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* @brief scfg xmc address mapping swap set
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* @param xmc_swap
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* this parameter can be one of the following values:
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* - SCFG_XMC_SWAP_NONE
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* - SCFG_XMC_SWAP_MODE1
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* - SCFG_XMC_SWAP_MODE2
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* - SCFG_XMC_SWAP_MODE3
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* @retval none
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*/
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void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap)
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{
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SCFG->cfg1_bit.swap_xmc = xmc_swap;
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}
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/**
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* @brief scfg infrared config
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* @param source
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* this parameter can be one of the following values:
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* - SCFG_IR_SOURCE_TMR10
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* - SCFG_IR_SOURCE_USART1
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* - SCFG_IR_SOURCE_USART2
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* @param polarity
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* this parameter can be one of the following values:
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* - SCFG_IR_POLARITY_NO_AFFECTE
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* - SCFG_IR_POLARITY_REVERSE
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* @retval none
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*/
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void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity)
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{
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SCFG->cfg1_bit.ir_src_sel = source;
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SCFG->cfg1_bit.ir_pol = polarity;
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}
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/**
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* @brief scfg memory address mapping set
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* @param mem_map
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* this parameter can be one of the following values:
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* - SCFG_MEM_MAP_MAIN_MEMORY
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* - SCFG_MEM_MAP_BOOT_MEMORY
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* - SCFG_MEM_MAP_XMC_BANK1
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* - SCFG_MEM_MAP_INTERNAL_SRAM
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* - SCFG_MEM_MAP_XMC_SDRAM_BANK1
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* @retval none
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*/
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void scfg_mem_map_set(scfg_mem_map_type mem_map)
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{
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SCFG->cfg1_bit.mem_map_sel = mem_map;
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}
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/**
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* @brief scfg emac interface set
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* @param mode
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* this parameter can be one of the following values:
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* - SCFG_EMAC_SELECT_MII
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* - SCFG_EMAC_SELECT_RMII
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* @retval none
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*/
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void scfg_emac_interface_set(scfg_emac_interface_type mode)
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{
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SCFG->cfg2_bit.mii_rmii_sel = mode;
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}
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/**
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* @brief select the gpio pin used as exint line.
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* @param port_source:
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* select the gpio port to be used as source for exint lines.
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* this parameter can be one of the following values:
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* - SCFG_PORT_SOURCE_GPIOA
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* - SCFG_PORT_SOURCE_GPIOB
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* - SCFG_PORT_SOURCE_GPIOC
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* - SCFG_PORT_SOURCE_GPIOD
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* - SCFG_PORT_SOURCE_GPIOE
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* - SCFG_PORT_SOURCE_GPIOF
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* - SCFG_PORT_SOURCE_GPIOG
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* - SCFG_PORT_SOURCE_GPIOH
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* @param pin_source:
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* specifies the exint line to be configured.
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* this parameter can be one of the following values:
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* - SCFG_PINS_SOURCE0
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* - SCFG_PINS_SOURCE1
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* - SCFG_PINS_SOURCE2
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* - SCFG_PINS_SOURCE3
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* - SCFG_PINS_SOURCE4
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* - SCFG_PINS_SOURCE5
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* - SCFG_PINS_SOURCE6
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* - SCFG_PINS_SOURCE7
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* - SCFG_PINS_SOURCE8
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* - SCFG_PINS_SOURCE9
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* - SCFG_PINS_SOURCE10
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* - SCFG_PINS_SOURCE11
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* - SCFG_PINS_SOURCE12
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* - SCFG_PINS_SOURCE13
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* - SCFG_PINS_SOURCE14
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* - SCFG_PINS_SOURCE15
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* @retval none
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*/
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void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source)
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{
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uint32_t tmp = 0x00;
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tmp = ((uint32_t)0x0F) << (0x04 * (pin_source & (uint8_t)0x03));
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switch (pin_source >> 0x02)
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{
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case 0:
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SCFG->exintc1 &= ~tmp;
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SCFG->exintc1 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
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break;
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case 1:
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SCFG->exintc2 &= ~tmp;
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SCFG->exintc2 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
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break;
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case 2:
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SCFG->exintc3 &= ~tmp;
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SCFG->exintc3 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
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break;
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case 3:
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SCFG->exintc4 &= ~tmp;
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SCFG->exintc4 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
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break;
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default:
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break;
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}
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}
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/**
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* @brief enable or disable gpio pins ultra driven.
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* @param value:
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* this parameter can be one of the following values:
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* - SCFG_ULTRA_DRIVEN_PB3
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* - SCFG_ULTRA_DRIVEN_PB9
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* - SCFG_ULTRA_DRIVEN_PB10
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* - SCFG_ULTRA_DRIVEN_PD12
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* - SCFG_ULTRA_DRIVEN_PD13
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* - SCFG_ULTRA_DRIVEN_PD14
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* - SCFG_ULTRA_DRIVEN_PD15
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* - SCFG_ULTRA_DRIVEN_PF14
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* - SCFG_ULTRA_DRIVEN_PF15
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* @param new_state (TRUE or FALSE)
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* @retval none
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*/
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void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state)
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{
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if(TRUE == new_state)
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{
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SCFG_REG(value) |= SCFG_REG_BIT(value);
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}
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else
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{
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SCFG_REG(value) &= ~(SCFG_REG_BIT(value));
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}
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}
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/**
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* @}
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*/
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#endif
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/**
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* @}
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*/
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/**
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* @}
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*/
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