395 lines
12 KiB
C
395 lines
12 KiB
C
/**
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**************************************************************************
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* @file at32f435_437_dac.h
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* @version v2.0.9
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* @date 2022-06-28
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* @brief at32f435_437 dac header file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F435_437_DAC_H
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#define __AT32F435_437_DAC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "at32f435_437.h"
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/** @addtogroup AT32F435_437_periph_driver
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* @{
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*/
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/** @addtogroup DAC
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* @{
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*/
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#define DAC1_D1DMAUDRF ((uint32_t)(0x00002000))
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#define DAC2_D2DMAUDRF ((uint32_t)(0x20000000))
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/** @defgroup DAC_exported_types
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* @{
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*/
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/**
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* @brief dac select type
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*/
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typedef enum
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{
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DAC1_SELECT = 0x01, /*!< dac1 select */
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DAC2_SELECT = 0x02 /*!< dac2 select */
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} dac_select_type;
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/**
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* @brief dac trigger type
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*/
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typedef enum
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{
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DAC_TMR6_TRGOUT_EVENT = 0x00, /*!< dac trigger selection:timer6 trgout event */
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DAC_TMR8_TRGOUT_EVENT = 0x01, /*!< dac trigger selection:timer8 trgout event */
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DAC_TMR7_TRGOUT_EVENT = 0x02, /*!< dac trigger selection:timer7 trgout event */
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DAC_TMR5_TRGOUT_EVENT = 0x03, /*!< dac trigger selection:timer5 trgout event */
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DAC_TMR2_TRGOUT_EVENT = 0x04, /*!< dac trigger selection:timer2 trgout event */
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DAC_TMR4_TRGOUT_EVENT = 0x05, /*!< dac trigger selection:timer4 trgout event */
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DAC_EXTERNAL_INTERRUPT_LINE_9 = 0x06, /*!< dac trigger selection:external line9 */
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DAC_SOFTWARE_TRIGGER = 0x07 /*!< dac trigger selection:software trigger */
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} dac_trigger_type;
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/**
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* @brief dac wave type
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*/
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typedef enum
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{
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DAC_WAVE_GENERATE_NONE = 0x00, /*!< dac wave generation disabled */
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DAC_WAVE_GENERATE_NOISE = 0x01, /*!< dac noise wave generation enabled */
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DAC_WAVE_GENERATE_TRIANGLE = 0x02 /*!< dac triangle wave generation enabled */
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} dac_wave_type;
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/**
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* @brief dac mask amplitude type
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*/
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typedef enum
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{
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DAC_LSFR_BIT0_AMPLITUDE_1 = 0x00, /*!< unmask bit0/ triangle amplitude equal to 1 */
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DAC_LSFR_BIT10_AMPLITUDE_3 = 0x01, /*!< unmask bit[1:0]/ triangle amplitude equal to 3 */
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DAC_LSFR_BIT20_AMPLITUDE_7 = 0x02, /*!< unmask bit[2:0]/ triangle amplitude equal to 7 */
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DAC_LSFR_BIT30_AMPLITUDE_15 = 0x03, /*!< unmask bit[3:0]/ triangle amplitude equal to 15 */
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DAC_LSFR_BIT40_AMPLITUDE_31 = 0x04, /*!< unmask bit[4:0]/ triangle amplitude equal to 31 */
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DAC_LSFR_BIT50_AMPLITUDE_63 = 0x05, /*!< unmask bit[5:0]/ triangle amplitude equal to 63 */
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DAC_LSFR_BIT60_AMPLITUDE_127 = 0x06, /*!< unmask bit[6:0]/ triangle amplitude equal to 127 */
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DAC_LSFR_BIT70_AMPLITUDE_255 = 0x07, /*!< unmask bit[7:0]/ triangle amplitude equal to 255 */
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DAC_LSFR_BIT80_AMPLITUDE_511 = 0x08, /*!< unmask bit[8:0]/ triangle amplitude equal to 511 */
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DAC_LSFR_BIT90_AMPLITUDE_1023 = 0x09, /*!< unmask bit[9:0]/ triangle amplitude equal to 1023 */
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DAC_LSFR_BITA0_AMPLITUDE_2047 = 0x0A, /*!< unmask bit[10:0]/ triangle amplitude equal to 2047 */
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DAC_LSFR_BITB0_AMPLITUDE_4095 = 0x0B /*!< unmask bit[11:0]/ triangle amplitude equal to 4095 */
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} dac_mask_amplitude_type;
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/**
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* @brief dac1 aligned data type
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*/
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typedef enum
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{
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DAC1_12BIT_RIGHT = 0x40007408, /*!< dac1 12-bit data right-aligned */
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DAC1_12BIT_LEFT = 0x4000740C, /*!< dac1 12-bit data left-aligned */
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DAC1_8BIT_RIGHT = 0x40007410 /*!< dac1 8-bit data right-aligned */
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} dac1_aligned_data_type;
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/**
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* @brief dac2 aligned data type
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*/
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typedef enum
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{
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DAC2_12BIT_RIGHT = 0x40007414, /*!< dac2 12-bit data right-aligned */
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DAC2_12BIT_LEFT = 0x40007418, /*!< dac2 12-bit data left-aligned */
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DAC2_8BIT_RIGHT = 0x4000741C /*!< dac2 8-bit data right-aligned */
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} dac2_aligned_data_type;
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/**
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* @brief dac dual data type
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*/
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typedef enum
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{
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DAC_DUAL_12BIT_RIGHT = 0x40007420, /*!<double dac 12-bit data right-aligned */
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DAC_DUAL_12BIT_LEFT = 0x40007424, /*!<double dac 12-bit data left-aligned */
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DAC_DUAL_8BIT_RIGHT = 0x40007428 /*!<double dac 8-bit data right-aligned */
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} dac_dual_data_type;
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/**
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* @brief type define dac register all
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*/
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typedef struct
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{
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/**
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* @brief dac ctrl register, offset:0x00
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*/
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union
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{
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__IO uint32_t ctrl;
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struct
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{
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__IO uint32_t d1en : 1; /* [0] */
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__IO uint32_t d1obdis : 1; /* [1] */
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__IO uint32_t d1trgen : 1; /* [2] */
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__IO uint32_t d1trgsel : 3; /* [5:3] */
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__IO uint32_t d1nm : 2; /* [7:6] */
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__IO uint32_t d1nbsel : 4; /* [11:8] */
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__IO uint32_t d1dmaen : 1; /* [12] */
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__IO uint32_t d1dmaudrien : 1; /* [13] */
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__IO uint32_t reserved1 : 2; /* [15:14] */
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__IO uint32_t d2en : 1; /* [16] */
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__IO uint32_t d2obdis : 1; /* [17] */
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__IO uint32_t d2trgen : 1; /* [18] */
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__IO uint32_t d2trgsel : 3; /* [21:19] */
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__IO uint32_t d2nm : 2; /* [23:22] */
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__IO uint32_t d2nbsel : 4; /* [27:24] */
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__IO uint32_t d2dmaen : 1; /* [28] */
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__IO uint32_t d2dmaudrien : 1; /* [29] */
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__IO uint32_t reserved2 : 2; /* [31:30] */
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} ctrl_bit;
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};
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/**
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* @brief dac swtrg register, offset:0x04
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*/
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union
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{
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__IO uint32_t swtrg;
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struct
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{
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__IO uint32_t d1swtrg : 1; /* [0] */
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__IO uint32_t d2swtrg : 1; /* [1] */
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__IO uint32_t reserved1 : 30;/* [31:2] */
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} swtrg_bit;
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};
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/**
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* @brief dac d1dth12r register, offset:0x08
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*/
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union
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{
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__IO uint32_t d1dth12r;
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struct
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{
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__IO uint32_t d1dt12r : 12;/* [11:0] */
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__IO uint32_t reserved1 : 20;/* [31:2] */
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} d1dth12r_bit;
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};
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/**
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* @brief dac d1dth12l register, offset:0x0C
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*/
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union
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{
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__IO uint32_t d1dth12l;
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struct
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{
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__IO uint32_t d1dt12l : 12;/* [11:0] */
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__IO uint32_t reserved1 : 20;/* [31:2] */
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} d1dth12l_bit;
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};
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/**
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* @brief dac d1dth8r register, offset:0x10
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*/
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union
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{
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__IO uint32_t d1dth8r;
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struct
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{
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__IO uint32_t d1dt8r : 8; /* [7:0] */
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__IO uint32_t reserved1 : 24;/* [31:8] */
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} d1dth8r_bit;
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};
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/**
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* @brief dac d2dth12r register, offset:0x14
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*/
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union
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{
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__IO uint32_t d2dth12r;
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struct
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{
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__IO uint32_t d2dt12r : 12;/* [11:0] */
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__IO uint32_t reserved1 : 20;/* [31:2] */
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} d2dth12r_bit;
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};
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/**
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* @brief dac d2dth12l register, offset:0x18
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*/
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union
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{
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__IO uint32_t d2dth12l;
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struct
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{
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__IO uint32_t d2dt12l : 12;/* [11:0] */
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__IO uint32_t reserved1 : 20;/* [31:2] */
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} d2dth12l_bit;
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};
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/**
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* @brief dac d2dth8r register, offset:0x1C
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*/
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union
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{
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__IO uint32_t d2dth8r;
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struct
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{
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__IO uint32_t d2dt8r : 8; /* [7:0] */
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__IO uint32_t reserved1 : 24;/* [31:8] */
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} d2dth8r_bit;
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};
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/**
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* @brief dac ddth12r register, offset:0x20
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*/
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union
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{
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__IO uint32_t ddth12r;
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struct
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{
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__IO uint32_t dd1dt12r : 12;/* [11:0] */
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__IO uint32_t reserved1 : 4; /* [15:12] */
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__IO uint32_t dd2dt12r : 12;/* [27:16] */
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__IO uint32_t reserved2 : 4; /* [31:28] */
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} ddth12r_bit;
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};
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/**
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* @brief dac ddth12l register, offset:0x24
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*/
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union
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{
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__IO uint32_t ddth12l;
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struct
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{
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__IO uint32_t reserved1 : 4; /* [3:0] */
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__IO uint32_t dd1dt12l : 12;/* [15:4] */
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__IO uint32_t reserved2 : 4; /* [19:16] */
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__IO uint32_t dd2dt12l : 12;/* [31:20] */
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} ddth12l_bit;
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};
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/**
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* @brief dac ddth8r register, offset:0x28
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*/
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union
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{
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__IO uint32_t ddth8r;
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struct
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{
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__IO uint32_t dd1dt8r : 8; /* [7:0] */
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__IO uint32_t dd2dt8r : 8; /* [15:8] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} ddth8r_bit;
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};
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/**
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* @brief dac d1odt register, offset:0x2c
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*/
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union
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{
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__IO uint32_t d1odt;
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struct
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{
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__IO uint32_t d1odt : 12;/* [11:0] */
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__IO uint32_t reserved1 : 20;/* [31:12] */
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} d1odt_bit;
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};
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/**
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* @brief dac d2odt register, offset:0x30
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*/
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union
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{
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__IO uint32_t d2odt;
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struct
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{
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__IO uint32_t d2odt : 12;/* [11:0] */
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__IO uint32_t reserved1 : 20;/* [31:12] */
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} d2odt_bit;
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};
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/**
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* @brief dac sr register, offset:0x34
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*/
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union
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{
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__IO uint32_t sts;
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struct
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{
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__IO uint32_t reserved1 : 13;/* [12:0] */
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__IO uint32_t d1dmaudrf : 1; /* [13] */
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__IO uint32_t reserved2 : 15;/* [28:14] */
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__IO uint32_t d2dmaudrf : 1; /* [29] */
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__IO uint32_t reserved3 : 2;/* [31:30] */
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} sts_bit;
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};
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} dac_type;
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/**
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* @}
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*/
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#define DAC ((dac_type *) DAC_BASE)
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/** @defgroup DAC_exported_functions
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* @{
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*/
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void dac_reset(void);
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void dac_enable(dac_select_type dac_select, confirm_state new_state);
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void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state);
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void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state);
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void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_source);
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void dac_software_trigger_generate(dac_select_type dac_select);
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void dac_dual_software_trigger_generate(void);
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void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave);
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void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude);
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void dac_dma_enable(dac_select_type dac_select, confirm_state new_state);
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uint16_t dac_data_output_get(dac_select_type dac_select);
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void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data);
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void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data);
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void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2);
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void dac_udr_enable(dac_select_type dac_select, confirm_state new_state);
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flag_status dac_udr_flag_get(dac_select_type dac_select);
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void dac_udr_flag_clear(dac_select_type dac_select);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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