566 lines
23 KiB
C
566 lines
23 KiB
C
/**
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**************************************************************************
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* @file at32f435_437_gpio.h
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* @version v2.0.9
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* @date 2022-06-28
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* @brief at32f435_437 gpio header file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F435_437_GPIO_H
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#define __AT32F435_437_GPIO_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* includes ------------------------------------------------------------------*/
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#include "at32f435_437.h"
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/** @addtogroup AT32F435_437_periph_driver
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* @{
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*/
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/** @addtogroup GPIO
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* @{
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*/
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/** @defgroup GPIO_pins_number_definition
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* @{
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*/
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#define GPIO_PINS_0 0x0001 /*!< gpio pins number 0 */
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#define GPIO_PINS_1 0x0002 /*!< gpio pins number 1 */
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#define GPIO_PINS_2 0x0004 /*!< gpio pins number 2 */
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#define GPIO_PINS_3 0x0008 /*!< gpio pins number 3 */
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#define GPIO_PINS_4 0x0010 /*!< gpio pins number 4 */
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#define GPIO_PINS_5 0x0020 /*!< gpio pins number 5 */
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#define GPIO_PINS_6 0x0040 /*!< gpio pins number 6 */
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#define GPIO_PINS_7 0x0080 /*!< gpio pins number 7 */
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#define GPIO_PINS_8 0x0100 /*!< gpio pins number 8 */
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#define GPIO_PINS_9 0x0200 /*!< gpio pins number 9 */
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#define GPIO_PINS_10 0x0400 /*!< gpio pins number 10 */
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#define GPIO_PINS_11 0x0800 /*!< gpio pins number 11 */
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#define GPIO_PINS_12 0x1000 /*!< gpio pins number 12 */
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#define GPIO_PINS_13 0x2000 /*!< gpio pins number 13 */
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#define GPIO_PINS_14 0x4000 /*!< gpio pins number 14 */
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#define GPIO_PINS_15 0x8000 /*!< gpio pins number 15 */
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#define GPIO_PINS_ALL 0xFFFF /*!< gpio all pins */
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/**
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* @}
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*/
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/** @defgroup GPIO_exported_types
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* @{
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*/
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/**
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* @brief gpio mode select
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*/
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typedef enum
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{
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GPIO_MODE_INPUT = 0x00, /*!< gpio input mode */
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GPIO_MODE_OUTPUT = 0x01, /*!< gpio output mode */
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GPIO_MODE_MUX = 0x02, /*!< gpio mux function mode */
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GPIO_MODE_ANALOG = 0x03 /*!< gpio analog in/out mode */
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} gpio_mode_type;
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/**
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* @brief gpio output drive strength select
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*/
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typedef enum
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{
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GPIO_DRIVE_STRENGTH_STRONGER = 0x01, /*!< stronger sourcing/sinking strength */
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GPIO_DRIVE_STRENGTH_MODERATE = 0x02 /*!< moderate sourcing/sinking strength */
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} gpio_drive_type;
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/**
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* @brief gpio output type
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*/
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typedef enum
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{
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GPIO_OUTPUT_PUSH_PULL = 0x00, /*!< output push-pull */
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GPIO_OUTPUT_OPEN_DRAIN = 0x01 /*!< output open-drain */
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} gpio_output_type;
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/**
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* @brief gpio pull type
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*/
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typedef enum
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{
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GPIO_PULL_NONE = 0x00, /*!< floating for input, no pull for output */
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GPIO_PULL_UP = 0x01, /*!< pull-up */
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GPIO_PULL_DOWN = 0x02 /*!< pull-down */
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} gpio_pull_type;
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/**
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* @brief gpio init type
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*/
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typedef struct
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{
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uint32_t gpio_pins; /*!< pins number selection */
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gpio_output_type gpio_out_type; /*!< output type selection */
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gpio_pull_type gpio_pull; /*!< pull type selection */
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gpio_mode_type gpio_mode; /*!< mode selection */
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gpio_drive_type gpio_drive_strength; /*!< drive strength selection */
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} gpio_init_type;
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/**
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* @brief gpio pins source type
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*/
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typedef enum
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{
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GPIO_PINS_SOURCE0 = 0x00, /*!< gpio pins source number 0 */
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GPIO_PINS_SOURCE1 = 0x01, /*!< gpio pins source number 1 */
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GPIO_PINS_SOURCE2 = 0x02, /*!< gpio pins source number 2 */
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GPIO_PINS_SOURCE3 = 0x03, /*!< gpio pins source number 3 */
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GPIO_PINS_SOURCE4 = 0x04, /*!< gpio pins source number 4 */
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GPIO_PINS_SOURCE5 = 0x05, /*!< gpio pins source number 5 */
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GPIO_PINS_SOURCE6 = 0x06, /*!< gpio pins source number 6 */
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GPIO_PINS_SOURCE7 = 0x07, /*!< gpio pins source number 7 */
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GPIO_PINS_SOURCE8 = 0x08, /*!< gpio pins source number 8 */
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GPIO_PINS_SOURCE9 = 0x09, /*!< gpio pins source number 9 */
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GPIO_PINS_SOURCE10 = 0x0A, /*!< gpio pins source number 10 */
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GPIO_PINS_SOURCE11 = 0x0B, /*!< gpio pins source number 11 */
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GPIO_PINS_SOURCE12 = 0x0C, /*!< gpio pins source number 12 */
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GPIO_PINS_SOURCE13 = 0x0D, /*!< gpio pins source number 13 */
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GPIO_PINS_SOURCE14 = 0x0E, /*!< gpio pins source number 14 */
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GPIO_PINS_SOURCE15 = 0x0F /*!< gpio pins source number 15 */
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} gpio_pins_source_type;
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/**
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* @brief gpio muxing function selection type
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*/
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typedef enum
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{
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GPIO_MUX_0 = 0x00, /*!< gpio muxing function selection 0 */
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GPIO_MUX_1 = 0x01, /*!< gpio muxing function selection 1 */
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GPIO_MUX_2 = 0x02, /*!< gpio muxing function selection 2 */
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GPIO_MUX_3 = 0x03, /*!< gpio muxing function selection 3 */
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GPIO_MUX_4 = 0x04, /*!< gpio muxing function selection 4 */
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GPIO_MUX_5 = 0x05, /*!< gpio muxing function selection 5 */
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GPIO_MUX_6 = 0x06, /*!< gpio muxing function selection 6 */
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GPIO_MUX_7 = 0x07, /*!< gpio muxing function selection 7 */
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GPIO_MUX_8 = 0x08, /*!< gpio muxing function selection 8 */
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GPIO_MUX_9 = 0x09, /*!< gpio muxing function selection 9 */
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GPIO_MUX_10 = 0x0A, /*!< gpio muxing function selection 10 */
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GPIO_MUX_11 = 0x0B, /*!< gpio muxing function selection 11 */
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GPIO_MUX_12 = 0x0C, /*!< gpio muxing function selection 12 */
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GPIO_MUX_13 = 0x0D, /*!< gpio muxing function selection 13 */
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GPIO_MUX_14 = 0x0E, /*!< gpio muxing function selection 14 */
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GPIO_MUX_15 = 0x0F /*!< gpio muxing function selection 15 */
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} gpio_mux_sel_type;
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/**
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* @brief type define gpio register all
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*/
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typedef struct
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{
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/**
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* @brief gpio mode register, offset:0x00
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*/
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union
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{
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__IO uint32_t cfgr;
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struct
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{
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__IO uint32_t iomc0 : 2; /* [1:0] */
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__IO uint32_t iomc1 : 2; /* [3:2] */
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__IO uint32_t iomc2 : 2; /* [5:4] */
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__IO uint32_t iomc3 : 2; /* [7:6] */
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__IO uint32_t iomc4 : 2; /* [9:8] */
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__IO uint32_t iomc5 : 2; /* [11:10] */
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__IO uint32_t iomc6 : 2; /* [13:12] */
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__IO uint32_t iomc7 : 2; /* [15:14] */
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__IO uint32_t iomc8 : 2; /* [17:16] */
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__IO uint32_t iomc9 : 2; /* [19:18] */
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__IO uint32_t iomc10 : 2; /* [21:20] */
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__IO uint32_t iomc11 : 2; /* [23:22] */
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__IO uint32_t iomc12 : 2; /* [25:24] */
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__IO uint32_t iomc13 : 2; /* [27:26] */
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__IO uint32_t iomc14 : 2; /* [29:28] */
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__IO uint32_t iomc15 : 2; /* [31:30] */
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} cfgr_bit;
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};
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/**
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* @brief gpio output type register, offset:0x04
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*/
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union
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{
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__IO uint32_t omode;
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struct
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{
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__IO uint32_t om0 : 1; /* [0] */
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__IO uint32_t om1 : 1; /* [1] */
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__IO uint32_t om2 : 1; /* [2] */
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__IO uint32_t om3 : 1; /* [3] */
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__IO uint32_t om4 : 1; /* [4] */
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__IO uint32_t om5 : 1; /* [5] */
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__IO uint32_t om6 : 1; /* [6] */
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__IO uint32_t om7 : 1; /* [7] */
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__IO uint32_t om8 : 1; /* [8] */
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__IO uint32_t om9 : 1; /* [9] */
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__IO uint32_t om10 : 1; /* [10] */
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__IO uint32_t om11 : 1; /* [11] */
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__IO uint32_t om12 : 1; /* [12] */
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__IO uint32_t om13 : 1; /* [13] */
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__IO uint32_t om14 : 1; /* [14] */
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__IO uint32_t om15 : 1; /* [15] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} omode_bit;
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};
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/**
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* @brief gpio output driver register, offset:0x08
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*/
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union
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{
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__IO uint32_t odrvr;
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struct
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{
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__IO uint32_t odrv0 : 2; /* [1:0] */
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__IO uint32_t odrv1 : 2; /* [3:2] */
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__IO uint32_t odrv2 : 2; /* [5:4] */
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__IO uint32_t odrv3 : 2; /* [7:6] */
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__IO uint32_t odrv4 : 2; /* [9:8] */
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__IO uint32_t odrv5 : 2; /* [11:10] */
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__IO uint32_t odrv6 : 2; /* [13:12] */
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__IO uint32_t odrv7 : 2; /* [15:14] */
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__IO uint32_t odrv8 : 2; /* [17:16] */
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__IO uint32_t odrv9 : 2; /* [19:18] */
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__IO uint32_t odrv10 : 2; /* [21:20] */
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__IO uint32_t odrv11 : 2; /* [23:22] */
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__IO uint32_t odrv12 : 2; /* [25:24] */
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__IO uint32_t odrv13 : 2; /* [27:26] */
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__IO uint32_t odrv14 : 2; /* [29:28] */
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__IO uint32_t odrv15 : 2; /* [31:30] */
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} odrvr_bit;
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};
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/**
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* @brief gpio pull up/down register, offset:0x0C
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*/
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union
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{
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__IO uint32_t pull;
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struct
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{
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__IO uint32_t pull0 : 2; /* [1:0] */
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__IO uint32_t pull1 : 2; /* [3:2] */
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__IO uint32_t pull2 : 2; /* [5:4] */
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__IO uint32_t pull3 : 2; /* [7:6] */
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__IO uint32_t pull4 : 2; /* [9:8] */
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__IO uint32_t pull5 : 2; /* [11:10] */
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__IO uint32_t pull6 : 2; /* [13:12] */
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__IO uint32_t pull7 : 2; /* [15:14] */
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__IO uint32_t pull8 : 2; /* [17:16] */
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__IO uint32_t pull9 : 2; /* [19:18] */
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__IO uint32_t pull10 : 2; /* [21:20] */
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__IO uint32_t pull11 : 2; /* [23:22] */
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__IO uint32_t pull12 : 2; /* [25:24] */
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__IO uint32_t pull13 : 2; /* [27:26] */
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__IO uint32_t pull14 : 2; /* [29:28] */
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__IO uint32_t pull15 : 2; /* [31:30] */
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} pull_bit;
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};
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/**
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* @brief gpio input data register, offset:0x10
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*/
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union
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{
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__IO uint32_t idt;
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struct
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{
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__IO uint32_t idt0 : 1; /* [0] */
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__IO uint32_t idt1 : 1; /* [1] */
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__IO uint32_t idt2 : 1; /* [2] */
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__IO uint32_t idt3 : 1; /* [3] */
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__IO uint32_t idt4 : 1; /* [4] */
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__IO uint32_t idt5 : 1; /* [5] */
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__IO uint32_t idt6 : 1; /* [6] */
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__IO uint32_t idt7 : 1; /* [7] */
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__IO uint32_t idt8 : 1; /* [8] */
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__IO uint32_t idt9 : 1; /* [9] */
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__IO uint32_t idt10 : 1; /* [10] */
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__IO uint32_t idt11 : 1; /* [11] */
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__IO uint32_t idt12 : 1; /* [12] */
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__IO uint32_t idt13 : 1; /* [13] */
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__IO uint32_t idt14 : 1; /* [14] */
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__IO uint32_t idt15 : 1; /* [15] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} idt_bit;
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};
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/**
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* @brief gpio output data register, offset:0x14
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*/
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union
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{
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__IO uint32_t odt;
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struct
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{
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__IO uint32_t odt0 : 1; /* [0] */
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__IO uint32_t odt1 : 1; /* [1] */
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__IO uint32_t odt2 : 1; /* [2] */
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__IO uint32_t odt3 : 1; /* [3] */
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__IO uint32_t odt4 : 1; /* [4] */
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__IO uint32_t odt5 : 1; /* [5] */
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__IO uint32_t odt6 : 1; /* [6] */
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__IO uint32_t odt7 : 1; /* [7] */
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__IO uint32_t odt8 : 1; /* [8] */
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__IO uint32_t odt9 : 1; /* [9] */
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__IO uint32_t odt10 : 1; /* [10] */
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__IO uint32_t odt11 : 1; /* [11] */
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__IO uint32_t odt12 : 1; /* [12] */
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__IO uint32_t odt13 : 1; /* [13] */
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__IO uint32_t odt14 : 1; /* [14] */
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__IO uint32_t odt15 : 1; /* [15] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} odt_bit;
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};
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/**
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* @brief gpio scr register, offset:0x18
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*/
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union
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{
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__IO uint32_t scr;
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struct
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{
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__IO uint32_t iosb0 : 1; /* [0] */
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__IO uint32_t iosb1 : 1; /* [1] */
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__IO uint32_t iosb2 : 1; /* [2] */
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__IO uint32_t iosb3 : 1; /* [3] */
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__IO uint32_t iosb4 : 1; /* [4] */
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__IO uint32_t iosb5 : 1; /* [5] */
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__IO uint32_t iosb6 : 1; /* [6] */
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__IO uint32_t iosb7 : 1; /* [7] */
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__IO uint32_t iosb8 : 1; /* [8] */
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__IO uint32_t iosb9 : 1; /* [9] */
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__IO uint32_t iosb10 : 1; /* [10] */
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__IO uint32_t iosb11 : 1; /* [11] */
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__IO uint32_t iosb12 : 1; /* [12] */
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__IO uint32_t iosb13 : 1; /* [13] */
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__IO uint32_t iosb14 : 1; /* [14] */
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__IO uint32_t iosb15 : 1; /* [15] */
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__IO uint32_t iocb0 : 1; /* [16] */
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__IO uint32_t iocb1 : 1; /* [17] */
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__IO uint32_t iocb2 : 1; /* [18] */
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__IO uint32_t iocb3 : 1; /* [19] */
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__IO uint32_t iocb4 : 1; /* [20] */
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__IO uint32_t iocb5 : 1; /* [21] */
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__IO uint32_t iocb6 : 1; /* [22] */
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__IO uint32_t iocb7 : 1; /* [23] */
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__IO uint32_t iocb8 : 1; /* [24] */
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__IO uint32_t iocb9 : 1; /* [25] */
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__IO uint32_t iocb10 : 1; /* [26] */
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__IO uint32_t iocb11 : 1; /* [27] */
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__IO uint32_t iocb12 : 1; /* [28] */
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__IO uint32_t iocb13 : 1; /* [29] */
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__IO uint32_t iocb14 : 1; /* [30] */
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__IO uint32_t iocb15 : 1; /* [31] */
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} scr_bit;
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};
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/**
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* @brief gpio wpen register, offset:0x1C
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*/
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union
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{
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__IO uint32_t wpr;
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struct
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{
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__IO uint32_t wpen0 : 1; /* [0] */
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__IO uint32_t wpen1 : 1; /* [1] */
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__IO uint32_t wpen2 : 1; /* [2] */
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__IO uint32_t wpen3 : 1; /* [3] */
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__IO uint32_t wpen4 : 1; /* [4] */
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__IO uint32_t wpen5 : 1; /* [5] */
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__IO uint32_t wpen6 : 1; /* [6] */
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__IO uint32_t wpen7 : 1; /* [7] */
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__IO uint32_t wpen8 : 1; /* [8] */
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__IO uint32_t wpen9 : 1; /* [9] */
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__IO uint32_t wpen10 : 1; /* [10] */
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__IO uint32_t wpen11 : 1; /* [11] */
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__IO uint32_t wpen12 : 1; /* [12] */
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__IO uint32_t wpen13 : 1; /* [13] */
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__IO uint32_t wpen14 : 1; /* [14] */
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__IO uint32_t wpen15 : 1; /* [15] */
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__IO uint32_t wpseq : 1; /* [16] */
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__IO uint32_t reserved1 : 15;/* [31:17] */
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} wpr_bit;
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};
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/**
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* @brief gpio muxl register, offset:0x20
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*/
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union
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{
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__IO uint32_t muxl;
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struct
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{
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__IO uint32_t muxl0 : 4; /* [3:0] */
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__IO uint32_t muxl1 : 4; /* [7:4] */
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__IO uint32_t muxl2 : 4; /* [11:8] */
|
|
__IO uint32_t muxl3 : 4; /* [15:12] */
|
|
__IO uint32_t muxl4 : 4; /* [19:16] */
|
|
__IO uint32_t muxl5 : 4; /* [23:20] */
|
|
__IO uint32_t muxl6 : 4; /* [27:24] */
|
|
__IO uint32_t muxl7 : 4; /* [31:28] */
|
|
} muxl_bit;
|
|
};
|
|
|
|
/**
|
|
* @brief gpio muxh register, offset:0x24
|
|
*/
|
|
union
|
|
{
|
|
__IO uint32_t muxh;
|
|
struct
|
|
{
|
|
__IO uint32_t muxh8 : 4; /* [3:0] */
|
|
__IO uint32_t muxh9 : 4; /* [7:4] */
|
|
__IO uint32_t muxh10 : 4; /* [11:8] */
|
|
__IO uint32_t muxh11 : 4; /* [15:12] */
|
|
__IO uint32_t muxh12 : 4; /* [19:16] */
|
|
__IO uint32_t muxh13 : 4; /* [23:20] */
|
|
__IO uint32_t muxh14 : 4; /* [27:24] */
|
|
__IO uint32_t muxh15 : 4; /* [31:28] */
|
|
} muxh_bit;
|
|
};
|
|
|
|
/**
|
|
* @brief gpio clr register, offset:0x28
|
|
*/
|
|
union
|
|
{
|
|
__IO uint32_t clr;
|
|
struct
|
|
{
|
|
__IO uint32_t iocb0 : 1; /* [0] */
|
|
__IO uint32_t iocb1 : 1; /* [1] */
|
|
__IO uint32_t iocb2 : 1; /* [2] */
|
|
__IO uint32_t iocb3 : 1; /* [3] */
|
|
__IO uint32_t iocb4 : 1; /* [4] */
|
|
__IO uint32_t iocb5 : 1; /* [5] */
|
|
__IO uint32_t iocb6 : 1; /* [6] */
|
|
__IO uint32_t iocb7 : 1; /* [7] */
|
|
__IO uint32_t iocb8 : 1; /* [8] */
|
|
__IO uint32_t iocb9 : 1; /* [9] */
|
|
__IO uint32_t iocb10 : 1; /* [10] */
|
|
__IO uint32_t iocb11 : 1; /* [11] */
|
|
__IO uint32_t iocb12 : 1; /* [12] */
|
|
__IO uint32_t iocb13 : 1; /* [13] */
|
|
__IO uint32_t iocb14 : 1; /* [14] */
|
|
__IO uint32_t iocb15 : 1; /* [15] */
|
|
__IO uint32_t reserved1 : 16;/* [31:16] */
|
|
} clr_bit;
|
|
};
|
|
|
|
/**
|
|
* @brief gpio reserved1 register, offset:0x2C~0x38
|
|
*/
|
|
__IO uint32_t reserved1[4];
|
|
|
|
/**
|
|
* @brief gpio hdrv register, offset:0x3C
|
|
*/
|
|
union
|
|
{
|
|
__IO uint32_t hdrv;
|
|
struct
|
|
{
|
|
__IO uint32_t hdrv0 : 1; /* [0] */
|
|
__IO uint32_t hdrv1 : 1; /* [1] */
|
|
__IO uint32_t hdrv2 : 1; /* [2] */
|
|
__IO uint32_t hdrv3 : 1; /* [3] */
|
|
__IO uint32_t hdrv4 : 1; /* [4] */
|
|
__IO uint32_t hdrv5 : 1; /* [5] */
|
|
__IO uint32_t hdrv6 : 1; /* [6] */
|
|
__IO uint32_t hdrv7 : 1; /* [7] */
|
|
__IO uint32_t hdrv8 : 1; /* [8] */
|
|
__IO uint32_t hdrv9 : 1; /* [9] */
|
|
__IO uint32_t hdrv10 : 1; /* [10] */
|
|
__IO uint32_t hdrv11 : 1; /* [11] */
|
|
__IO uint32_t hdrv12 : 1; /* [12] */
|
|
__IO uint32_t hdrv13 : 1; /* [13] */
|
|
__IO uint32_t hdrv14 : 1; /* [14] */
|
|
__IO uint32_t hdrv15 : 1; /* [15] */
|
|
__IO uint32_t reserved1 : 16;/* [31:16] */
|
|
} hdrv_bit;
|
|
};
|
|
|
|
} gpio_type;
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#define GPIOA ((gpio_type *) GPIOA_BASE)
|
|
#define GPIOB ((gpio_type *) GPIOB_BASE)
|
|
#define GPIOC ((gpio_type *) GPIOC_BASE)
|
|
#define GPIOD ((gpio_type *) GPIOD_BASE)
|
|
#define GPIOE ((gpio_type *) GPIOE_BASE)
|
|
#define GPIOF ((gpio_type *) GPIOF_BASE)
|
|
#define GPIOG ((gpio_type *) GPIOG_BASE)
|
|
#define GPIOH ((gpio_type *) GPIOH_BASE)
|
|
|
|
/** @defgroup GPIO_exported_functions
|
|
* @{
|
|
*/
|
|
|
|
void gpio_reset(gpio_type *gpio_x);
|
|
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
|
|
void gpio_default_para_init(gpio_init_type *gpio_init_struct);
|
|
flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
|
|
uint16_t gpio_input_data_read(gpio_type *gpio_x);
|
|
flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
|
|
uint16_t gpio_output_data_read(gpio_type *gpio_x);
|
|
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
|
|
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
|
|
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
|
|
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value);
|
|
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
|
|
void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
|
|
void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif
|