126 lines
4.0 KiB
C
126 lines
4.0 KiB
C
/**
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**************************************************************************
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* @file at32f435_437_misc.h
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* @version v2.0.9
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* @date 2022-06-28
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* @brief at32f435_437 misc header file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F435_437_MISC_H
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#define __AT32F435_437_MISC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* includes ------------------------------------------------------------------*/
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#include "at32f435_437.h"
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/** @addtogroup AT32F435_437_periph_driver
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* @{
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*/
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/** @addtogroup MISC
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* @{
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*/
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/** @defgroup MISC_vector_table_base_address
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* @{
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*/
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#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
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#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
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/**
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* @}
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*/
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/** @defgroup MISC_exported_types
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* @{
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*/
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/**
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* @brief nvic interrupt priority group
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*/
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typedef enum
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{
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NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
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NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
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NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
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NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
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NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
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} nvic_priority_group_type;
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/**
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* @brief nvic low power mode
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*/
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typedef enum
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{
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NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */
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NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
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NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */
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} nvic_lowpower_mode_type;
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/**
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* @brief systick clock source
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*/
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typedef enum
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{
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SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8 = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
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SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV = ((uint32_t)0x00000004) /*!< systick clock source from core clock */
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} systick_clock_source_type;
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/**
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* @}
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*/
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/** @defgroup MISC_exported_functions
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* @{
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*/
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void nvic_system_reset(void);
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void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority);
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void nvic_irq_disable(IRQn_Type irqn);
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void nvic_priority_group_config(nvic_priority_group_type priority_group);
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void nvic_vector_table_set(uint32_t base, uint32_t offset);
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void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
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void systick_clock_source_config(systick_clock_source_type source);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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