324 lines
10 KiB
C
324 lines
10 KiB
C
/**
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**************************************************************************
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* @file at32f435_437_scfg.h
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* @version v2.0.9
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* @date 2022-06-28
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* @brief at32f435_437 system config header file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F435_437_SCFG_H
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#define __AT32F435_437_SCFG_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "at32f435_437.h"
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/** @addtogroup AT32F435_437_periph_driver
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* @{
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*/
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/** @addtogroup SCFG
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* @{
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*/
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#define SCFG_REG(value) PERIPH_REG(SCFG_BASE, value)
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#define SCFG_REG_BIT(value) PERIPH_REG_BIT(value)
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/** @defgroup SCFG_exported_types
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* @{
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*/
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/**
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* @brief scfg xmc addres mapping swap type
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*/
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typedef enum
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{
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SCFG_XMC_SWAP_NONE = 0x00, /* no swap */
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SCFG_XMC_SWAP_MODE1 = 0x01, /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000 */
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SCFG_XMC_SWAP_MODE2 = 0x02, /* qspi2 0x80000000, nand3 0xB0000000 */
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SCFG_XMC_SWAP_MODE3 = 0x03 /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000, qspi2 0x80000000, nand3 0xB0000000 */
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} scfg_xmc_swap_type;
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/**
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* @brief scfg infrared modulation signal source selecting type
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*/
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typedef enum
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{
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SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */
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SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */
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SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */
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} scfg_ir_source_type;
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/**
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* @brief scfg infrared output polarity selecting type
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*/
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typedef enum
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{
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SCFG_IR_POLARITY_NO_AFFECTE = 0x00, /* infrared output polarity no affecte */
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SCFG_IR_POLARITY_REVERSE = 0x01 /* infrared output polarity reverse */
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} scfg_ir_polarity_type;
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/**
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* @brief scfg memory address mapping selecting type
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*/
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typedef enum
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{
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SCFG_MEM_MAP_MAIN_MEMORY = 0x00, /* 0x00000000 address mapping from main memory */
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SCFG_MEM_MAP_BOOT_MEMORY = 0x01, /* 0x00000000 address mapping from boot memory */
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SCFG_MEM_MAP_XMC_BANK1 = 0x02, /* 0x00000000 address mapping from xmc bank1 */
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SCFG_MEM_MAP_INTERNAL_SRAM = 0x03, /* 0x00000000 address mapping from internal sram */
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SCFG_MEM_MAP_XMC_SDRAM_BANK1 = 0x04 /* 0x00000000 address mapping from xmc sdram bank1 */
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} scfg_mem_map_type;
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/**
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* @brief scfg pin source type
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*/
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typedef enum
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{
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SCFG_PINS_SOURCE0 = 0x00,
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SCFG_PINS_SOURCE1 = 0x01,
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SCFG_PINS_SOURCE2 = 0x02,
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SCFG_PINS_SOURCE3 = 0x03,
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SCFG_PINS_SOURCE4 = 0x04,
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SCFG_PINS_SOURCE5 = 0x05,
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SCFG_PINS_SOURCE6 = 0x06,
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SCFG_PINS_SOURCE7 = 0x07,
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SCFG_PINS_SOURCE8 = 0x08,
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SCFG_PINS_SOURCE9 = 0x09,
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SCFG_PINS_SOURCE10 = 0x0A,
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SCFG_PINS_SOURCE11 = 0x0B,
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SCFG_PINS_SOURCE12 = 0x0C,
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SCFG_PINS_SOURCE13 = 0x0D,
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SCFG_PINS_SOURCE14 = 0x0E,
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SCFG_PINS_SOURCE15 = 0x0F
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} scfg_pins_source_type;
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/**
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* @brief gpio port source type
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*/
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typedef enum
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{
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SCFG_PORT_SOURCE_GPIOA = 0x00,
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SCFG_PORT_SOURCE_GPIOB = 0x01,
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SCFG_PORT_SOURCE_GPIOC = 0x02,
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SCFG_PORT_SOURCE_GPIOD = 0x03,
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SCFG_PORT_SOURCE_GPIOE = 0x04,
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SCFG_PORT_SOURCE_GPIOF = 0x05,
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SCFG_PORT_SOURCE_GPIOG = 0x06,
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SCFG_PORT_SOURCE_GPIOH = 0x07
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} scfg_port_source_type;
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/**
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* @brief scfg emac interface selecting type
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*/
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typedef enum
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{
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SCFG_EMAC_SELECT_MII = 0x00, /* emac interface select mii mode */
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SCFG_EMAC_SELECT_RMII = 0x01 /* emac interface select rmii mode */
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} scfg_emac_interface_type;
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/**
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* @brief scfg ultra high sourcing/sinking strength pins type
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*/
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typedef enum
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{
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SCFG_ULTRA_DRIVEN_PB3 = MAKE_VALUE(0x2C, 0),
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SCFG_ULTRA_DRIVEN_PB9 = MAKE_VALUE(0x2C, 1),
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SCFG_ULTRA_DRIVEN_PB10 = MAKE_VALUE(0x2C, 2),
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SCFG_ULTRA_DRIVEN_PD12 = MAKE_VALUE(0x2C, 5),
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SCFG_ULTRA_DRIVEN_PD13 = MAKE_VALUE(0x2C, 6),
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SCFG_ULTRA_DRIVEN_PD14 = MAKE_VALUE(0x2C, 7),
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SCFG_ULTRA_DRIVEN_PD15 = MAKE_VALUE(0x2C, 8),
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SCFG_ULTRA_DRIVEN_PF14 = MAKE_VALUE(0x2C, 9),
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SCFG_ULTRA_DRIVEN_PF15 = MAKE_VALUE(0x2C, 10)
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} scfg_ultra_driven_pins_type;
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/**
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* @brief type define system config register all
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*/
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typedef struct
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{
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/**
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* @brief scfg cfg1 register, offset:0x00
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*/
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union
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{
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__IO uint32_t cfg1;
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struct
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{
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__IO uint32_t mem_map_sel : 3; /* [2:0] */
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__IO uint32_t reserved1 : 2; /* [4:3] */
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__IO uint32_t ir_pol : 1; /* [5] */
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__IO uint32_t ir_src_sel : 2; /* [7:6] */
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__IO uint32_t reserved2 : 2; /* [9:8] */
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__IO uint32_t swap_xmc : 2; /* [11:10] */
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__IO uint32_t reserved3 : 20;/* [31:12] */
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} cfg1_bit;
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};
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/**
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* @brief scfg cfg2 register, offset:0x04
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*/
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union
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{
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__IO uint32_t cfg2;
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struct
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{
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__IO uint32_t reserved1 : 23;/* [22:0] */
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__IO uint32_t mii_rmii_sel : 1; /* [23] */
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__IO uint32_t reserved2 : 8; /* [31:24] */
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} cfg2_bit;
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};
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/**
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* @brief scfg exintc1 register, offset:0x08
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*/
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union
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{
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__IO uint32_t exintc1;
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struct
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{
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__IO uint32_t exint0 : 4; /* [3:0] */
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__IO uint32_t exint1 : 4; /* [7:4] */
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__IO uint32_t exint2 : 4; /* [11:8] */
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__IO uint32_t exint3 : 4; /* [15:12] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} exintc1_bit;
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};
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/**
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* @brief scfg exintc2 register, offset:0x0C
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*/
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union
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{
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__IO uint32_t exintc2;
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struct
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{
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__IO uint32_t exint4 : 4; /* [3:0] */
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__IO uint32_t exint5 : 4; /* [7:4] */
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__IO uint32_t exint6 : 4; /* [11:8] */
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__IO uint32_t exint7 : 4; /* [15:12] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} exintc2_bit;
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};
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/**
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* @brief scfg exintc3 register, offset:0x10
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*/
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union
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{
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__IO uint32_t exintc3;
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struct
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{
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__IO uint32_t exint8 : 4; /* [3:0] */
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__IO uint32_t exint9 : 4; /* [7:4] */
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__IO uint32_t exint10 : 4; /* [11:8] */
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__IO uint32_t exint11 : 4; /* [15:12] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} exintc3_bit;
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};
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/**
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* @brief scfg exintc4 register, offset:0x14
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*/
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union
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{
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__IO uint32_t exintc4;
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struct
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{
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__IO uint32_t exint12 : 4; /* [3:0] */
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__IO uint32_t exint13 : 4; /* [7:4] */
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__IO uint32_t exint14 : 4; /* [11:8] */
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__IO uint32_t exint15 : 4; /* [15:12] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} exintc4_bit;
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};
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/**
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* @brief crm reserved1 register, offset:0x18~0x28
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*/
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__IO uint32_t reserved1[5];
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/**
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* @brief scfg uhdrv register, offset:0x2C
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*/
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union
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{
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__IO uint32_t uhdrv;
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struct
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{
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__IO uint32_t pb3_uh : 1; /* [0] */
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__IO uint32_t pb9_uh : 1; /* [1] */
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__IO uint32_t pb10_uh : 1; /* [2] */
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__IO uint32_t reserved1 : 2; /* [4:3] */
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__IO uint32_t pd12_uh : 1; /* [5] */
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__IO uint32_t pd13_uh : 1; /* [6] */
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__IO uint32_t pd14_uh : 1; /* [7] */
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__IO uint32_t pd15_uh : 1; /* [8] */
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__IO uint32_t pf14_uh : 1; /* [9] */
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__IO uint32_t pf15_uh : 1; /* [10] */
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__IO uint32_t reserved2 : 21;/* [31:11] */
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} uhdrv_bit;
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};
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} scfg_type;
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/**
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* @}
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*/
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#define SCFG ((scfg_type *) SCFG_BASE)
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/** @defgroup SCFG_exported_functions
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* @{
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*/
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void scfg_reset(void);
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void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap);
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void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity);
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void scfg_mem_map_set(scfg_mem_map_type mem_map);
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void scfg_emac_interface_set(scfg_emac_interface_type mode);
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void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source);
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void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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