625 lines
23 KiB
C
625 lines
23 KiB
C
/**
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**************************************************************************
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* @file at32f435_437_sdio.h
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* @version v2.0.9
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* @date 2022-06-28
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* @brief at32f435_437 sdio header file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F435_437_SDIO_H
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#define __AT32F435_437_SDIO_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* includes ------------------------------------------------------------------*/
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#include "at32f435_437.h"
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/** @addtogroup AT32F435_437_periph_driver
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* @{
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*/
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/** @addtogroup SDIO
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* @{
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*/
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/** @defgroup SDIO_interrupts_definition
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* @brief sdio interrupt
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* @{
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*/
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#define SDIO_CMDFAIL_INT ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
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#define SDIO_DTFAIL_INT ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
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#define SDIO_CMDTIMEOUT_INT ((uint32_t)0x00000004) /*!< command response timerout interrupt */
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#define SDIO_DTTIMEOUT_INT ((uint32_t)0x00000008) /*!< data timeout interrupt */
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#define SDIO_TXERRU_INT ((uint32_t)0x00000010) /*!< transmit underrun error interrupt */
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#define SDIO_RXERRO_INT ((uint32_t)0x00000020) /*!< received overrun error interrupt */
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#define SDIO_CMDRSPCMPL_INT ((uint32_t)0x00000040) /*!< command response received interrupt */
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#define SDIO_CMDCMPL_INT ((uint32_t)0x00000080) /*!< command sent interrupt */
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#define SDIO_DTCMP_INT ((uint32_t)0x00000100) /*!< data sent interrupt */
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#define SDIO_SBITERR_INT ((uint32_t)0x00000200) /*!< start bit not detected on data bus interrupt */
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#define SDIO_DTBLKCMPL_INT ((uint32_t)0x00000400) /*!< data block sent/received interrupt */
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#define SDIO_DOCMD_INT ((uint32_t)0x00000800) /*!< command transfer in progress interrupt */
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#define SDIO_DOTX_INT ((uint32_t)0x00001000) /*!< data transmit in progress interrupt */
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#define SDIO_DORX_INT ((uint32_t)0x00002000) /*!< data receive in progress interrupt */
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#define SDIO_TXBUFH_INT ((uint32_t)0x00004000) /*!< transmit buf half empty interrupt */
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#define SDIO_RXBUFH_INT ((uint32_t)0x00008000) /*!< receive buf half full interrupt */
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#define SDIO_TXBUFF_INT ((uint32_t)0x00010000) /*!< transmit buf full interrupt */
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#define SDIO_RXBUFF_INT ((uint32_t)0x00020000) /*!< receive buf full interrupt */
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#define SDIO_TXBUFE_INT ((uint32_t)0x00040000) /*!< transmit buf empty interrupt */
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#define SDIO_RXBUFE_INT ((uint32_t)0x00080000) /*!< receive buf empty interrupt */
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#define SDIO_TXBUF_INT ((uint32_t)0x00100000) /*!< data available in transmit interrupt */
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#define SDIO_RXBUF_INT ((uint32_t)0x00200000) /*!< data available in receive interrupt */
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#define SDIO_SDIOIF_INT ((uint32_t)0x00400000) /*!< sdio interface received interrupt */
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/**
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* @}
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*/
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/** @defgroup SDIO_flags_definition
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* @brief sdio flag
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* @{
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*/
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#define SDIO_CMDFAIL_FLAG ((uint32_t)0x00000001) /*!< command response received check failed flag */
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#define SDIO_DTFAIL_FLAG ((uint32_t)0x00000002) /*!< data block sent/received check failed flag */
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#define SDIO_CMDTIMEOUT_FLAG ((uint32_t)0x00000004) /*!< command response timerout flag */
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#define SDIO_DTTIMEOUT_FLAG ((uint32_t)0x00000008) /*!< data timeout flag */
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#define SDIO_TXERRU_FLAG ((uint32_t)0x00000010) /*!< transmit underrun error flag */
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#define SDIO_RXERRO_FLAG ((uint32_t)0x00000020) /*!< received overrun error flag */
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#define SDIO_CMDRSPCMPL_FLAG ((uint32_t)0x00000040) /*!< command response received flag */
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#define SDIO_CMDCMPL_FLAG ((uint32_t)0x00000080) /*!< command sent flag */
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#define SDIO_DTCMPL_FLAG ((uint32_t)0x00000100) /*!< data sent flag */
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#define SDIO_SBITERR_FLAG ((uint32_t)0x00000200) /*!< start bit not detected on data bus flag */
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#define SDIO_DTBLKCMPL_FLAG ((uint32_t)0x00000400) /*!< data block sent/received flag */
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#define SDIO_DOCMD_FLAG ((uint32_t)0x00000800) /*!< command transfer in progress flag */
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#define SDIO_DOTX_FLAG ((uint32_t)0x00001000) /*!< data transmit in progress flag */
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#define SDIO_DORX_FLAG ((uint32_t)0x00002000) /*!< data receive in progress flag */
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#define SDIO_TXBUFH_FLAG ((uint32_t)0x00004000) /*!< transmit buf half empty flag */
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#define SDIO_RXBUFH_FLAG ((uint32_t)0x00008000) /*!< receive buf half full flag */
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#define SDIO_TXBUFF_FLAG ((uint32_t)0x00010000) /*!< transmit buf full flag */
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#define SDIO_RXBUFF_FLAG ((uint32_t)0x00020000) /*!< receive buf full flag */
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#define SDIO_TXBUFE_FLAG ((uint32_t)0x00040000) /*!< transmit buf empty flag */
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#define SDIO_RXBUFE_FLAG ((uint32_t)0x00080000) /*!< receive buf empty flag */
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#define SDIO_TXBUF_FLAG ((uint32_t)0x00100000) /*!< data available in transmit flag */
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#define SDIO_RXBUF_FLAG ((uint32_t)0x00200000) /*!< data available in receive flag */
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#define SDIO_SDIOIF_FLAG ((uint32_t)0x00400000) /*!< sdio interface received flag */
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/**
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* @}
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*/
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/** @defgroup SDIO_exported_types
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* @{
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*/
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/**
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* @brief sdio power state
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*/
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typedef enum
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{
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SDIO_POWER_OFF = 0x00, /*!< power-off, clock to card is stopped */
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SDIO_POWER_ON = 0x03 /*!< power-on, the card is clocked */
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} sdio_power_state_type;
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/**
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* @brief sdio edge phase
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*/
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typedef enum
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{
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SDIO_CLOCK_EDGE_RISING = 0x00, /*!< sdio bus clock generated on the rising edge of the master clock */
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SDIO_CLOCK_EDGE_FALLING = 0x01 /*!< sdio bus clock generated on the falling edge of the master clock */
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} sdio_edge_phase_type;
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/**
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* @brief sdio bus width
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*/
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typedef enum
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{
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SDIO_BUS_WIDTH_D1 = 0x00, /*!< sdio wide bus select 1-bit */
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SDIO_BUS_WIDTH_D4 = 0x01, /*!< sdio wide bus select 4-bit */
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SDIO_BUS_WIDTH_D8 = 0x02 /*!< sdio wide bus select 8-bit */
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} sdio_bus_width_type;
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/**
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* @brief sdio response type
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*/
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typedef enum
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{
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SDIO_RESPONSE_NO = 0x00, /*!< no response */
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SDIO_RESPONSE_SHORT = 0x01, /*!< short response */
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SDIO_RESPONSE_LONG = 0x03 /*!< long response */
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} sdio_reponse_type;
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/**
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* @brief sdio wait type
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*/
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typedef enum
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{
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SDIO_WAIT_FOR_NO = 0x00, /*!< no wait */
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SDIO_WAIT_FOR_INT = 0x01, /*!< wait interrupt request */
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SDIO_WAIT_FOR_PEND = 0x02 /*!< wait end of transfer */
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} sdio_wait_type;
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/**
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* @brief sdio response register index
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*/
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typedef enum
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{
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SDIO_RSP1_INDEX = 0x00, /*!< response index 1, corresponding to sdio_rsp register 1 */
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SDIO_RSP2_INDEX = 0x01, /*!< response index 2, corresponding to sdio_rsp register 2 */
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SDIO_RSP3_INDEX = 0x02, /*!< response index 3, corresponding to sdio_rsp register 3 */
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SDIO_RSP4_INDEX = 0x03 /*!< response index 4, corresponding to sdio_rsp register 4 */
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} sdio_rsp_index_type;
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/**
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* @brief sdio data block size
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*/
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typedef enum
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{
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SDIO_DATA_BLOCK_SIZE_1B = 0x00, /*!< data block size 1 byte */
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SDIO_DATA_BLOCK_SIZE_2B = 0x01, /*!< data block size 2 bytes */
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SDIO_DATA_BLOCK_SIZE_4B = 0x02, /*!< data block size 4 bytes */
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SDIO_DATA_BLOCK_SIZE_8B = 0x03, /*!< data block size 8 bytes */
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SDIO_DATA_BLOCK_SIZE_16B = 0x04, /*!< data block size 16 bytes */
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SDIO_DATA_BLOCK_SIZE_32B = 0x05, /*!< data block size 32 bytes */
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SDIO_DATA_BLOCK_SIZE_64B = 0x06, /*!< data block size 64 bytes */
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SDIO_DATA_BLOCK_SIZE_128B = 0x07, /*!< data block size 128 bytes */
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SDIO_DATA_BLOCK_SIZE_256B = 0x08, /*!< data block size 256 bytes */
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SDIO_DATA_BLOCK_SIZE_512B = 0x09, /*!< data block size 512 bytes */
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SDIO_DATA_BLOCK_SIZE_1024B = 0x0A, /*!< data block size 1024 bytes */
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SDIO_DATA_BLOCK_SIZE_2048B = 0x0B, /*!< data block size 2048 bytes */
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SDIO_DATA_BLOCK_SIZE_4096B = 0x0C, /*!< data block size 4096 bytes */
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SDIO_DATA_BLOCK_SIZE_8192B = 0x0D, /*!< data block size 8192 bytes */
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SDIO_DATA_BLOCK_SIZE_16384B = 0x0E /*!< data block size 16384 bytes */
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} sdio_block_size_type;
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/**
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* @brief sdio data transfer mode
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*/
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typedef enum
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{
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SDIO_DATA_BLOCK_TRANSFER = 0x00, /*!< the sdio block transfer mode */
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SDIO_DATA_STREAM_TRANSFER = 0x01 /*!< the sdio stream transfer mode */
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} sdio_transfer_mode_type;
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/**
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* @brief sdio data transfer direction
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*/
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typedef enum
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{
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SDIO_DATA_TRANSFER_TO_CARD = 0x00, /*!< the sdio controller write */
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SDIO_DATA_TRANSFER_TO_CONTROLLER = 0x01 /*!< the sdio controller read */
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} sdio_transfer_direction_type;
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/**
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* @brief sdio read wait mode
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*/
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typedef enum
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{
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SDIO_READ_WAIT_CONTROLLED_BY_D2 = 0x00, /*!< the sdio read wait on data2 line */
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SDIO_READ_WAIT_CONTROLLED_BY_CK = 0x01 /*!< the sdio read wait on clock line */
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} sdio_read_wait_mode_type;
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/**
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* @brief sdio command structure
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*/
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typedef struct
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{
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uint32_t argument; /*!< the sdio command argument is sent to a card as part of command message */
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uint8_t cmd_index; /*!< the sdio command index */
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sdio_reponse_type rsp_type; /*!< the sdio response type */
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sdio_wait_type wait_type; /*!< the sdio wait for interrupt request is enabled or disable */
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} sdio_command_struct_type;
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/**
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* @brief sdio data structure
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*/
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typedef struct
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{
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uint32_t timeout; /*!< the sdio data timeout period in car bus clock periods */
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uint32_t data_length; /*!< the sdio data length */
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sdio_block_size_type block_size; /*!< the sdio data block size of block transfer mode */
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sdio_transfer_mode_type transfer_mode; /*!< the sdio transfer mode, block or stream */
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sdio_transfer_direction_type transfer_direction; /*!< the sdio data transfer direction */
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} sdio_data_struct_type;
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/**
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* @brief type define sdio register all
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*/
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typedef struct
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{
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/**
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* @brief sdio pwrctrl register, offset:0x00
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*/
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union
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{
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__IO uint32_t pwrctrl;
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struct
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{
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__IO uint32_t ps : 2; /* [1:0] */
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__IO uint32_t reserved1 : 30;/* [31:2] */
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} pwrctrl_bit;
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};
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/**
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* @brief sdio clkctrl register, offset:0x04
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*/
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union
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{
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__IO uint32_t clkctrl;
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struct
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{
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__IO uint32_t clkdiv_l : 8; /* [7:0] */
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__IO uint32_t clkoen : 1; /* [8] */
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__IO uint32_t pwrsven : 1; /* [9] */
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__IO uint32_t bypsen : 1; /* [10] */
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__IO uint32_t busws : 2; /* [12:11] */
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__IO uint32_t clkegs : 1; /* [13] */
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__IO uint32_t hfcen : 1; /* [14] */
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__IO uint32_t clkdiv_h : 2; /* [16:15] */
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__IO uint32_t reserved1 : 15;/* [31:17] */
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} clkctrl_bit;
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};
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/**
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* @brief sdio argu register, offset:0x08
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*/
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union
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{
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__IO uint32_t argu;
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struct
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{
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__IO uint32_t argu : 32;/* [31:0] */
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} argu_bit;
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};
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/**
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* @brief sdio cmdctrl register, offset:0x0C
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*/
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union
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{
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__IO uint32_t cmdctrl;
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struct
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{
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__IO uint32_t cmdidx : 6; /* [5:0] */
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__IO uint32_t rspwt : 2; /* [7:6] */
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__IO uint32_t intwt : 1; /* [8] */
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__IO uint32_t pndwt : 1; /* [9] */
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__IO uint32_t ccsmen : 1; /* [10] */
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__IO uint32_t iosusp : 1; /* [11] */
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__IO uint32_t reserved1 : 20;/* [31:12] */
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} cmdctrl_bit;
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};
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/**
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* @brief sdio rspcmd register, offset:0x10
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*/
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union
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{
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__IO uint32_t rspcmd;
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struct
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{
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__IO uint32_t rspcmd : 6; /* [5:0] */
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__IO uint32_t reserved1 : 26;/* [31:6] */
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} rspcmd_bit;
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};
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/**
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* @brief sdio rsp1 register, offset:0x14
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*/
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union
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{
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__IO uint32_t rsp1;
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struct
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{
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__IO uint32_t cardsts1 : 32;/* [31:0] */
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} rsp1_bit;
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};
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/**
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* @brief sdio rsp2 register, offset:0x18
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*/
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union
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{
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__IO uint32_t rsp2;
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struct
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{
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__IO uint32_t cardsts2 : 32;/* [31:0] */
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} rsp2_bit;
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};
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/**
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* @brief sdio rsp3 register, offset:0x1C
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*/
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union
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{
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__IO uint32_t rsp3;
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struct
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{
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__IO uint32_t cardsts3 : 32;/* [31:0] */
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} rsp3_bit;
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};
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/**
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* @brief sdio rsp4 register, offset:0x20
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*/
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union
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{
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__IO uint32_t rsp4;
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struct
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{
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__IO uint32_t cardsts4 : 32;/* [31:0] */
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} rsp4_bit;
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};
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/**
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* @brief sdio dttmr register, offset:0x24
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*/
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union
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{
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__IO uint32_t dttmr;
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struct
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{
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__IO uint32_t timeout : 32;/* [31:0] */
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} dttmr_bit;
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};
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/**
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* @brief sdio dtlen register, offset:0x28
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*/
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union
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{
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__IO uint32_t dtlen;
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struct
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{
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__IO uint32_t dtlen : 25;/* [24:0] */
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__IO uint32_t reserved1 : 7; /* [31:25] */
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} dtlen_bit;
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};
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/**
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* @brief sdio dtctrl register, offset:0x2C
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*/
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union
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{
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__IO uint32_t dtctrl;
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struct
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{
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__IO uint32_t tfren : 1; /* [0] */
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__IO uint32_t tfrdir : 1; /* [1] */
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__IO uint32_t tfrmode : 1; /* [2] */
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__IO uint32_t dmaen : 1; /* [3] */
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__IO uint32_t blksize : 4; /* [7:4] */
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__IO uint32_t rdwtstart : 1; /* [8] */
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__IO uint32_t rdwtstop : 1; /* [9] */
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__IO uint32_t rdwtmode : 1; /* [10] */
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__IO uint32_t ioen : 1; /* [11] */
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__IO uint32_t reserved1 : 20;/* [31:12] */
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} dtctrl_bit;
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};
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/**
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* @brief sdio dtcnt register, offset:0x30
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*/
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union
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{
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__IO uint32_t dtcnt;
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struct
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{
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__IO uint32_t cnt : 25;/* [24:0] */
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__IO uint32_t reserved1 : 7; /* [31:25] */
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} dtcnt_bit;
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};
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/**
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* @brief sdio sts register, offset:0x34
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*/
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union
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{
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__IO uint32_t sts;
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struct
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{
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__IO uint32_t cmdfail : 1; /* [0] */
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__IO uint32_t dtfail : 1; /* [1] */
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__IO uint32_t cmdtimeout : 1; /* [2] */
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__IO uint32_t dttimeout : 1; /* [3] */
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__IO uint32_t txerru : 1; /* [4] */
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__IO uint32_t rxerro : 1; /* [5] */
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__IO uint32_t cmdrspcmpl : 1; /* [6] */
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__IO uint32_t cmdcmpl : 1; /* [7] */
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__IO uint32_t dtcmpl : 1; /* [8] */
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__IO uint32_t sbiterr : 1; /* [9] */
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__IO uint32_t dtblkcmpl : 1; /* [10] */
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__IO uint32_t docmd : 1; /* [11] */
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__IO uint32_t dotx : 1; /* [12] */
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__IO uint32_t dorx : 1; /* [13] */
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__IO uint32_t txbufh : 1; /* [14] */
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__IO uint32_t rxbufh : 1; /* [15] */
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|
__IO uint32_t txbuff : 1; /* [16] */
|
|
__IO uint32_t rxbuff : 1; /* [17] */
|
|
__IO uint32_t txbufe : 1; /* [18] */
|
|
__IO uint32_t rxbufe : 1; /* [19] */
|
|
__IO uint32_t txbuf : 1; /* [20] */
|
|
__IO uint32_t rxbuf : 1; /* [21] */
|
|
__IO uint32_t ioif : 1; /* [22] */
|
|
__IO uint32_t reserved1 : 9; /* [31:23] */
|
|
} sts_bit;
|
|
};
|
|
|
|
/**
|
|
* @brief sdio intclr register, offset:0x38
|
|
*/
|
|
union
|
|
{
|
|
__IO uint32_t intclr;
|
|
struct
|
|
{
|
|
__IO uint32_t cmdfail : 1; /* [0] */
|
|
__IO uint32_t dtfail : 1; /* [1] */
|
|
__IO uint32_t cmdtimeout : 1; /* [2] */
|
|
__IO uint32_t dttimeout : 1; /* [3] */
|
|
__IO uint32_t txerru : 1; /* [4] */
|
|
__IO uint32_t rxerro : 1; /* [5] */
|
|
__IO uint32_t cmdrspcmpl : 1; /* [6] */
|
|
__IO uint32_t cmdcmpl : 1; /* [7] */
|
|
__IO uint32_t dtcmpl : 1; /* [8] */
|
|
__IO uint32_t sbiterr : 1; /* [9] */
|
|
__IO uint32_t dtblkcmpl : 1; /* [10] */
|
|
__IO uint32_t reserved1 : 11;/* [21:11] */
|
|
__IO uint32_t ioif : 1; /* [22] */
|
|
__IO uint32_t reserved2 : 9; /* [31:23] */
|
|
} intclr_bit;
|
|
};
|
|
|
|
/**
|
|
* @brief sdio inten register, offset:0x3C
|
|
*/
|
|
union
|
|
{
|
|
__IO uint32_t inten;
|
|
struct
|
|
{
|
|
__IO uint32_t cmdfailien : 1; /* [0] */
|
|
__IO uint32_t dtfailien : 1; /* [1] */
|
|
__IO uint32_t cmdtimeoutien : 1; /* [2] */
|
|
__IO uint32_t dttimeoutien : 1; /* [3] */
|
|
__IO uint32_t txerruien : 1; /* [4] */
|
|
__IO uint32_t rxerroien : 1; /* [5] */
|
|
__IO uint32_t cmdrspcmplien : 1; /* [6] */
|
|
__IO uint32_t cmdcmplien : 1; /* [7] */
|
|
__IO uint32_t dtcmplien : 1; /* [8] */
|
|
__IO uint32_t sbiterrien : 1; /* [9] */
|
|
__IO uint32_t dtblkcmplien : 1; /* [10] */
|
|
__IO uint32_t docmdien : 1; /* [11] */
|
|
__IO uint32_t dotxien : 1; /* [12] */
|
|
__IO uint32_t dorxien : 1; /* [13] */
|
|
__IO uint32_t txbufhien : 1; /* [14] */
|
|
__IO uint32_t rxbufhien : 1; /* [15] */
|
|
__IO uint32_t txbuffien : 1; /* [16] */
|
|
__IO uint32_t rxbuffien : 1; /* [17] */
|
|
__IO uint32_t txbufeien : 1; /* [18] */
|
|
__IO uint32_t rxbufeien : 1; /* [19] */
|
|
__IO uint32_t txbufien : 1; /* [20] */
|
|
__IO uint32_t rxbufien : 1; /* [21] */
|
|
__IO uint32_t ioifien : 1; /* [22] */
|
|
__IO uint32_t reserved1 : 9; /* [31:23] */
|
|
} inten_bit;
|
|
};
|
|
|
|
/**
|
|
* @brief sdio reserved1 register, offset:0x40~0x44
|
|
*/
|
|
__IO uint32_t reserved1[2];
|
|
|
|
/**
|
|
* @brief sdio bufcnt register, offset:0x48
|
|
*/
|
|
union
|
|
{
|
|
__IO uint32_t bufcnt;
|
|
struct
|
|
{
|
|
__IO uint32_t cnt : 24;/* [23:0] */
|
|
__IO uint32_t reserved1 : 8; /* [31:24] */
|
|
} bufcnt_bit;
|
|
};
|
|
|
|
/**
|
|
* @brief sdio reserved2 register, offset:0x4C~0x7C
|
|
*/
|
|
__IO uint32_t reserved2[13];
|
|
|
|
/**
|
|
* @brief sdio buf register, offset:0x80
|
|
*/
|
|
union
|
|
{
|
|
__IO uint32_t buf;
|
|
struct
|
|
{
|
|
__IO uint32_t dt : 32;/* [31:0] */
|
|
} buf_bit;
|
|
};
|
|
|
|
} sdio_type;
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#define SDIO1 ((sdio_type *) SDIO1_BASE)
|
|
#define SDIO2 ((sdio_type *) SDIO2_BASE)
|
|
|
|
/** @defgroup SDIO_exported_functions
|
|
* @{
|
|
*/
|
|
|
|
void sdio_reset(sdio_type *sdio_x);
|
|
void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
|
|
sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x);
|
|
void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
|
|
void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
|
|
void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
|
|
void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
|
|
void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
|
|
void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
|
|
void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
|
|
void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state);
|
|
flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
|
|
void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
|
|
void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
|
|
void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
|
|
uint8_t sdio_command_response_get(sdio_type *sdio_x);
|
|
uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
|
|
void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
|
|
void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
|
|
uint32_t sdio_data_counter_get(sdio_type *sdio_x);
|
|
uint32_t sdio_data_read(sdio_type *sdio_x);
|
|
uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
|
|
void sdio_data_write(sdio_type *sdio_x, uint32_t data);
|
|
void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
|
|
void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
|
|
void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
|
|
void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
|
|
void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif
|