274 lines
9.9 KiB
C
274 lines
9.9 KiB
C
/**
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**************************************************************************
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* @file main.c
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* @brief main program
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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#include "at32f435_437_board.h"
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#include "at32f435_437_clock.h"
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/** @addtogroup AT32F435_periph_examples
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* @{
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*/
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/** @addtogroup 435_USART_transfer_by_dma_interrupt USART_transfer_by_dma_interrupt
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* @{
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*/
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#define COUNTOF(a) (sizeof(a) / sizeof(*(a)))
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#define USART2_TX_BUFFER_SIZE (COUNTOF(usart2_tx_buffer) - 1)
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#define USART3_TX_BUFFER_SIZE (COUNTOF(usart3_tx_buffer) - 1)
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uint8_t usart2_tx_buffer[] = "usart transfer by dma interrupt: usart2 -> usart3 using dma";
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uint8_t usart3_tx_buffer[] = "usart transfer by dma interrupt: usart3 -> usart2 using dma";
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uint8_t usart2_rx_buffer[USART3_TX_BUFFER_SIZE];
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uint8_t usart3_rx_buffer[USART2_TX_BUFFER_SIZE];
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volatile uint8_t usart2_tx_dma_status = 0;
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volatile uint8_t usart2_rx_dma_status = 0;
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volatile uint8_t usart3_tx_dma_status = 0;
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volatile uint8_t usart3_rx_dma_status = 0;
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/**
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* @brief config usart
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* @param none
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* @retval none
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*/
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void usart_configuration(void)
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{
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gpio_init_type gpio_init_struct;
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/* enable the usart2 and gpio clock */
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crm_periph_clock_enable(CRM_USART2_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
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/* enable the usart3 and gpio clock */
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crm_periph_clock_enable(CRM_USART3_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
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gpio_default_para_init(&gpio_init_struct);
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/* configure the usart2 tx, rx pin */
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_pins = GPIO_PINS_2 | GPIO_PINS_3;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init(GPIOA, &gpio_init_struct);
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gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE2, GPIO_MUX_7);
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gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE3, GPIO_MUX_7);
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/* configure the usart3 tx, rx pin */
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gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
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gpio_init(GPIOB, &gpio_init_struct);
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_7);
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_7);
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/* configure usart2 param */
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usart_init(USART2, 115200, USART_DATA_8BITS, USART_STOP_1_BIT);
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usart_transmitter_enable(USART2, TRUE);
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usart_receiver_enable(USART2, TRUE);
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usart_dma_transmitter_enable(USART2, TRUE);
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usart_dma_receiver_enable(USART2, TRUE);
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usart_enable(USART2, TRUE);
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/* configure usart3 param */
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usart_init(USART3, 115200, USART_DATA_8BITS, USART_STOP_1_BIT);
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usart_transmitter_enable(USART3, TRUE);
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usart_receiver_enable(USART3, TRUE);
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usart_dma_transmitter_enable(USART3, TRUE);
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usart_dma_receiver_enable(USART3, TRUE);
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usart_enable(USART3, TRUE);
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}
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/**
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* @brief config dma for usart2 and usart3
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* @param none
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* @retval none
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*/
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void dma_configuration(void)
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{
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dma_init_type dma_init_struct;
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/* enable dma1 clock */
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crm_periph_clock_enable(CRM_DMA1_PERIPH_CLOCK, TRUE);
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dmamux_enable(DMA1, TRUE);
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/* dma1 channel1 for usart2 tx configuration */
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dma_reset(DMA1_CHANNEL1);
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dma_default_para_init(&dma_init_struct);
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dma_init_struct.buffer_size = USART2_TX_BUFFER_SIZE;
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dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
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dma_init_struct.memory_base_addr = (uint32_t)usart2_tx_buffer;
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dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
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dma_init_struct.memory_inc_enable = TRUE;
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dma_init_struct.peripheral_base_addr = (uint32_t)&USART2->dt;
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dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
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dma_init_struct.peripheral_inc_enable = FALSE;
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dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init(DMA1_CHANNEL1, &dma_init_struct);
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
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/* dma1 channel1 interrupt nvic init */
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nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
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nvic_irq_enable(DMA1_Channel1_IRQn, 0, 0);
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/* config flexible dma for usart2 tx */
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dmamux_init(DMA1MUX_CHANNEL1, DMAMUX_DMAREQ_ID_USART2_TX);
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/* dma1 channel2 for usart2 rx configuration */
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dma_reset(DMA1_CHANNEL2);
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dma_default_para_init(&dma_init_struct);
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dma_init_struct.buffer_size = USART3_TX_BUFFER_SIZE;
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dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
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dma_init_struct.memory_base_addr = (uint32_t)usart2_rx_buffer;
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dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
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dma_init_struct.memory_inc_enable = TRUE;
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dma_init_struct.peripheral_base_addr = (uint32_t)&USART2->dt;
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dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
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dma_init_struct.peripheral_inc_enable = FALSE;
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dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init(DMA1_CHANNEL2, &dma_init_struct);
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA1_CHANNEL2, DMA_FDT_INT, TRUE);
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/* dma1 channel2 interrupt nvic init */
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nvic_irq_enable(DMA1_Channel2_IRQn, 0, 0);
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/* config flexible dma for usart2 rx */
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dmamux_init(DMA1MUX_CHANNEL2, DMAMUX_DMAREQ_ID_USART2_RX);
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/* dma1 channel3 for usart3 tx configuration */
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dma_reset(DMA1_CHANNEL3);
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dma_default_para_init(&dma_init_struct);
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dma_init_struct.buffer_size = USART3_TX_BUFFER_SIZE;
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dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
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dma_init_struct.memory_base_addr = (uint32_t)usart3_tx_buffer;
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dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
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dma_init_struct.memory_inc_enable = TRUE;
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dma_init_struct.peripheral_base_addr = (uint32_t)&USART3->dt;
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dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
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dma_init_struct.peripheral_inc_enable = FALSE;
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dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init(DMA1_CHANNEL3, &dma_init_struct);
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA1_CHANNEL3, DMA_FDT_INT, TRUE);
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/* dma1 channel3 interrupt nvic init */
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nvic_irq_enable(DMA1_Channel3_IRQn, 0, 0);
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/* config flexible dma for usart3 tx */
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dmamux_init(DMA1MUX_CHANNEL3, DMAMUX_DMAREQ_ID_USART3_TX);
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/* dma1 channel4 for usart3 rx configuration */
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dma_reset(DMA1_CHANNEL4);
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dma_default_para_init(&dma_init_struct);
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dma_init_struct.buffer_size = USART2_TX_BUFFER_SIZE;
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dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
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dma_init_struct.memory_base_addr = (uint32_t)usart3_rx_buffer;
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dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
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dma_init_struct.memory_inc_enable = TRUE;
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dma_init_struct.peripheral_base_addr = (uint32_t)&USART3->dt;
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dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
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dma_init_struct.peripheral_inc_enable = FALSE;
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dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init(DMA1_CHANNEL4, &dma_init_struct);
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA1_CHANNEL4, DMA_FDT_INT, TRUE);
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/* dma1 channel4 interrupt nvic init */
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nvic_irq_enable(DMA1_Channel4_IRQn, 0, 0);
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/* config flexible dma for usart3 rx */
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dmamux_init(DMA1MUX_CHANNEL4, DMAMUX_DMAREQ_ID_USART3_RX);
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dma_channel_enable(DMA1_CHANNEL2, TRUE); /* usart2 rx begin dma receiving */
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dma_channel_enable(DMA1_CHANNEL4, TRUE); /* usart3 rx begin dma receiving */
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dma_channel_enable(DMA1_CHANNEL1, TRUE); /* usart2 tx begin dma transmitting */
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dma_channel_enable(DMA1_CHANNEL3, TRUE); /* usart3 tx begin dma transmitting */
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}
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/**
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* @brief compares two buffers.
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* @param pbuffer1, pbuffer2: buffers to be compared.
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* @param buffer_length: buffer's length
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* @retval 1: pbuffer1 identical to pbuffer2
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* 0: pbuffer1 differs from pbuffer2
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*/
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uint8_t buffer_compare(uint8_t* pbuffer1, uint8_t* pbuffer2, uint16_t buffer_length)
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{
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while(buffer_length--)
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{
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if(*pbuffer1 != *pbuffer2)
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{
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return 0;
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}
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pbuffer1++;
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pbuffer2++;
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}
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return 1;
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}
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/**
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* @brief main function.
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* @param none
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* @retval none
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*/
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int main(void)
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{
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system_clock_config();
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at32_board_init();
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usart_configuration();
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dma_configuration();
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/* wait dma transmission complete */
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while((usart2_tx_dma_status == 0) || (usart2_rx_dma_status == 0) || (usart3_tx_dma_status == 0) || (usart3_rx_dma_status == 0));
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while(1)
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{
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/* compare data buffer */
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if(buffer_compare(usart2_tx_buffer, usart3_rx_buffer, USART2_TX_BUFFER_SIZE) && \
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buffer_compare(usart3_tx_buffer, usart2_rx_buffer, USART3_TX_BUFFER_SIZE))
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{
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at32_led_toggle(LED2);
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at32_led_toggle(LED3);
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at32_led_toggle(LED4);
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delay_sec(1);
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}
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}
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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