146 lines
4.8 KiB
C
146 lines
4.8 KiB
C
/**
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**************************************************************************
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* @file main.c
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* @brief main program
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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#include "at32f435_437_board.h"
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#include "at32f435_437_clock.h"
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/** @addtogroup AT32F437_periph_examples
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* @{
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*/
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/** @addtogroup 437_DMAMUX_genertor_exint DMAMUX_genertor_exint
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* @{
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*/
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gpio_init_type gpio_init_struct = {0};
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dma_init_type dma_init_struct;
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dmamux_gen_init_type dmamux_gen_init_struct;
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exint_init_type exint_init_struct;
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#define BUFFER_SIZE 16
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uint16_t src_buffer[BUFFER_SIZE] = {0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, 0x0008,
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0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010};
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uint16_t dst_buffer[BUFFER_SIZE];
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/**
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* @brief exint1 interrupt handler
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* @param none
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* @retval none
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*/
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void EXINT1_IRQHandler(void)
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{
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if(exint_flag_get(EXINT_LINE_1) != RESET)
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{
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at32_led_toggle(LED2);
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exint_flag_clear(EXINT_LINE_1);
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}
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}
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/**
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* @brief main function.
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* @param none
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* @retval none
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*/
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int main(void)
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{
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/* initial system clock */
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system_clock_config();
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/* at board initial */
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at32_board_init();
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/* enable dma2/gpioa clock */
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crm_periph_clock_enable(CRM_DMA2_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
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/* config pa1 for input mode */
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gpio_init_struct.gpio_pins = GPIO_PINS_1;
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gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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gpio_init(GPIOA, &gpio_init_struct);
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scfg_exint_line_config(SCFG_PORT_SOURCE_GPIOA, SCFG_PINS_SOURCE1);
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exint_default_para_init(&exint_init_struct);
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exint_init_struct.line_enable = TRUE;
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exint_init_struct.line_mode = EXINT_LINE_INTERRUPUT;
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exint_init_struct.line_select = EXINT_LINE_1;
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exint_init_struct.line_polarity = EXINT_TRIGGER_RISING_EDGE;
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exint_init(&exint_init_struct);
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/* exint line1 interrupt nvic init */
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nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
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nvic_irq_enable(EXINT1_IRQn, 1, 0);
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/* dma2 channel4 configuration */
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dma_reset(DMA2_CHANNEL4);
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dma_init_struct.buffer_size = BUFFER_SIZE;
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dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
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dma_init_struct.memory_base_addr = (uint32_t)dst_buffer;
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dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_HALFWORD;
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dma_init_struct.memory_inc_enable = TRUE;
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dma_init_struct.peripheral_base_addr = (uint32_t)src_buffer;
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dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_HALFWORD;
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dma_init_struct.peripheral_inc_enable = TRUE;
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dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init(DMA2_CHANNEL4, &dma_init_struct);
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/* genertor1 configuration */
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dmamux_generator_default_para_init(&dmamux_gen_init_struct);
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dmamux_gen_init_struct.gen_polarity = DMAMUX_GEN_POLARITY_RISING;
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dmamux_gen_init_struct.gen_request_number = 4;
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dmamux_gen_init_struct.gen_signal_sel = DMAMUX_GEN_ID_EXINT1;
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dmamux_gen_init_struct.gen_enable = TRUE;
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dmamux_generator_config(DMA2MUX_GENERATOR1, &dmamux_gen_init_struct);
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);
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/* dma2 channel4 interrupt nvic init */
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nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
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nvic_irq_enable(DMA2_Channel4_IRQn, 1, 0);
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/* dmamux function enable */
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dmamux_enable(DMA2, TRUE);
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dmamux_init(DMA2MUX_CHANNEL4, DMAMUX_DMAREQ_ID_REQ_G1);
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/* enable dma channe4 */
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dma_channel_enable(DMA2_CHANNEL4, TRUE);
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while(1)
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{
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}
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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