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AT32F435_437_Firmware_Library
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AT32F435_437_Firmware_Library/project/at_start_f437/examples/usart/transfer_by_dma_interrupt/src/main.c

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/**
**************************************************************************
* @file main.c
* @brief main program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f435_437_board.h"
#include "at32f435_437_clock.h"
/** @addtogroup AT32F437_periph_examples
* @{
*/
/** @addtogroup 437_USART_transfer_by_dma_interrupt USART_transfer_by_dma_interrupt
* @{
*/
#define COUNTOF(a) (sizeof(a) / sizeof(*(a)))
#define USART2_TX_BUFFER_SIZE (COUNTOF(usart2_tx_buffer) - 1)
#define USART3_TX_BUFFER_SIZE (COUNTOF(usart3_tx_buffer) - 1)
uint8_t usart2_tx_buffer[] = "usart transfer by dma interrupt: usart2 -> usart3 using dma";
uint8_t usart3_tx_buffer[] = "usart transfer by dma interrupt: usart3 -> usart2 using dma";
uint8_t usart2_rx_buffer[USART3_TX_BUFFER_SIZE];
uint8_t usart3_rx_buffer[USART2_TX_BUFFER_SIZE];
volatile uint8_t usart2_tx_dma_status = 0;
volatile uint8_t usart2_rx_dma_status = 0;
volatile uint8_t usart3_tx_dma_status = 0;
volatile uint8_t usart3_rx_dma_status = 0;
/**
* @brief config usart
* @param none
* @retval none
*/
void usart_configuration(void)
{
gpio_init_type gpio_init_struct;
/* enable the usart2 and gpio clock */
crm_periph_clock_enable(CRM_USART2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
/* enable the usart3 and gpio clock */
crm_periph_clock_enable(CRM_USART3_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_default_para_init(&gpio_init_struct);
/* configure the usart2 tx, rx pin */
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_pins = GPIO_PINS_2 | GPIO_PINS_3;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init(GPIOA, &gpio_init_struct);
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE2, GPIO_MUX_7);
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE3, GPIO_MUX_7);
/* configure the usart3 tx, rx pin */
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_7);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_7);
/* configure usart2 param */
usart_init(USART2, 115200, USART_DATA_8BITS, USART_STOP_1_BIT);
usart_transmitter_enable(USART2, TRUE);
usart_receiver_enable(USART2, TRUE);
usart_dma_transmitter_enable(USART2, TRUE);
usart_dma_receiver_enable(USART2, TRUE);
usart_enable(USART2, TRUE);
/* configure usart3 param */
usart_init(USART3, 115200, USART_DATA_8BITS, USART_STOP_1_BIT);
usart_transmitter_enable(USART3, TRUE);
usart_receiver_enable(USART3, TRUE);
usart_dma_transmitter_enable(USART3, TRUE);
usart_dma_receiver_enable(USART3, TRUE);
usart_enable(USART3, TRUE);
}
/**
* @brief config dma for usart2 and usart3
* @param none
* @retval none
*/
void dma_configuration(void)
{
dma_init_type dma_init_struct;
/* enable dma1 clock */
crm_periph_clock_enable(CRM_DMA1_PERIPH_CLOCK, TRUE);
dmamux_enable(DMA1, TRUE);
/* dma1 channel1 for usart2 tx configuration */
dma_reset(DMA1_CHANNEL1);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = USART2_TX_BUFFER_SIZE;
dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
dma_init_struct.memory_base_addr = (uint32_t)usart2_tx_buffer;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)&USART2->dt;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL1, &dma_init_struct);
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
/* dma1 channel1 interrupt nvic init */
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
nvic_irq_enable(DMA1_Channel1_IRQn, 0, 0);
/* config flexible dma for usart2 tx */
dmamux_init(DMA1MUX_CHANNEL1, DMAMUX_DMAREQ_ID_USART2_TX);
/* dma1 channel2 for usart2 rx configuration */
dma_reset(DMA1_CHANNEL2);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = USART3_TX_BUFFER_SIZE;
dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dma_init_struct.memory_base_addr = (uint32_t)usart2_rx_buffer;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)&USART2->dt;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL2, &dma_init_struct);
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL2, DMA_FDT_INT, TRUE);
/* dma1 channel2 interrupt nvic init */
nvic_irq_enable(DMA1_Channel2_IRQn, 0, 0);
/* config flexible dma for usart2 rx */
dmamux_init(DMA1MUX_CHANNEL2, DMAMUX_DMAREQ_ID_USART2_RX);
/* dma1 channel3 for usart3 tx configuration */
dma_reset(DMA1_CHANNEL3);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = USART3_TX_BUFFER_SIZE;
dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
dma_init_struct.memory_base_addr = (uint32_t)usart3_tx_buffer;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)&USART3->dt;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL3, &dma_init_struct);
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL3, DMA_FDT_INT, TRUE);
/* dma1 channel3 interrupt nvic init */
nvic_irq_enable(DMA1_Channel3_IRQn, 0, 0);
/* config flexible dma for usart3 tx */
dmamux_init(DMA1MUX_CHANNEL3, DMAMUX_DMAREQ_ID_USART3_TX);
/* dma1 channel4 for usart3 rx configuration */
dma_reset(DMA1_CHANNEL4);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = USART2_TX_BUFFER_SIZE;
dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dma_init_struct.memory_base_addr = (uint32_t)usart3_rx_buffer;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)&USART3->dt;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL4, &dma_init_struct);
/* enable transfer full data interrupt */
dma_interrupt_enable(DMA1_CHANNEL4, DMA_FDT_INT, TRUE);
/* dma1 channel4 interrupt nvic init */
nvic_irq_enable(DMA1_Channel4_IRQn, 0, 0);
/* config flexible dma for usart3 rx */
dmamux_init(DMA1MUX_CHANNEL4, DMAMUX_DMAREQ_ID_USART3_RX);
dma_channel_enable(DMA1_CHANNEL2, TRUE); /* usart2 rx begin dma receiving */
dma_channel_enable(DMA1_CHANNEL4, TRUE); /* usart3 rx begin dma receiving */
dma_channel_enable(DMA1_CHANNEL1, TRUE); /* usart2 tx begin dma transmitting */
dma_channel_enable(DMA1_CHANNEL3, TRUE); /* usart3 tx begin dma transmitting */
}
/**
* @brief compares two buffers.
* @param pbuffer1, pbuffer2: buffers to be compared.
* @param buffer_length: buffer's length
* @retval 1: pbuffer1 identical to pbuffer2
* 0: pbuffer1 differs from pbuffer2
*/
uint8_t buffer_compare(uint8_t* pbuffer1, uint8_t* pbuffer2, uint16_t buffer_length)
{
while(buffer_length--)
{
if(*pbuffer1 != *pbuffer2)
{
return 0;
}
pbuffer1++;
pbuffer2++;
}
return 1;
}
/**
* @brief main function.
* @param none
* @retval none
*/
int main(void)
{
system_clock_config();
at32_board_init();
usart_configuration();
dma_configuration();
/* wait dma transmission complete */
while((usart2_tx_dma_status == 0) || (usart2_rx_dma_status == 0) || (usart3_tx_dma_status == 0) || (usart3_rx_dma_status == 0));
while(1)
{
/* compare data buffer */
if(buffer_compare(usart2_tx_buffer, usart3_rx_buffer, USART2_TX_BUFFER_SIZE) && \
buffer_compare(usart3_tx_buffer, usart2_rx_buffer, USART3_TX_BUFFER_SIZE))
{
at32_led_toggle(LED2);
at32_led_toggle(LED3);
at32_led_toggle(LED4);
delay_sec(1);
}
}
}
/**
* @}
*/
/**
* @}
*/
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