2021-03-19 10:05:24 -07:00
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file GPIO/hal_pal_lld.c
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2021-04-06 00:11:47 -07:00
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* @brief GD32 PAL low level driver code.
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*
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* @addtogroup PAL
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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2021-03-22 05:18:20 -07:00
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#if GD32_HAS_GPIOE
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#define APB2_EN_MASK (RCU_APB2EN_PAEN | RCU_APB2EN_PBEN | \
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RCU_APB2EN_PCEN | RCU_APB2EN_PDEN | \
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RCU_APB2EN_PEEN | RCU_APB2EN_AFEN)
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#else
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#define APB2_EN_MASK (RCU_APB2EN_PAEN | RCU_APB2EN_PBEN | \
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RCU_APB2EN_PCEN | RCU_APB2EN_PDEN | \
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RCU_APB2EN_AFEN)
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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#if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE) || defined(__DOXYGEN__)
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/**
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* @brief Event records for the 16 GPIO EXTI channels.
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*/
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palevent_t _pal_events[16];
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief GD32 I/O ports configuration.
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* @details Ports A-D(E) clocks enabled, AFIO clock enabled.
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*
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* @param[in] config the GD32 ports configuration
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*
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* @notapi
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*/
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void _pal_lld_init(const PALConfig *config) {
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#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__)
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unsigned i;
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for (i = 0; i < 16; i++) {
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_pal_init_event(i);
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}
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#endif
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/*
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* Enables the GPIO related clocks.
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*/
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2021-03-31 02:24:51 -07:00
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rcuEnableAPB2(APB2_EN_MASK, true);
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/*
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* Initial GPIO setup.
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*/
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GPIOA->OCTL = config->PAData.octl;
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GPIOA->CTL1 = config->PAData.ctl1;
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GPIOA->CTL0 = config->PAData.ctl0;
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GPIOB->OCTL = config->PBData.octl;
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GPIOB->CTL1 = config->PBData.ctl1;
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GPIOB->CTL0 = config->PBData.ctl0;
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GPIOC->OCTL = config->PCData.octl;
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GPIOC->CTL1 = config->PCData.ctl1;
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GPIOC->CTL0 = config->PCData.ctl0;
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GPIOD->OCTL = config->PDData.octl;
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GPIOD->CTL1 = config->PDData.ctl1;
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GPIOD->CTL0 = config->PDData.ctl0;
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#if GD32_HAS_GPIOE || defined(__DOXYGEN__)
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GPIOE->OCTL = config->PEData.octl;
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GPIOE->CTL1 = config->PEData.ctl1;
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GPIOE->CTL0 = config->PEData.ctl0;
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#endif
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}
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/**
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* @brief Pads mode setup.
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* @details This function programs a pads group belonging to the same port
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* with the specified mode.
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* @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz.
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* @note Writing on pads programmed as pull-up or pull-down has the side
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* effect to modify the resistor setting because the output latched
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* data is used for the resistor selection.
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*
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* @param[in] port the port identifier
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* @param[in] mask the group mask
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* @param[in] mode the mode
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*
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* @notapi
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*/
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void _pal_lld_setgroupmode(ioportid_t port,
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ioportmask_t mask,
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iomode_t mode) {
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static const uint8_t cfgtab[] = {
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4, /* PAL_MODE_RESET, implemented as input.*/
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2, /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/
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4, /* PAL_MODE_INPUT */
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8, /* PAL_MODE_INPUT_PULLUP */
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8, /* PAL_MODE_INPUT_PULLDOWN */
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0, /* PAL_MODE_INPUT_ANALOG */
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3, /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/
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7, /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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0xB, /* PAL_MODE_GD32_ALTERNATE_PUSHPULL, 50MHz.*/
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0xF, /* PAL_MODE_GD32_ALTERNATE_OPENDRAIN, 50MHz.*/
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};
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uint32_t mh, ml, ctl1, ctl0, cfg;
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unsigned i;
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if (mode == PAL_MODE_INPUT_PULLUP)
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port->BOP = mask;
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else if (mode == PAL_MODE_INPUT_PULLDOWN)
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port->BC = mask;
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cfg = cfgtab[mode];
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mh = ml = ctl1 = ctl0 = 0;
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for (i = 0; i < 8; i++) {
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ml <<= 4;
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mh <<= 4;
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ctl0 <<= 4;
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ctl1 <<= 4;
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if ((mask & 0x0080) == 0)
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ml |= 0xf;
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else
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ctl0 |= cfg;
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if ((mask & 0x8000) == 0)
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mh |= 0xf;
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else
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ctl1 |= cfg;
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mask <<= 1;
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}
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port->CTL1 = (port->CTL1 & mh) | ctl1;
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port->CTL0 = (port->CTL0 & ml) | ctl0;
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}
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#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__)
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/**
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* @brief Pad event enable.
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* @note Programming an unknown or unsupported mode is silently ignored.
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*
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* @param[in] port port identifier
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* @param[in] pad pad number within the port
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* @param[in] mode pad event mode
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*
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* @notapi
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*/
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void _pal_lld_enablepadevent(ioportid_t port,
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iopadid_t pad,
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ioeventmode_t mode) {
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uint32_t padmask, cridx, croff, crmask, portidx;
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/* Mask of the pad.*/
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padmask = 1U << (uint32_t)pad;
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/* Multiple channel setting of the same channel not allowed, first disable
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it. This is done because on GD32 the same channel cannot be mapped on
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multiple ports.*/
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osalDbgAssert(((EXTI->RTEN & padmask) == 0U) &&
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((EXTI->FTEN & padmask) == 0U), "channel already in use");
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/* Index and mask of the SYSCFG CR register to be used.*/
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cridx = (uint32_t)pad >> 2U;
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croff = ((uint32_t)pad & 3U) * 4U;
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crmask = ~(0xFU << croff);
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/* Port index is obtained assuming that GPIO ports are placed at regular
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0x400 intervals in memory space. So far this is true for all devices.*/
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portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
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/* Port selection in SYSCFG.*/
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AFIO->EXTICR[cridx] = (AFIO->EXTICR[cridx] & crmask) | (portidx << croff);
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/* Programming edge registers.*/
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if (mode & PAL_EVENT_MODE_RISING_EDGE)
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EXTI->RTEN |= padmask;
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else
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EXTI->RTEN &= ~padmask;
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if (mode & PAL_EVENT_MODE_FALLING_EDGE)
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EXTI->FTEN |= padmask;
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else
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EXTI->FTEN &= ~padmask;
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/* Programming interrupt and event registers.*/
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EXTI->INTEN |= padmask;
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EXTI->EVEN &= ~padmask;
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}
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/**
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* @brief Pad event disable.
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* @details This function disables previously programmed event callbacks.
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*
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* @param[in] port port identifier
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* @param[in] pad pad number within the port
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*
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* @notapi
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*/
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void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
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uint32_t padmask, rtsr1, ftsr1;
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rtsr1 = EXTI->RTEN;
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ftsr1 = EXTI->FTEN;
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/* Mask of the pad.*/
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padmask = 1U << (uint32_t)pad;
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/* If either RTRS1 or FTSR1 is enabled then the channel is in use.*/
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if (((rtsr1 | ftsr1) & padmask) != 0U) {
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uint32_t cridx, croff, crport, portidx;
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/* Index and mask of the SYSCFG CR register to be used.*/
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cridx = (uint32_t)pad >> 2U;
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croff = ((uint32_t)pad & 3U) * 4U;
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/* Port index is obtained assuming that GPIO ports are placed at regular
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0x400 intervals in memory space. So far this is true for all devices.*/
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portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
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crport = (AFIO->EXTICR[cridx] >> croff) & 0xFU;
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osalDbgAssert(crport == portidx, "channel mapped on different port");
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/* Disabling channel.*/
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EXTI->INTEN &= ~padmask;
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EXTI->EVEN &= ~padmask;
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EXTI->RTEN = rtsr1 & ~padmask;
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EXTI->FTEN = ftsr1 & ~padmask;
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EXTI->PD = padmask;
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#if PAL_USE_CALLBACKS || PAL_USE_WAIT
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/* Callback cleared and/or thread reset.*/
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_pal_clear_event(pad);
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#endif
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}
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}
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#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */
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#endif /* HAL_USE_PAL */
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/** @} */
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