CAN Register renames
This commit is contained in:
Stefan Kerkmann
parent
8539fe76bc
commit
004ed9d005
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@ -89,8 +89,8 @@ static void can_lld_set_filters(CANDriver* canp,
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if (canp == &CAND1) {
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rccEnableCAN1(true);
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/* Filters initialization.*/
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canp->can->FMR = (canp->can->FMR & 0xFFFF0000) | CAN_FMR_FINIT;
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canp->can->FMR = (canp->can->FMR & 0xFFFF0000) | (can2sb << 8) | CAN_FMR_FINIT;
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canp->can->FCTL = (canp->can->FCTL & 0xFFFF0000) | CAN_FCTL_FLD;
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canp->can->FCTL = (canp->can->FCTL & 0xFFFF0000) | (can2sb << 8) | CAN_FCTL_FLD;
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}
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#endif
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@ -98,10 +98,10 @@ static void can_lld_set_filters(CANDriver* canp,
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uint32_t i, fmask;
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/* All filters cleared.*/
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canp->can->FA1R = 0;
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canp->can->FM1R = 0;
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canp->can->FS1R = 0;
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canp->can->FFA1R = 0;
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canp->can->FW = 0;
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canp->can->FMCFG = 0;
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canp->can->FSCFG = 0;
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canp->can->FAFIFO = 0;
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#if GD32_CAN_USE_CAN1
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if (canp == &CAND1) {
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@ -116,14 +116,14 @@ static void can_lld_set_filters(CANDriver* canp,
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for (i = 0; i < num; i++) {
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fmask = 1 << cfp->filter;
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if (cfp->mode)
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canp->can->FM1R |= fmask;
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canp->can->FMCFG |= fmask;
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if (cfp->scale)
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canp->can->FS1R |= fmask;
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canp->can->FSCFG |= fmask;
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if (cfp->assignment)
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canp->can->FFA1R |= fmask;
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canp->can->FAFIFO |= fmask;
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canp->can->sFilterRegister[cfp->filter].FR1 = cfp->register1;
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canp->can->sFilterRegister[cfp->filter].FR2 = cfp->register2;
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canp->can->FA1R |= fmask;
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canp->can->FW |= fmask;
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cfp++;
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}
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}
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@ -138,18 +138,18 @@ static void can_lld_set_filters(CANDriver* canp,
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canp->can->sFilterRegister[can2sb].FR2 = 0;
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}
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#endif
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canp->can->FM1R = 0;
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canp->can->FFA1R = 0;
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canp->can->FS1R = 1;
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canp->can->FA1R = 1;
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canp->can->FMCFG = 0;
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canp->can->FAFIFO = 0;
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canp->can->FSCFG = 1;
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canp->can->FW = 1;
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#if GD32_CAN_USE_CAN2
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if (canp == &CAND1) {
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canp->can->FS1R |= 1 << can2sb;
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canp->can->FA1R |= 1 << can2sb;
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canp->can->FSCFG |= 1 << can2sb;
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canp->can->FW |= 1 << can2sb;
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}
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#endif
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}
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canp->can->FMR &= ~CAN_FMR_FINIT;
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canp->can->FCTL &= ~CAN_FCTL_FLD;
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/* Clock disabled, it will be enabled again in can_lld_start().*/
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/* Temporarily enabling CAN clock.*/
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@ -168,19 +168,19 @@ static void can_lld_set_filters(CANDriver* canp,
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* @notapi
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*/
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static void can_lld_tx_handler(CANDriver *canp) {
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uint32_t tsr;
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uint32_t tstat;
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eventflags_t flags;
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/* Clearing IRQ sources.*/
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tsr = canp->can->TSR;
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canp->can->TSR = tsr;
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tstat = canp->can->TSTAT;
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canp->can->TSTAT = tstat;
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/* Flags to be signaled through the TX event source.*/
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flags = 0U;
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/* Checking mailbox 0.*/
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if ((tsr & CAN_TSR_RQCP0) != 0U) {
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if ((tsr & (CAN_TSR_ALST0 | CAN_TSR_TERR0)) != 0U) {
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if ((tstat & CAN_TSTAT_MTF0) != 0U) {
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if ((tstat & (CAN_TSTAT_MAL0 | CAN_TSTAT_MTE0)) != 0U) {
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flags |= CAN_MAILBOX_TO_MASK(1U) << 16U;
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}
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else {
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@ -189,8 +189,8 @@ static void can_lld_tx_handler(CANDriver *canp) {
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}
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/* Checking mailbox 1.*/
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if ((tsr & CAN_TSR_RQCP1) != 0U) {
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if ((tsr & (CAN_TSR_ALST1 | CAN_TSR_TERR1)) != 0U) {
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if ((tstat & CAN_TSTAT_MTF1) != 0U) {
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if ((tstat & (CAN_TSTAT_MAL1 | CAN_TSTAT_MTE1)) != 0U) {
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flags |= CAN_MAILBOX_TO_MASK(2U) << 16U;
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}
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else {
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@ -199,8 +199,8 @@ static void can_lld_tx_handler(CANDriver *canp) {
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}
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/* Checking mailbox 2.*/
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if ((tsr & CAN_TSR_RQCP2) != 0U) {
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if ((tsr & (CAN_TSR_ALST2 | CAN_TSR_TERR2)) != 0U) {
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if ((tstat & CAN_TSTAT_MTF2) != 0U) {
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if ((tstat & (CAN_TSTAT_MAL2 | CAN_TSTAT_MTE2)) != 0U) {
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flags |= CAN_MAILBOX_TO_MASK(3U) << 16U;
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}
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else {
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@ -220,17 +220,17 @@ static void can_lld_tx_handler(CANDriver *canp) {
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* @notapi
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*/
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static void can_lld_rx0_handler(CANDriver *canp) {
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uint32_t rf0r;
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uint32_t rfifo0;
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rf0r = canp->can->RF0R;
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if ((rf0r & CAN_RF0R_FMP0) > 0) {
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rfifo0 = canp->can->RFIFO0;
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if ((rfifo0 & CAN_RFIFO0_RFL0) > 0) {
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/* No more receive events until the queue 0 has been emptied.*/
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canp->can->IER &= ~CAN_IER_FMPIE0;
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canp->can->INTEN &= ~CAN_INTEN_RFNEIE0;
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_can_rx_full_isr(canp, CAN_MAILBOX_TO_MASK(1U));
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}
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if ((rf0r & CAN_RF0R_FOVR0) > 0) {
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if ((rfifo0 & CAN_RFIFO0_RFO0) > 0) {
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/* Overflow events handling.*/
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canp->can->RF0R = CAN_RF0R_FOVR0;
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canp->can->RFIFO0 = CAN_RFIFO0_RFO0;
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_can_error_isr(canp, CAN_OVERFLOW_ERROR);
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}
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}
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@ -243,17 +243,17 @@ static void can_lld_rx0_handler(CANDriver *canp) {
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* @notapi
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*/
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static void can_lld_rx1_handler(CANDriver *canp) {
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uint32_t rf1r;
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uint32_t rfifo1;
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rf1r = canp->can->RF1R;
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if ((rf1r & CAN_RF1R_FMP1) > 0) {
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rfifo1 = canp->can->RFIFO1;
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if ((rfifo1 & CAN_RFIFO1_RFL1) > 0) {
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/* No more receive events until the queue 0 has been emptied.*/
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canp->can->IER &= ~CAN_IER_FMPIE1;
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canp->can->INTEN &= ~CAN_INTEN_RFNEIE1;
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_can_rx_full_isr(canp, CAN_MAILBOX_TO_MASK(2U));
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}
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if ((rf1r & CAN_RF1R_FOVR1) > 0) {
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if ((rfifo1 & CAN_RFIFO1_RFO1) > 0) {
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/* Overflow events handling.*/
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canp->can->RF1R = CAN_RF1R_FOVR1;
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canp->can->RFIFO1 = CAN_RFIFO1_RFO1;
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_can_error_isr(canp, CAN_OVERFLOW_ERROR);
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}
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}
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@ -266,28 +266,28 @@ static void can_lld_rx1_handler(CANDriver *canp) {
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* @notapi
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*/
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static void can_lld_sce_handler(CANDriver *canp) {
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uint32_t msr;
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uint32_t stat;
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/* Clearing IRQ sources.*/
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msr = canp->can->MSR;
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canp->can->MSR = msr;
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stat = canp->can->STAT;
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canp->can->STAT = stat;
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/* Wakeup event.*/
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#if CAN_USE_SLEEP_MODE
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if (msr & CAN_MSR_WKUI) {
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if (stat & CAN_STAT_WUIF) {
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canp->state = CAN_READY;
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canp->can->MCR &= ~CAN_MCR_SLEEP;
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canp->can->CTL &= ~CAN_CTL_SLPWMOD;
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_can_wakeup_isr(canp);
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}
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#endif /* CAN_USE_SLEEP_MODE */
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/* Error event.*/
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if (msr & CAN_MSR_ERRI) {
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if (stat & CAN_STAT_ERRIF) {
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eventflags_t flags;
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uint32_t esr = canp->can->ESR;
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uint32_t err = canp->can->ERR;
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#if GD32_CAN_REPORT_ALL_ERRORS
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flags = (eventflags_t)(esr & 7);
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if ((esr & CAN_ESR_LEC) > 0)
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flags = (eventflags_t)(err & 7);
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if ((err & CAN_ERR_ERRN) > 0)
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flags |= CAN_FRAMING_ERROR;
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#else
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flags = 0;
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@ -295,7 +295,7 @@ static void can_lld_sce_handler(CANDriver *canp) {
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/* The content of the ESR register is copied unchanged in the upper
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half word of the listener flags mask.*/
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_can_error_isr(canp, flags | (eventflags_t)(esr << 16U));
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_can_error_isr(canp, flags | (eventflags_t)(err << 16U));
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}
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}
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@ -558,23 +558,23 @@ void can_lld_start(CANDriver *canp) {
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#endif
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/* Configuring CAN. */
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canp->can->MCR = CAN_MCR_INRQ;
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while ((canp->can->MSR & CAN_MSR_INAK) == 0)
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canp->can->CTL = CAN_CTL_IWMOD;
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while ((canp->can->STAT & CAN_STAT_IWS) == 0)
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osalThreadSleepS(1);
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canp->can->BTR = canp->config->btr;
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canp->can->MCR = canp->config->mcr;
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canp->can->BT = canp->config->bt;
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canp->can->CTL = canp->config->ctl;
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/* Interrupt sources initialization.*/
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#if GD32_CAN_REPORT_ALL_ERRORS
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canp->can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 |
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CAN_IER_WKUIE | CAN_IER_ERRIE | CAN_IER_LECIE |
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CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE |
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CAN_IER_FOVIE0 | CAN_IER_FOVIE1;
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canp->can->INTEN = CAN_INTEN_TMEIE | CAN_INTEN_RFNEIE0 | CAN_INTEN_RFNEIE1 |
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CAN_INTEN_WIE | CAN_INTEN_ERRIE | CAN_INTEN_ERRNIE |
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CAN_INTEN_BOIE | CAN_INTEN_PERRIE | CAN_INTEN_WERRIE |
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CAN_INTEN_RFOIE0 | CAN_INTEN_RFOIE1;
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#else
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canp->can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 |
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CAN_IER_WKUIE | CAN_IER_ERRIE |
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CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE |
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CAN_IER_FOVIE0 | CAN_IER_FOVIE1;
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canp->can->INTEN = CAN_INTEN_TMEIE | CAN_INTEN_RFNEIE0 | CAN_INTEN_RFNEIE1 |
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CAN_INTEN_WIE | CAN_INTEN_ERRIE |
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CAN_INTEN_BOIE | CAN_INTEN_PERRIE | CAN_INTEN_WERRIE |
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CAN_INTEN_RFOIE0 | CAN_INTEN_RFOIE1;
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#endif
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}
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@ -591,8 +591,8 @@ void can_lld_stop(CANDriver *canp) {
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if (canp->state == CAN_READY) {
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#if GD32_CAN_USE_CAN1
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if (&CAND1 == canp) {
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CAN1->MCR = 0x00010002; /* Register reset value. */
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CAN1->IER = 0x00000000; /* All sources disabled. */
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CAN1->CTL = 0x00010002; /* Register reset value. */
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CAN1->INTEN = 0x00000000; /* All sources disabled. */
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#if GD32_CAN_USE_CAN2
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/* If CAND2 is stopped then CAN1 clock is stopped here.*/
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if (CAND2.state == CAN_STOP)
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@ -605,8 +605,8 @@ void can_lld_stop(CANDriver *canp) {
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#if GD32_CAN_USE_CAN2
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if (&CAND2 == canp) {
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CAN2->MCR = 0x00010002; /* Register reset value. */
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CAN2->IER = 0x00000000; /* All sources disabled. */
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CAN2->CTL = 0x00010002; /* Register reset value. */
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CAN2->INTEN = 0x00000000; /* All sources disabled. */
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#if GD32_CAN_USE_CAN1
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/* If CAND1 is stopped then CAN1 clock is stopped here.*/
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if (CAND1.state == CAN_STOP)
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@ -636,13 +636,13 @@ bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
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switch (mailbox) {
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case CAN_ANY_MAILBOX:
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return (canp->can->TSR & CAN_TSR_TME) != 0;
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return (canp->can->TSTAT & CAN_TSTAT_TME) != 0;
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case 1:
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return (canp->can->TSR & CAN_TSR_TME0) != 0;
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return (canp->can->TSTAT & CAN_TSTAT_TME0) != 0;
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case 2:
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return (canp->can->TSR & CAN_TSR_TME1) != 0;
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return (canp->can->TSTAT & CAN_TSTAT_TME1) != 0;
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case 3:
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return (canp->can->TSR & CAN_TSR_TME2) != 0;
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return (canp->can->TSTAT & CAN_TSTAT_TME2) != 0;
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default:
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return false;
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}
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@ -666,7 +666,7 @@ void can_lld_transmit(CANDriver *canp,
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/* Pointer to a free transmission mailbox.*/
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switch (mailbox) {
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case CAN_ANY_MAILBOX:
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tmbp = &canp->can->sTxMailBox[(canp->can->TSR & CAN_TSR_CODE) >> 24];
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tmbp = &canp->can->sTxMailBox[(canp->can->TSTAT & CAN_TSTAT_NUM) >> 24];
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break;
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case 1:
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tmbp = &canp->can->sTxMailBox[0];
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@ -684,13 +684,13 @@ void can_lld_transmit(CANDriver *canp,
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/* Preparing the message.*/
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if (ctfp->IDE)
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tir = ((uint32_t)ctfp->EID << 3) | ((uint32_t)ctfp->RTR << 1) |
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CAN_TI0R_IDE;
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CAN_TMI0_FF;
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else
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tir = ((uint32_t)ctfp->SID << 21) | ((uint32_t)ctfp->RTR << 1);
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tmbp->TDTR = ctfp->DLC;
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tmbp->TDLR = ctfp->data32[0];
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tmbp->TDHR = ctfp->data32[1];
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tmbp->TIR = tir | CAN_TI0R_TXRQ;
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tmbp->TMP = ctfp->DLC;
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tmbp->DATA0 = ctfp->data32[0];
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tmbp->DATA1 = ctfp->data32[1];
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tmbp->TMI = tir | CAN_TMI0_TEN;
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}
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/**
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@ -709,12 +709,12 @@ bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
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switch (mailbox) {
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case CAN_ANY_MAILBOX:
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return ((canp->can->RF0R & CAN_RF0R_FMP0) != 0 ||
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(canp->can->RF1R & CAN_RF1R_FMP1) != 0);
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return ((canp->can->RFIFO0 & CAN_RFIFO0_RFL0) != 0 ||
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(canp->can->RFIFO1 & CAN_RFIFO1_RFL1) != 0);
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case 1:
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return (canp->can->RF0R & CAN_RF0R_FMP0) != 0;
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return (canp->can->RFIFO0 & CAN_RFIFO0_RFL0) != 0;
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case 2:
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return (canp->can->RF1R & CAN_RF1R_FMP1) != 0;
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return (canp->can->RFIFO1 & CAN_RFIFO1_RFL1) != 0;
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default:
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return false;
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}
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@ -735,9 +735,9 @@ void can_lld_receive(CANDriver *canp,
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uint32_t rir, rdtr;
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if (mailbox == CAN_ANY_MAILBOX) {
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if ((canp->can->RF0R & CAN_RF0R_FMP0) != 0)
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if ((canp->can->RFIFO0 & CAN_RFIFO0_RFL0) != 0)
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mailbox = 1;
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else if ((canp->can->RF1R & CAN_RF1R_FMP1) != 0)
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else if ((canp->can->RFIFO1 & CAN_RFIFO1_RFL1) != 0)
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mailbox = 2;
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else {
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/* Should not happen, do nothing.*/
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@ -747,33 +747,33 @@ void can_lld_receive(CANDriver *canp,
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switch (mailbox) {
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case 1:
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/* Fetches the message.*/
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rir = canp->can->sFIFOMailBox[0].RIR;
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rdtr = canp->can->sFIFOMailBox[0].RDTR;
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crfp->data32[0] = canp->can->sFIFOMailBox[0].RDLR;
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crfp->data32[1] = canp->can->sFIFOMailBox[0].RDHR;
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rir = canp->can->sFIFOMailBox[0].RFIFOMI;
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rdtr = canp->can->sFIFOMailBox[0].RFIFOMP;
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crfp->data32[0] = canp->can->sFIFOMailBox[0].RFIFOMDATA0;
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crfp->data32[1] = canp->can->sFIFOMailBox[0].RFIFOMDATA1;
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/* Releases the mailbox.*/
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canp->can->RF0R = CAN_RF0R_RFOM0;
|
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canp->can->RFIFO0 = CAN_RFIFO0_RFD0;
|
||||
|
||||
/* If the queue is empty re-enables the interrupt in order to generate
|
||||
events again.*/
|
||||
if ((canp->can->RF0R & CAN_RF0R_FMP0) == 0)
|
||||
canp->can->IER |= CAN_IER_FMPIE0;
|
||||
if ((canp->can->RFIFO0 & CAN_RFIFO0_RFL0) == 0)
|
||||
canp->can->INTEN |= CAN_INTEN_RFNEIE0;
|
||||
break;
|
||||
case 2:
|
||||
/* Fetches the message.*/
|
||||
rir = canp->can->sFIFOMailBox[1].RIR;
|
||||
rdtr = canp->can->sFIFOMailBox[1].RDTR;
|
||||
crfp->data32[0] = canp->can->sFIFOMailBox[1].RDLR;
|
||||
crfp->data32[1] = canp->can->sFIFOMailBox[1].RDHR;
|
||||
rir = canp->can->sFIFOMailBox[1].RFIFOMI;
|
||||
rdtr = canp->can->sFIFOMailBox[1].RFIFOMP;
|
||||
crfp->data32[0] = canp->can->sFIFOMailBox[1].RFIFOMDATA0;
|
||||
crfp->data32[1] = canp->can->sFIFOMailBox[1].RFIFOMDATA1;
|
||||
|
||||
/* Releases the mailbox.*/
|
||||
canp->can->RF1R = CAN_RF1R_RFOM1;
|
||||
canp->can->RFIFO1 = CAN_RFIFO1_RFD1;
|
||||
|
||||
/* If the queue is empty re-enables the interrupt in order to generate
|
||||
events again.*/
|
||||
if ((canp->can->RF1R & CAN_RF1R_FMP1) == 0)
|
||||
canp->can->IER |= CAN_IER_FMPIE1;
|
||||
if ((canp->can->RFIFO1 & CAN_RFIFO1_RFL1) == 0)
|
||||
canp->can->INTEN |= CAN_INTEN_RFNEIE1;
|
||||
break;
|
||||
default:
|
||||
/* Should not happen, do nothing.*/
|
||||
|
|
@ -803,7 +803,7 @@ void can_lld_receive(CANDriver *canp,
|
|||
void can_lld_abort(CANDriver *canp,
|
||||
canmbx_t mailbox) {
|
||||
|
||||
canp->can->TSR = 128U << ((mailbox - 1U) * 8U);
|
||||
canp->can->TSTAT = 128U << ((mailbox - 1U) * 8U);
|
||||
}
|
||||
|
||||
#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
|
||||
|
|
@ -816,7 +816,7 @@ void can_lld_abort(CANDriver *canp,
|
|||
*/
|
||||
void can_lld_sleep(CANDriver *canp) {
|
||||
|
||||
canp->can->MCR |= CAN_MCR_SLEEP;
|
||||
canp->can->CTL |= CAN_CTL_SLPWMOD;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -828,7 +828,7 @@ void can_lld_sleep(CANDriver *canp) {
|
|||
*/
|
||||
void can_lld_wakeup(CANDriver *canp) {
|
||||
|
||||
canp->can->MCR &= ~CAN_MCR_SLEEP;
|
||||
canp->can->CTL &= ~CAN_CTL_SLPWMOD;
|
||||
}
|
||||
#endif /* CAN_USE_SLEEP_MODE */
|
||||
|
||||
|
|
|
|||
|
|
@ -35,10 +35,10 @@
|
|||
* The following macros from the ST header file are replaced with better
|
||||
* equivalents.
|
||||
*/
|
||||
#undef CAN_BTR_BRP
|
||||
#undef CAN_BTR_TS1
|
||||
#undef CAN_BTR_TS2
|
||||
#undef CAN_BTR_SJW
|
||||
#undef CAN_BT_BAUDPSC
|
||||
#undef CAN_BT_BS1
|
||||
#undef CAN_BT_BS2
|
||||
#undef CAN_BT_SJW
|
||||
|
||||
/**
|
||||
* @brief This switch defines whether the driver implementation supports
|
||||
|
|
@ -60,10 +60,10 @@
|
|||
* @name CAN registers helper macros
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BTR_BRP(n) (n) /**< @brief BRP field macro.*/
|
||||
#define CAN_BTR_TS1(n) ((n) << 16) /**< @brief TS1 field macro.*/
|
||||
#define CAN_BTR_TS2(n) ((n) << 20) /**< @brief TS2 field macro.*/
|
||||
#define CAN_BTR_SJW(n) ((n) << 24) /**< @brief SJW field macro.*/
|
||||
#define CAN_BT_BAUDPSC(n) (n) /**< @brief BRP field macro.*/
|
||||
#define CAN_BT_BS1(n) ((n) << 16) /**< @brief TS1 field macro.*/
|
||||
#define CAN_BT_BS2(n) ((n) << 20) /**< @brief TS2 field macro.*/
|
||||
#define CAN_BT_SJW(n) ((n) << 24) /**< @brief SJW field macro.*/
|
||||
|
||||
#define CAN_IDE_STD 0 /**< @brief Standard id. */
|
||||
#define CAN_IDE_EXT 1 /**< @brief Extended id. */
|
||||
|
|
@ -250,19 +250,19 @@ typedef struct {
|
|||
uint32_t filter:16;
|
||||
/**
|
||||
* @brief Filter mode.
|
||||
* @note This bit represent the CAN_FM1R register bit associated to this
|
||||
* @note This bit represent the CAN_FMCFG register bit associated to this
|
||||
* filter (0=mask mode, 1=list mode).
|
||||
*/
|
||||
uint32_t mode:1;
|
||||
/**
|
||||
* @brief Filter scale.
|
||||
* @note This bit represent the CAN_FS1R register bit associated to this
|
||||
* @note This bit represent the CAN_FSCFG register bit associated to this
|
||||
* filter (0=16 bits mode, 1=32 bits mode).
|
||||
*/
|
||||
uint32_t scale:1;
|
||||
/**
|
||||
* @brief Filter mode.
|
||||
* @note This bit represent the CAN_FFA1R register bit associated to this
|
||||
* @note This bit represent the CAN_FAFIFO register bit associated to this
|
||||
* filter, must be set to zero in this version of the driver.
|
||||
*/
|
||||
uint32_t assignment:1;
|
||||
|
|
@ -281,17 +281,17 @@ typedef struct {
|
|||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief CAN MCR register initialization data.
|
||||
* @brief CAN CTL register initialization data.
|
||||
* @note Some bits in this register are enforced by the driver regardless
|
||||
* their status in this field.
|
||||
*/
|
||||
uint32_t mcr;
|
||||
uint32_t ctl;
|
||||
/**
|
||||
* @brief CAN BTR register initialization data.
|
||||
* @brief CAN BT register initialization data.
|
||||
* @note Some bits in this register are enforced by the driver regardless
|
||||
* their status in this field.
|
||||
*/
|
||||
uint32_t btr;
|
||||
uint32_t bt;
|
||||
} CANConfig;
|
||||
|
||||
/**
|
||||
|
|
|
|||
File diff suppressed because it is too large
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Reference in New Issue