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Rename I2C registers, add fast mode plus register

This commit is contained in:
Stefan Kerkmann 2021-03-25 17:10:37 +01:00
parent 5a3ca17dd3
commit 0058d3df0b
3 changed files with 302 additions and 296 deletions
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176
os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.c
View File

@ -55,30 +55,30 @@
/*===========================================================================*/ /*===========================================================================*/
#define I2C_EV5_MASTER_MODE_SELECT \ #define I2C_EV5_MASTER_MODE_SELECT \
((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_SB)) ((uint32_t)(((I2C_STAT1_MASTER | I2C_STAT1_I2CBSY) << 16) | I2C_STAT0_SBSEND))
#define I2C_EV5_MASTER_MODE_SELECT_NO_BUSY \ #define I2C_EV5_MASTER_MODE_SELECT_NO_BUSY \
((uint32_t)((I2C_SR2_MSL << 16) | I2C_SR1_SB)) ((uint32_t)((I2C_STAT1_MASTER << 16) | I2C_STAT0_SBSEND))
#define I2C_EV6_MASTER_TRA_MODE_SELECTED \ #define I2C_EV6_MASTER_TRA_MODE_SELECTED \
((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | \ ((uint32_t)(((I2C_STAT1_MASTER | I2C_STAT1_I2CBSY | I2C_STAT1_TR) << 16) | \
I2C_SR1_ADDR | I2C_SR1_TXE)) I2C_STAT0_ADDSEND | I2C_STAT0_TBE))
#define I2C_EV6_MASTER_REC_MODE_SELECTED \ #define I2C_EV6_MASTER_REC_MODE_SELECTED \
((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY)<< 16) | I2C_SR1_ADDR)) ((uint32_t)(((I2C_STAT1_MASTER | I2C_STAT1_I2CBSY)<< 16) | I2C_STAT0_ADDSEND))
#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED \ #define I2C_EV8_2_MASTER_BYTE_TRANSMITTED \
((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | \ ((uint32_t)(((I2C_STAT1_MASTER | I2C_STAT1_I2CBSY | I2C_STAT1_TR) << 16) | \
I2C_SR1_BTF | I2C_SR1_TXE)) I2C_STAT0_BTC | I2C_STAT0_TBE))
#define I2C_EV9_MASTER_ADD10 \ #define I2C_EV9_MASTER_ADD10 \
((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_ADD10)) ((uint32_t)(((I2C_STAT1_MASTER | I2C_STAT1_I2CBSY) << 16) | I2C_STAT0_ADD10SEND))
#define I2C_EV_MASK 0x00FFFFFF #define I2C_EV_MASK 0x00FFFFFF
#define I2C_ERROR_MASK \ #define I2C_ERROR_MASK \
((uint16_t)(I2C_SR1_BERR | I2C_SR1_ARLO | I2C_SR1_AF | I2C_SR1_OVR | \ ((uint16_t)(I2C_STAT0_BERR | I2C_STAT0_LOSTARB | I2C_STAT0_AERR | I2C_STAT0_OUERR | \
I2C_SR1_PECERR | I2C_SR1_TIMEOUT | I2C_SR1_SMBALERT)) I2C_STAT0_PECERR | I2C_STAT0_SMBTO | I2C_STAT0_SMBALT))
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported variables. */ /* Driver exported variables. */
@ -113,10 +113,10 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) {
I2C_TypeDef *dp = i2cp->i2c; I2C_TypeDef *dp = i2cp->i2c;
/* Stops the I2C peripheral.*/ /* Stops the I2C peripheral.*/
dp->CR1 = I2C_CR1_SWRST; dp->CTL0 = I2C_CTL0_SRESET;
dp->CR1 = 0; dp->CTL0 = 0;
dp->CR2 = 0; dp->CTL1 = 0;
dp->SR1 = 0; dp->STAT0 = 0;
/* Stops the associated DMA streams.*/ /* Stops the associated DMA streams.*/
dmaStreamDisable(i2cp->dmatx); dmaStreamDisable(i2cp->dmatx);
@ -132,7 +132,7 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) {
*/ */
static void i2c_lld_set_clock(I2CDriver *i2cp) { static void i2c_lld_set_clock(I2CDriver *i2cp) {
I2C_TypeDef *dp = i2cp->i2c; I2C_TypeDef *dp = i2cp->i2c;
uint16_t regCCR, clock_div; uint16_t regCKCFG, clock_div;
int32_t clock_speed = i2cp->config->clock_speed; int32_t clock_speed = i2cp->config->clock_speed;
i2cdutycycle_t duty = i2cp->config->duty_cycle; i2cdutycycle_t duty = i2cp->config->duty_cycle;
@ -141,12 +141,12 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
(clock_speed <= 400000)); (clock_speed <= 400000));
/* CR2 Configuration.*/ /* CR2 Configuration.*/
dp->CR2 &= (uint16_t)~I2C_CR2_FREQ; dp->CTL1 &= (uint16_t)~I2C_CTL1_I2CCLK;
dp->CR2 |= (uint16_t)I2C_CLK_FREQ; dp->CTL1 |= (uint16_t)I2C_CLK_FREQ;
/* CCR Configuration.*/ /* CCR Configuration.*/
regCCR = 0; regCKCFG = 0;
clock_div = I2C_CCR_CCR; clock_div = I2C_CKCFG_CLKC;
if (clock_speed <= 100000) { if (clock_speed <= 100000) {
/* Configure clock_div in standard mode.*/ /* Configure clock_div in standard mode.*/
@ -159,10 +159,10 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
osalDbgAssert(clock_div >= 0x04, osalDbgAssert(clock_div >= 0x04,
"clock divider less then 0x04 not allowed"); "clock divider less then 0x04 not allowed");
regCCR |= (clock_div & I2C_CCR_CCR); regCKCFG |= (clock_div & I2C_CKCFG_CLKC);
/* Sets the Maximum Rise Time for standard mode.*/ /* Sets the Maximum Rise Time for standard mode.*/
dp->TRISE = I2C_CLK_FREQ + 1; dp->RT = I2C_CLK_FREQ + 1;
} }
else if (clock_speed <= 400000) { else if (clock_speed <= 400000) {
/* Configure clock_div in fast mode.*/ /* Configure clock_div in fast mode.*/
@ -181,20 +181,20 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
osalDbgAssert((GD32_PCLK1 % (clock_speed * 25)) == 0, osalDbgAssert((GD32_PCLK1 % (clock_speed * 25)) == 0,
"PCLK1 must be divided without remainder"); "PCLK1 must be divided without remainder");
clock_div = (uint16_t)(GD32_PCLK1 / (clock_speed * 25)); clock_div = (uint16_t)(GD32_PCLK1 / (clock_speed * 25));
regCCR |= I2C_CCR_DUTY; regCKCFG |= I2C_CKCFG_DTCY;
} }
osalDbgAssert(clock_div >= 0x01, osalDbgAssert(clock_div >= 0x01,
"clock divider less then 0x04 not allowed"); "clock divider less then 0x04 not allowed");
regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR)); regCKCFG |= (I2C_CKCFG_FAST | (clock_div & I2C_CKCFG_CLKC));
/* Sets the Maximum Rise Time for fast mode.*/ /* Sets the Maximum Rise Time for fast mode.*/
dp->TRISE = (I2C_CLK_FREQ * 300 / 1000) + 1; dp->RT = (I2C_CLK_FREQ * 300 / 1000) + 1;
} }
osalDbgAssert((clock_div <= I2C_CCR_CCR), "the selected clock is too low"); osalDbgAssert((clock_div <= I2C_CKCFG_CLKC), "the selected clock is too low");
dp->CCR = regCCR; dp->CKCFG = regCKCFG;
} }
/** /**
@ -209,20 +209,20 @@ static void i2c_lld_set_opmode(I2CDriver *i2cp) {
i2copmode_t opmode = i2cp->config->op_mode; i2copmode_t opmode = i2cp->config->op_mode;
uint16_t regCR1; uint16_t regCR1;
regCR1 = dp->CR1; regCR1 = dp->CTL0;
switch (opmode) { switch (opmode) {
case OPMODE_I2C: case OPMODE_I2C:
regCR1 &= (uint16_t)~(I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); regCR1 &= (uint16_t)~(I2C_CTL0_SMBEN|I2C_CTL0_SMBSEL);
break; break;
case OPMODE_SMBUS_DEVICE: case OPMODE_SMBUS_DEVICE:
regCR1 |= I2C_CR1_SMBUS; regCR1 |= I2C_CTL0_SMBEN;
regCR1 &= (uint16_t)~(I2C_CR1_SMBTYPE); regCR1 &= (uint16_t)~(I2C_CTL0_SMBSEL);
break; break;
case OPMODE_SMBUS_HOST: case OPMODE_SMBUS_HOST:
regCR1 |= (I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); regCR1 |= (I2C_CTL0_SMBEN|I2C_CTL0_SMBSEL);
break; break;
} }
dp->CR1 = regCR1; dp->CTL0 = regCR1;
} }
/** /**
@ -234,8 +234,8 @@ static void i2c_lld_set_opmode(I2CDriver *i2cp) {
*/ */
static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) { static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
I2C_TypeDef *dp = i2cp->i2c; I2C_TypeDef *dp = i2cp->i2c;
uint32_t regSR2 = dp->SR2; uint32_t regSR2 = dp->STAT1;
uint32_t event = dp->SR1; uint32_t event = dp->STAT0;
/*for(int32_t i = 0; i < 20; i++){ /*for(int32_t i = 0; i < 20; i++){
__asm__ volatile ("nop"); __asm__ volatile ("nop");
@ -249,57 +249,57 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
case I2C_EV5_MASTER_MODE_SELECT_NO_BUSY: case I2C_EV5_MASTER_MODE_SELECT_NO_BUSY:
if ((i2cp->addr >> 8) > 0) { if ((i2cp->addr >> 8) > 0) {
/* 10-bit address: 1 1 1 1 0 X X R/W */ /* 10-bit address: 1 1 1 1 0 X X R/W */
dp->DR = 0xF0 | (0x6 & (i2cp->addr >> 8)) | (0x1 & i2cp->addr); dp->DATA = 0xF0 | (0x6 & (i2cp->addr >> 8)) | (0x1 & i2cp->addr);
} else { } else {
dp->DR = i2cp->addr; dp->DATA = i2cp->addr;
} }
break; break;
case I2C_EV9_MASTER_ADD10: case I2C_EV9_MASTER_ADD10:
/* Set second addr byte (10-bit addressing)*/ /* Set second addr byte (10-bit addressing)*/
dp->DR = (0xFF & (i2cp->addr >> 1)); dp->DATA = (0xFF & (i2cp->addr >> 1));
break; break;
case I2C_EV6_MASTER_REC_MODE_SELECTED: case I2C_EV6_MASTER_REC_MODE_SELECTED:
dp->CR2 &= ~I2C_CR2_ITEVTEN; dp->CTL1 &= ~I2C_CTL1_EVIE;
/* Clear address flags before dma enable */ /* Clear address flags before dma enable */
if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10)){ if (event & (I2C_STAT0_ADDSEND | I2C_STAT0_ADD10SEND)){
(void)dp->SR1; (void)dp->STAT0;
(void)dp->SR2; (void)dp->STAT1;
} }
dp->CR2 |= I2C_CR2_DMAEN; dp->CTL1 |= I2C_CTL1_DMAON;
dmaStreamEnable(i2cp->dmarx); dmaStreamEnable(i2cp->dmarx);
dp->CR2 |= I2C_CR2_LAST; /* Needed in receiver mode. */ dp->CTL1 |= I2C_CTL1_DMALST; /* Needed in receiver mode. */
if (dmaStreamGetTransactionSize(i2cp->dmarx) < 2) if (dmaStreamGetTransactionSize(i2cp->dmarx) < 2)
dp->CR1 &= ~I2C_CR1_ACK; dp->CTL0 &= ~I2C_CTL0_ACKEN;
break; break;
case I2C_EV6_MASTER_TRA_MODE_SELECTED: case I2C_EV6_MASTER_TRA_MODE_SELECTED:
dp->CR2 &= ~I2C_CR2_ITEVTEN; dp->CTL1 &= ~I2C_CTL1_EVIE;
/* Clear address flags before dma enable */ /* Clear address flags before dma enable */
if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10)){ if (event & (I2C_STAT0_ADDSEND | I2C_STAT0_ADD10SEND)){
(void)dp->SR1; (void)dp->STAT0;
(void)dp->SR2; (void)dp->STAT1;
} }
dp->CR2 |= I2C_CR2_DMAEN; dp->CTL1 |= I2C_CTL1_DMAON;
dmaStreamEnable(i2cp->dmatx); dmaStreamEnable(i2cp->dmatx);
break; break;
case I2C_EV8_2_MASTER_BYTE_TRANSMITTED: case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
/* Catches BTF event after the end of transmission.*/ /* Catches BTF event after the end of transmission.*/
(void)dp->DR; /* clear BTF.*/ (void)dp->DATA; /* clear BTF.*/
if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) { if (dmaStreamGetTransactionSize(i2cp->dmarx) > 0) {
/* Starts "read after write" operation, LSB = 1 -> receive.*/ /* Starts "read after write" operation, LSB = 1 -> receive.*/
i2cp->addr |= 0x01; i2cp->addr |= 0x01;
dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK; dp->CTL0 |= I2C_CTL0_START | I2C_CTL0_ACKEN;
return; return;
} }
dp->CR2 &= ~I2C_CR2_ITEVTEN; dp->CTL1 &= ~I2C_CTL1_EVIE;
dp->CR1 |= I2C_CR1_STOP; dp->CTL0 |= I2C_CTL0_STOP;
_i2c_wakeup_isr(i2cp); _i2c_wakeup_isr(i2cp);
break; break;
default: default:
break; break;
} }
if (event & (I2C_SR1_ADDR | I2C_SR1_ADD10)){ if (event & (I2C_STAT0_ADDSEND | I2C_STAT0_ADD10SEND)){
(void)dp->SR1; (void)dp->STAT0;
(void)dp->SR2; (void)dp->STAT1;
} }
} }
@ -325,9 +325,9 @@ static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) {
dmaStreamDisable(i2cp->dmarx); dmaStreamDisable(i2cp->dmarx);
dp->CR2 &= ~I2C_CR2_LAST; dp->CTL1 &= ~I2C_CTL1_DMALST;
dp->CR1 &= ~I2C_CR1_ACK; dp->CTL0 &= ~I2C_CTL0_ACKEN;
dp->CR1 |= I2C_CR1_STOP; dp->CTL0 |= I2C_CTL0_STOP;
_i2c_wakeup_isr(i2cp); _i2c_wakeup_isr(i2cp);
} }
@ -354,7 +354,7 @@ static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) {
/* Enables interrupts to catch BTF event meaning transmission part complete. /* Enables interrupts to catch BTF event meaning transmission part complete.
Interrupt handler will decide to generate STOP or to begin receiving part Interrupt handler will decide to generate STOP or to begin receiving part
of R/W transaction itself.*/ of R/W transaction itself.*/
dp->CR2 |= I2C_CR2_ITEVTEN; dp->CTL1 |= I2C_CTL1_EVIE;
} }
/** /**
@ -373,32 +373,32 @@ static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) {
i2cp->errors = I2C_NO_ERROR; i2cp->errors = I2C_NO_ERROR;
if (sr & I2C_SR1_BERR) { /* Bus error. */ if (sr & I2C_STAT0_BERR) { /* Bus error. */
i2cp->errors |= I2C_BUS_ERROR; i2cp->errors |= I2C_BUS_ERROR;
/* Errata 2.4.6 for STM32F40x, Spurious Bus Error detection in /* Errata 2.4.6 for STM32F40x, Spurious Bus Error detection in
Master mode.*/ Master mode.*/
i2cp->i2c->SR1 &= ~I2C_SR1_BERR; i2cp->i2c->STAT0 &= ~I2C_STAT0_BERR;
} }
if (sr & I2C_SR1_ARLO) /* Arbitration lost. */ if (sr & I2C_STAT0_LOSTARB) /* Arbitration lost. */
i2cp->errors |= I2C_ARBITRATION_LOST; i2cp->errors |= I2C_ARBITRATION_LOST;
if (sr & I2C_SR1_AF) { /* Acknowledge fail. */ if (sr & I2C_STAT0_AERR) { /* Acknowledge fail. */
i2cp->i2c->CR2 &= ~I2C_CR2_ITEVTEN; i2cp->i2c->CTL1 &= ~I2C_CTL1_EVIE;
i2cp->i2c->CR1 |= I2C_CR1_STOP; /* Setting stop bit. */ i2cp->i2c->CTL0 |= I2C_CTL0_STOP; /* Setting stop bit. */
i2cp->errors |= I2C_ACK_FAILURE; i2cp->errors |= I2C_ACK_FAILURE;
} }
if (sr & I2C_SR1_OVR) /* Overrun. */ if (sr & I2C_STAT0_OUERR) /* Overrun. */
i2cp->errors |= I2C_OVERRUN; i2cp->errors |= I2C_OVERRUN;
if (sr & I2C_SR1_TIMEOUT) /* SMBus Timeout. */ if (sr & I2C_STAT0_SMBTO) /* SMBus Timeout. */
i2cp->errors |= I2C_TIMEOUT; i2cp->errors |= I2C_TIMEOUT;
if (sr & I2C_SR1_PECERR) /* PEC error. */ if (sr & I2C_STAT0_PECERR) /* PEC error. */
i2cp->errors |= I2C_PEC_ERROR; i2cp->errors |= I2C_PEC_ERROR;
if (sr & I2C_SR1_SMBALERT) /* SMBus alert. */ if (sr & I2C_STAT0_SMBALT) /* SMBus alert. */
i2cp->errors |= I2C_SMB_ALERT; i2cp->errors |= I2C_SMB_ALERT;
/* If some error has been identified then sends wakes the waiting thread.*/ /* If some error has been identified then sends wakes the waiting thread.*/
@ -429,11 +429,11 @@ OSAL_IRQ_HANDLER(GD32_I2C1_EVENT_HANDLER) {
* @brief I2C1 error interrupt handler. * @brief I2C1 error interrupt handler.
*/ */
OSAL_IRQ_HANDLER(GD32_I2C1_ERROR_HANDLER) { OSAL_IRQ_HANDLER(GD32_I2C1_ERROR_HANDLER) {
uint16_t sr = I2CD1.i2c->SR1; uint16_t sr = I2CD1.i2c->STAT0;
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
I2CD1.i2c->SR1 = ~(sr & I2C_ERROR_MASK); I2CD1.i2c->STAT0 = ~(sr & I2C_ERROR_MASK);
i2c_lld_serve_error_interrupt(&I2CD1, sr); i2c_lld_serve_error_interrupt(&I2CD1, sr);
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
@ -461,11 +461,11 @@ OSAL_IRQ_HANDLER(GD32_I2C2_EVENT_HANDLER) {
* @notapi * @notapi
*/ */
OSAL_IRQ_HANDLER(GD32_I2C2_ERROR_HANDLER) { OSAL_IRQ_HANDLER(GD32_I2C2_ERROR_HANDLER) {
uint16_t sr = I2CD2.i2c->SR1; uint16_t sr = I2CD2.i2c->STAT0;
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
I2CD2.i2c->SR1 = ~(sr & I2C_ERROR_MASK); I2CD2.i2c->STAT0 = ~(sr & I2C_ERROR_MASK);
i2c_lld_serve_error_interrupt(&I2CD2, sr); i2c_lld_serve_error_interrupt(&I2CD2, sr);
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
@ -576,21 +576,21 @@ void i2c_lld_start(I2CDriver *i2cp) {
} }
/* I2C registers pointed by the DMA.*/ /* I2C registers pointed by the DMA.*/
dmaStreamSetPeripheral(i2cp->dmarx, &dp->DR); dmaStreamSetPeripheral(i2cp->dmarx, &dp->DATA);
dmaStreamSetPeripheral(i2cp->dmatx, &dp->DR); dmaStreamSetPeripheral(i2cp->dmatx, &dp->DATA);
/* Reset i2c peripheral.*/ /* Reset i2c peripheral.*/
dp->CR1 = I2C_CR1_SWRST; dp->CTL0 = I2C_CTL0_SRESET;
dp->CR1 = 0; dp->CTL0 = 0;
dp->CR2 = 0; dp->CTL1 = 0;
dp->SR1 = 0; dp->STAT0 = 0;
dp->CR2 = I2C_CR2_ITERREN; dp->CTL1 = I2C_CTL1_ERRIE;
/* Setup I2C parameters.*/ /* Setup I2C parameters.*/
i2c_lld_set_clock(i2cp); i2c_lld_set_clock(i2cp);
i2c_lld_set_opmode(i2cp); i2c_lld_set_opmode(i2cp);
/* Ready to go.*/ /* Ready to go.*/
dp->CR1 |= I2C_CR1_PE; dp->CTL0 |= I2C_CTL0_I2CEN;
} }
/** /**
@ -689,7 +689,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
/* If the bus is not busy then the operation can continue, note, the /* If the bus is not busy then the operation can continue, note, the
loop is exited in the locked state.*/ loop is exited in the locked state.*/
if (!(dp->SR2 & I2C_SR2_BUSY) && !(dp->CR1 & I2C_CR1_STOP)) if (!(dp->STAT1 & I2C_STAT1_I2CBSY) && !(dp->CTL0 & I2C_CTL0_STOP))
break; break;
/* If the system time went outside the allowed window then a timeout /* If the system time went outside the allowed window then a timeout
@ -703,8 +703,8 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
} }
/* Starts the operation.*/ /* Starts the operation.*/
dp->CR2 |= I2C_CR2_ITEVTEN; dp->CTL1 |= I2C_CTL1_EVIE;
dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK; dp->CTL0 |= I2C_CTL0_START | I2C_CTL0_ACKEN;
/* Waits for the operation completion or a timeout.*/ /* Waits for the operation completion or a timeout.*/
msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
@ -782,7 +782,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
/* If the bus is not busy then the operation can continue, note, the /* If the bus is not busy then the operation can continue, note, the
loop is exited in the locked state.*/ loop is exited in the locked state.*/
if (!(dp->SR2 & I2C_SR2_BUSY) && !(dp->CR1 & I2C_CR1_STOP)) if (!(dp->STAT1 & I2C_STAT1_I2CBSY) && !(dp->CTL0 & I2C_CTL0_STOP))
break; break;
/* If the system time went outside the allowed window then a timeout /* If the system time went outside the allowed window then a timeout
@ -797,8 +797,8 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
} }
/* Starts the operation.*/ /* Starts the operation.*/
dp->CR2 |= I2C_CR2_ITEVTEN; dp->CTL1 |= I2C_CTL1_EVIE;
dp->CR1 |= I2C_CR1_START; dp->CTL0 |= I2C_CTL0_START;
/* Waits for the operation completion or a timeout.*/ /* Waits for the operation completion or a timeout.*/
msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);

4
os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.h
View File

@ -260,8 +260,8 @@ struct I2CDriver {
*/ */
mutex_t mutex; mutex_t mutex;
#endif /* I2C_USE_MUTUAL_EXCLUSION */ #endif /* I2C_USE_MUTUAL_EXCLUSION */
#if defined(I2C_DRIVER_EXT_FIELDS) #if defined(I2C_DATAIVER_EXT_FIELDS)
I2C_DRIVER_EXT_FIELDS I2C_DATAIVER_EXT_FIELDS
#endif #endif
/* End of the mandatory fields.*/ /* End of the mandatory fields.*/
/** /**

418
os/hal/ports/GD/GD32VF103/stm32f105xc.h
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@ -385,15 +385,16 @@ typedef struct
typedef struct typedef struct
{ {
__IO uint32_t CR1; __IO uint32_t CTL0;
__IO uint32_t CR2; __IO uint32_t CTL1;
__IO uint32_t OAR1; __IO uint32_t SADDR0;
__IO uint32_t OAR2; __IO uint32_t SADDR1;
__IO uint32_t DR; __IO uint32_t DATA;
__IO uint32_t SR1; __IO uint32_t STAT0;
__IO uint32_t SR2; __IO uint32_t STAT1;
__IO uint32_t CCR; __IO uint32_t CKCFG;
__IO uint32_t TRISE; __IO uint32_t RT;
__IO uint32_t FMPCFG;
} I2C_TypeDef; } I2C_TypeDef;
/** /**
@ -11879,214 +11880,219 @@ typedef struct
/* */ /* */
/******************************************************************************/ /******************************************************************************/
/******************* Bit definition for I2C_CR1 register ********************/ /******************* Bit definition for I2C_CTL0 register ********************/
#define I2C_CR1_PE_Pos (0U) #define I2C_CTL0_I2CEN_Pos (0U)
#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ #define I2C_CTL0_I2CEN_Msk (0x1U << I2C_CTL0_I2CEN_Pos) /*!< 0x00000001 */
#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ #define I2C_CTL0_I2CEN I2C_CTL0_I2CEN_Msk /*!< Peripheral Enable */
#define I2C_CR1_SMBUS_Pos (1U) #define I2C_CTL0_SMBEN_Pos (1U)
#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ #define I2C_CTL0_SMBEN_Msk (0x1U << I2C_CTL0_SMBEN_Pos) /*!< 0x00000002 */
#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ #define I2C_CTL0_SMBEN I2C_CTL0_SMBEN_Msk /*!< SMBus Mode */
#define I2C_CR1_SMBTYPE_Pos (3U) #define I2C_CTL0_SMBSEL_Pos (3U)
#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ #define I2C_CTL0_SMBSEL_Msk (0x1U << I2C_CTL0_SMBSEL_Pos) /*!< 0x00000008 */
#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ #define I2C_CTL0_SMBSEL I2C_CTL0_SMBSEL_Msk /*!< SMBus Type */
#define I2C_CR1_ENARP_Pos (4U) #define I2C_CTL0_ARPEN_Pos (4U)
#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ #define I2C_CTL0_ARPEN_Msk (0x1U << I2C_CTL0_ARPEN_Pos) /*!< 0x00000010 */
#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ #define I2C_CTL0_ARPEN I2C_CTL0_ARPEN_Msk /*!< ARP Enable */
#define I2C_CR1_ENPEC_Pos (5U) #define I2C_CTL0_PECTRANSEN_Pos (5U)
#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ #define I2C_CTL0_PECTRANSEN_Msk (0x1U << I2C_CTL0_PECTRANSEN_Pos) /*!< 0x00000020 */
#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ #define I2C_CTL0_PECTRANSEN I2C_CTL0_PECTRANSEN_Msk /*!< PEC Enable */
#define I2C_CR1_ENGC_Pos (6U) #define I2C_CTL0_GCEN_Pos (6U)
#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ #define I2C_CTL0_GCEN_Msk (0x1U << I2C_CTL0_GCEN_Pos) /*!< 0x00000040 */
#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ #define I2C_CTL0_GCEN I2C_CTL0_GCEN_Msk /*!< General Call Enable */
#define I2C_CR1_NOSTRETCH_Pos (7U) #define I2C_CTL0_SS_Pos (7U)
#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ #define I2C_CTL0_SS_Msk (0x1U << I2C_CTL0_SS_Pos) /*!< 0x00000080 */
#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ #define I2C_CTL0_SS I2C_CTL0_SS_Msk /*!< Clock Stretching Disable (Slave mode) */
#define I2C_CR1_START_Pos (8U) #define I2C_CTL0_START_Pos (8U)
#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */ #define I2C_CTL0_START_Msk (0x1U << I2C_CTL0_START_Pos) /*!< 0x00000100 */
#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ #define I2C_CTL0_START I2C_CTL0_START_Msk /*!< Start Generation */
#define I2C_CR1_STOP_Pos (9U) #define I2C_CTL0_STOP_Pos (9U)
#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ #define I2C_CTL0_STOP_Msk (0x1U << I2C_CTL0_STOP_Pos) /*!< 0x00000200 */
#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ #define I2C_CTL0_STOP I2C_CTL0_STOP_Msk /*!< Stop Generation */
#define I2C_CR1_ACK_Pos (10U) #define I2C_CTL0_ACKEN_Pos (10U)
#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ #define I2C_CTL0_ACKEN_Msk (0x1U << I2C_CTL0_ACKEN_Pos) /*!< 0x00000400 */
#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ #define I2C_CTL0_ACKEN I2C_CTL0_ACKEN_Msk /*!< Acknowledge Enable */
#define I2C_CR1_POS_Pos (11U) #define I2C_CTL0_POAP_Pos (11U)
#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */ #define I2C_CTL0_POAP_Msk (0x1U << I2C_CTL0_POAP_Pos) /*!< 0x00000800 */
#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ #define I2C_CTL0_POAP I2C_CTL0_POAP_Msk /*!< Acknowledge/PEC Position (for data reception) */
#define I2C_CR1_PEC_Pos (12U) #define I2C_CTL0_I2CENC_Pos (12U)
#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ #define I2C_CTL0_I2CENC_Msk (0x1U << I2C_CTL0_I2CENC_Pos) /*!< 0x00001000 */
#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ #define I2C_CTL0_I2CENC I2C_CTL0_I2CENC_Msk /*!< Packet Error Checking */
#define I2C_CR1_ALERT_Pos (13U) #define I2C_CTL0_SALT_Pos (13U)
#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ #define I2C_CTL0_SALT_Msk (0x1U << I2C_CTL0_SALT_Pos) /*!< 0x00002000 */
#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ #define I2C_CTL0_SALT I2C_CTL0_SALT_Msk /*!< SMBus Alert */
#define I2C_CR1_SWRST_Pos (15U) #define I2C_CTL0_SRESET_Pos (15U)
#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ #define I2C_CTL0_SRESET_Msk (0x1U << I2C_CTL0_SRESET_Pos) /*!< 0x00008000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ #define I2C_CTL0_SRESET I2C_CTL0_SRESET_Msk /*!< Software Reset */
/******************* Bit definition for I2C_CR2 register ********************/ /******************* Bit definition for I2C_CTL1 register ********************/
#define I2C_CR2_FREQ_Pos (0U) #define I2C_CTL1_I2CCLK_Pos (0U)
#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ #define I2C_CTL1_I2CCLK_Msk (0x3FU << I2C_CTL1_I2CCLK_Pos) /*!< 0x0000003F */
#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ #define I2C_CTL1_I2CCLK I2C_CTL1_I2CCLK_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ #define I2C_CTL1_I2CCLK_0 (0x01U << I2C_CTL1_I2CCLK_Pos) /*!< 0x00000001 */
#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ #define I2C_CTL1_I2CCLK_1 (0x02U << I2C_CTL1_I2CCLK_Pos) /*!< 0x00000002 */
#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ #define I2C_CTL1_I2CCLK_2 (0x04U << I2C_CTL1_I2CCLK_Pos) /*!< 0x00000004 */
#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ #define I2C_CTL1_I2CCLK_3 (0x08U << I2C_CTL1_I2CCLK_Pos) /*!< 0x00000008 */
#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ #define I2C_CTL1_I2CCLK_4 (0x10U << I2C_CTL1_I2CCLK_Pos) /*!< 0x00000010 */
#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ #define I2C_CTL1_I2CCLK_5 (0x20U << I2C_CTL1_I2CCLK_Pos) /*!< 0x00000020 */
#define I2C_CR2_ITERREN_Pos (8U) #define I2C_CTL1_ERRIE_Pos (8U)
#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ #define I2C_CTL1_ERRIE_Msk (0x1U << I2C_CTL1_ERRIE_Pos) /*!< 0x00000100 */
#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ #define I2C_CTL1_ERRIE I2C_CTL1_ERRIE_Msk /*!< Error Interrupt Enable */
#define I2C_CR2_ITEVTEN_Pos (9U) #define I2C_CTL1_EVIE_Pos (9U)
#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ #define I2C_CTL1_EVIE_Msk (0x1U << I2C_CTL1_EVIE_Pos) /*!< 0x00000200 */
#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ #define I2C_CTL1_EVIE I2C_CTL1_EVIE_Msk /*!< Event Interrupt Enable */
#define I2C_CR2_ITBUFEN_Pos (10U) #define I2C_CTL1_BUFIE_Pos (10U)
#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ #define I2C_CTL1_BUFIE_Msk (0x1U << I2C_CTL1_BUFIE_Pos) /*!< 0x00000400 */
#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ #define I2C_CTL1_BUFIE I2C_CTL1_BUFIE_Msk /*!< Buffer Interrupt Enable */
#define I2C_CR2_DMAEN_Pos (11U) #define I2C_CTL1_DMAON_Pos (11U)
#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ #define I2C_CTL1_DMAON_Msk (0x1U << I2C_CTL1_DMAON_Pos) /*!< 0x00000800 */
#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ #define I2C_CTL1_DMAON I2C_CTL1_DMAON_Msk /*!< DMA Requests Enable */
#define I2C_CR2_LAST_Pos (12U) #define I2C_CTL1_DMALST_Pos (12U)
#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ #define I2C_CTL1_DMALST_Msk (0x1U << I2C_CTL1_DMALST_Pos) /*!< 0x00001000 */
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ #define I2C_CTL1_DMALST I2C_CTL1_DMALST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/ /******************* Bit definition for I2C_SADDR0 register *******************/
#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */ #define I2C_SADDR0_ADDRESS1_7 0x000000FEU /*!< Interface Address */
#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */ #define I2C_SADDR0_ADDRESS8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U) #define I2C_SADDR0_ADDRESS0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ #define I2C_SADDR0_ADDRESS0_Msk (0x1U << I2C_SADDR0_ADDRESS0_Pos) /*!< 0x00000001 */
#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ #define I2C_SADDR0_ADDRESS0 I2C_SADDR0_ADDRESS0_Msk /*!< Bit 0 */
#define I2C_OAR1_ADD1_Pos (1U) #define I2C_SADDR0_ADDRESS1_Pos (1U)
#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ #define I2C_SADDR0_ADDRESS1_Msk (0x1U << I2C_SADDR0_ADDRESS1_Pos) /*!< 0x00000002 */
#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ #define I2C_SADDR0_ADDRESS1 I2C_SADDR0_ADDRESS1_Msk /*!< Bit 1 */
#define I2C_OAR1_ADD2_Pos (2U) #define I2C_SADDR0_ADDRESS2_Pos (2U)
#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ #define I2C_SADDR0_ADDRESS2_Msk (0x1U << I2C_SADDR0_ADDRESS2_Pos) /*!< 0x00000004 */
#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ #define I2C_SADDR0_ADDRESS2 I2C_SADDR0_ADDRESS2_Msk /*!< Bit 2 */
#define I2C_OAR1_ADD3_Pos (3U) #define I2C_SADDR0_ADDRESS3_Pos (3U)
#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ #define I2C_SADDR0_ADDRESS3_Msk (0x1U << I2C_SADDR0_ADDRESS3_Pos) /*!< 0x00000008 */
#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ #define I2C_SADDR0_ADDRESS3 I2C_SADDR0_ADDRESS3_Msk /*!< Bit 3 */
#define I2C_OAR1_ADD4_Pos (4U) #define I2C_SADDR0_ADDRESS4_Pos (4U)
#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ #define I2C_SADDR0_ADDRESS4_Msk (0x1U << I2C_SADDR0_ADDRESS4_Pos) /*!< 0x00000010 */
#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ #define I2C_SADDR0_ADDRESS4 I2C_SADDR0_ADDRESS4_Msk /*!< Bit 4 */
#define I2C_OAR1_ADD5_Pos (5U) #define I2C_SADDR0_ADDRESS5_Pos (5U)
#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ #define I2C_SADDR0_ADDRESS5_Msk (0x1U << I2C_SADDR0_ADDRESS5_Pos) /*!< 0x00000020 */
#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ #define I2C_SADDR0_ADDRESS5 I2C_SADDR0_ADDRESS5_Msk /*!< Bit 5 */
#define I2C_OAR1_ADD6_Pos (6U) #define I2C_SADDR0_ADDRESS6_Pos (6U)
#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ #define I2C_SADDR0_ADDRESS6_Msk (0x1U << I2C_SADDR0_ADDRESS6_Pos) /*!< 0x00000040 */
#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ #define I2C_SADDR0_ADDRESS6 I2C_SADDR0_ADDRESS6_Msk /*!< Bit 6 */
#define I2C_OAR1_ADD7_Pos (7U) #define I2C_SADDR0_ADDRESS7_Pos (7U)
#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ #define I2C_SADDR0_ADDRESS7_Msk (0x1U << I2C_SADDR0_ADDRESS7_Pos) /*!< 0x00000080 */
#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ #define I2C_SADDR0_ADDRESS7 I2C_SADDR0_ADDRESS7_Msk /*!< Bit 7 */
#define I2C_OAR1_ADD8_Pos (8U) #define I2C_SADDR0_ADDRESS8_Pos (8U)
#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ #define I2C_SADDR0_ADDRESS8_Msk (0x1U << I2C_SADDR0_ADDRESS8_Pos) /*!< 0x00000100 */
#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ #define I2C_SADDR0_ADDRESS8 I2C_SADDR0_ADDRESS8_Msk /*!< Bit 8 */
#define I2C_OAR1_ADD9_Pos (9U) #define I2C_SADDR0_ADDRESS9_Pos (9U)
#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ #define I2C_SADDR0_ADDRESS9_Msk (0x1U << I2C_SADDR0_ADDRESS9_Pos) /*!< 0x00000200 */
#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ #define I2C_SADDR0_ADDRESS9 I2C_SADDR0_ADDRESS9_Msk /*!< Bit 9 */
#define I2C_OAR1_ADDMODE_Pos (15U) #define I2C_SADDR0_ADDRESSMODE_Pos (15U)
#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ #define I2C_SADDR0_ADDRESSMODE_Msk (0x1U << I2C_SADDR0_ADDRESSMODE_Pos) /*!< 0x00008000 */
#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ #define I2C_SADDR0_ADDRESSMODE I2C_SADDR0_ADDRESSMODE_Msk /*!< Addressing Mode (Slave mode) */
/******************* Bit definition for I2C_OAR2 register *******************/ /******************* Bit definition for I2C_SADDR1 register *******************/
#define I2C_OAR2_ENDUAL_Pos (0U) #define I2C_SADDR1_DUADEN_Pos (0U)
#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ #define I2C_SADDR1_DUADEN_Msk (0x1U << I2C_SADDR1_DUADEN_Pos) /*!< 0x00000001 */
#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ #define I2C_SADDR1_DUADEN I2C_SADDR1_DUADEN_Msk /*!< Dual addressing mode enable */
#define I2C_OAR2_ADD2_Pos (1U) #define I2C_SADDR1_ADDRESS2_Pos (1U)
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ #define I2C_SADDR1_ADDRESS2_Msk (0x7FU << I2C_SADDR1_ADDRESS2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ #define I2C_SADDR1_ADDRESS2 I2C_SADDR1_ADDRESS2_Msk /*!< Interface address */
/******************** Bit definition for I2C_DR register ********************/ /******************** Bit definition for I2C_DATA register ********************/
#define I2C_DR_DR_Pos (0U) #define I2C_DATA_TRB_Pos (0U)
#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */ #define I2C_DATA_TRB_Msk (0xFFU << I2C_DATA_TRB_Pos) /*!< 0x000000FF */
#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */ #define I2C_DATA_TRB I2C_DATA_TRB_Msk /*!< 8-bit Data Register */
/******************* Bit definition for I2C_SR1 register ********************/ /******************* Bit definition for I2C_STAT0 register ********************/
#define I2C_SR1_SB_Pos (0U) #define I2C_STAT0_SBSEND_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */ #define I2C_STAT0_SBSEND_Msk (0x1U << I2C_STAT0_SBSEND_Pos) /*!< 0x00000001 */
#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ #define I2C_STAT0_SBSEND I2C_STAT0_SBSEND_Msk /*!< Start Bit (Master mode) */
#define I2C_SR1_ADDR_Pos (1U) #define I2C_STAT0_ADDSEND_Pos (1U)
#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ #define I2C_STAT0_ADDSEND_Msk (0x1U << I2C_STAT0_ADDSEND_Pos) /*!< 0x00000002 */
#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ #define I2C_STAT0_ADDSEND I2C_STAT0_ADDSEND_Msk /*!< Address sent (master mode)/matched (slave mode) */
#define I2C_SR1_BTF_Pos (2U) #define I2C_STAT0_BTC_Pos (2U)
#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ #define I2C_STAT0_BTC_Msk (0x1U << I2C_STAT0_BTC_Pos) /*!< 0x00000004 */
#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ #define I2C_STAT0_BTC I2C_STAT0_BTC_Msk /*!< Byte Transfer Finished */
#define I2C_SR1_ADD10_Pos (3U) #define I2C_STAT0_ADD10SEND_Pos (3U)
#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ #define I2C_STAT0_ADD10SEND_Msk (0x1U << I2C_STAT0_ADD10SEND_Pos) /*!< 0x00000008 */
#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ #define I2C_STAT0_ADD10SEND I2C_STAT0_ADD10SEND_Msk /*!< 10-bit header sent (Master mode) */
#define I2C_SR1_STOPF_Pos (4U) #define I2C_STAT0_STPDET_Pos (4U)
#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ #define I2C_STAT0_STPDET_Msk (0x1U << I2C_STAT0_STPDET_Pos) /*!< 0x00000010 */
#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ #define I2C_STAT0_STPDET I2C_STAT0_STPDET_Msk /*!< Stop detection (Slave mode) */
#define I2C_SR1_RXNE_Pos (6U) #define I2C_STAT0_RBNE_Pos (6U)
#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ #define I2C_STAT0_RBNE_Msk (0x1U << I2C_STAT0_RBNE_Pos) /*!< 0x00000040 */
#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ #define I2C_STAT0_RBNE I2C_STAT0_RBNE_Msk /*!< Data Register not Empty (receivers) */
#define I2C_SR1_TXE_Pos (7U) #define I2C_STAT0_TBE_Pos (7U)
#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ #define I2C_STAT0_TBE_Msk (0x1U << I2C_STAT0_TBE_Pos) /*!< 0x00000080 */
#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ #define I2C_STAT0_TBE I2C_STAT0_TBE_Msk /*!< Data Register Empty (transmitters) */
#define I2C_SR1_BERR_Pos (8U) #define I2C_STAT0_BERR_Pos (8U)
#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ #define I2C_STAT0_BERR_Msk (0x1U << I2C_STAT0_BERR_Pos) /*!< 0x00000100 */
#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ #define I2C_STAT0_BERR I2C_STAT0_BERR_Msk /*!< Bus Error */
#define I2C_SR1_ARLO_Pos (9U) #define I2C_STAT0_LOSTARB_Pos (9U)
#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ #define I2C_STAT0_LOSTARB_Msk (0x1U << I2C_STAT0_LOSTARB_Pos) /*!< 0x00000200 */
#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ #define I2C_STAT0_LOSTARB I2C_STAT0_LOSTARB_Msk /*!< Arbitration Lost (master mode) */
#define I2C_SR1_AF_Pos (10U) #define I2C_STAT0_AERR_Pos (10U)
#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */ #define I2C_STAT0_AERR_Msk (0x1U << I2C_STAT0_AERR_Pos) /*!< 0x00000400 */
#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ #define I2C_STAT0_AERR I2C_STAT0_AERR_Msk /*!< Acknowledge Failure */
#define I2C_SR1_OVR_Pos (11U) #define I2C_STAT0_OUERR_Pos (11U)
#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ #define I2C_STAT0_OUERR_Msk (0x1U << I2C_STAT0_OUERR_Pos) /*!< 0x00000800 */
#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ #define I2C_STAT0_OUERR I2C_STAT0_OUERR_Msk /*!< Overrun/Underrun */
#define I2C_SR1_PECERR_Pos (12U) #define I2C_STAT0_PECERR_Pos (12U)
#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ #define I2C_STAT0_PECERR_Msk (0x1U << I2C_STAT0_PECERR_Pos) /*!< 0x00001000 */
#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ #define I2C_STAT0_PECERR I2C_STAT0_PECERR_Msk /*!< PEC Error in reception */
#define I2C_SR1_TIMEOUT_Pos (14U) #define I2C_STAT0_SMBTO_Pos (14U)
#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ #define I2C_STAT0_SMBTO_Msk (0x1U << I2C_STAT0_SMBTO_Pos) /*!< 0x00004000 */
#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ #define I2C_STAT0_SMBTO I2C_STAT0_SMBTO_Msk /*!< Timeout or Tlow Error */
#define I2C_SR1_SMBALERT_Pos (15U) #define I2C_STAT0_SMBALT_Pos (15U)
#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ #define I2C_STAT0_SMBALT_Msk (0x1U << I2C_STAT0_SMBALT_Pos) /*!< 0x00008000 */
#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ #define I2C_STAT0_SMBALT I2C_STAT0_SMBALT_Msk /*!< SMBus Alert */
/******************* Bit definition for I2C_SR2 register ********************/ /******************* Bit definition for I2C_STAT1 register ********************/
#define I2C_SR2_MSL_Pos (0U) #define I2C_STAT1_MASTER_Pos (0U)
#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ #define I2C_STAT1_MASTER_Msk (0x1U << I2C_STAT1_MASTER_Pos) /*!< 0x00000001 */
#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ #define I2C_STAT1_MASTER I2C_STAT1_MASTER_Msk /*!< Master/Slave */
#define I2C_SR2_BUSY_Pos (1U) #define I2C_STAT1_I2CBSY_Pos (1U)
#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ #define I2C_STAT1_I2CBSY_Msk (0x1U << I2C_STAT1_I2CBSY_Pos) /*!< 0x00000002 */
#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ #define I2C_STAT1_I2CBSY I2C_STAT1_I2CBSY_Msk /*!< Bus Busy */
#define I2C_SR2_TRA_Pos (2U) #define I2C_STAT1_TR_Pos (2U)
#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ #define I2C_STAT1_TR_Msk (0x1U << I2C_STAT1_TR_Pos) /*!< 0x00000004 */
#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ #define I2C_STAT1_TR I2C_STAT1_TR_Msk /*!< Transmitter/Receiver */
#define I2C_SR2_GENCALL_Pos (4U) #define I2C_STAT1_RXGC_Pos (4U)
#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ #define I2C_STAT1_RXGC_Msk (0x1U << I2C_STAT1_RXGC_Pos) /*!< 0x00000010 */
#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ #define I2C_STAT1_RXGC I2C_STAT1_RXGC_Msk /*!< General Call Address (Slave mode) */
#define I2C_SR2_SMBDEFAULT_Pos (5U) #define I2C_STAT1_DEFSMB_Pos (5U)
#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ #define I2C_STAT1_DEFSMB_Msk (0x1U << I2C_STAT1_DEFSMB_Pos) /*!< 0x00000020 */
#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ #define I2C_STAT1_DEFSMB I2C_STAT1_DEFSMB_Msk /*!< SMBus Device Default Address (Slave mode) */
#define I2C_SR2_SMBHOST_Pos (6U) #define I2C_STAT1_HSTSMB_Pos (6U)
#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ #define I2C_STAT1_HSTSMB_Msk (0x1U << I2C_STAT1_HSTSMB_Pos) /*!< 0x00000040 */
#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ #define I2C_STAT1_HSTSMB I2C_STAT1_HSTSMB_Msk /*!< SMBus Host Header (Slave mode) */
#define I2C_SR2_DUALF_Pos (7U) #define I2C_STAT1_DUMODF_Pos (7U)
#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ #define I2C_STAT1_DUMODF_Msk (0x1U << I2C_STAT1_DUMODF_Pos) /*!< 0x00000080 */
#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ #define I2C_STAT1_DUMODF I2C_STAT1_DUMODF_Msk /*!< Dual Flag (Slave mode) */
#define I2C_SR2_PEC_Pos (8U) #define I2C_STAT1_PECV_Pos (8U)
#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ #define I2C_STAT1_PECV_Msk (0xFFU << I2C_STAT1_PECV_Pos) /*!< 0x0000FF00 */
#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ #define I2C_STAT1_PECV I2C_STAT1_PECV_Msk /*!< Packet Error Checking Register */
/******************* Bit definition for I2C_CCR register ********************/ /******************* Bit definition for I2C_CKCFG register ********************/
#define I2C_CCR_CCR_Pos (0U) #define I2C_CKCFG_CLKC_Pos (0U)
#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ #define I2C_CKCFG_CLKC_Msk (0xFFFU << I2C_CKCFG_CLKC_Pos) /*!< 0x00000FFF */
#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ #define I2C_CKCFG_CLKC I2C_CKCFG_CLKC_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
#define I2C_CCR_DUTY_Pos (14U) #define I2C_CKCFG_DTCY_Pos (14U)
#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ #define I2C_CKCFG_DTCY_Msk (0x1U << I2C_CKCFG_DTCY_Pos) /*!< 0x00004000 */
#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ #define I2C_CKCFG_DTCY I2C_CKCFG_DTCY_Msk /*!< Fast Mode Duty Cycle */
#define I2C_CCR_FS_Pos (15U) #define I2C_CKCFG_FAST_Pos (15U)
#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */ #define I2C_CKCFG_FAST_Msk (0x1U << I2C_CKCFG_FAST_Pos) /*!< 0x00008000 */
#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ #define I2C_CKCFG_FAST I2C_CKCFG_FAST_Msk /*!< I2C Master Mode Selection */
/****************** Bit definition for I2C_TRISE register *******************/ /****************** Bit definition for I2C_RT register *******************/
#define I2C_TRISE_TRISE_Pos (0U) #define I2C_RT_RISETIME_Pos (0U)
#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ #define I2C_RT_RISETIME_Msk (0x3FU << I2C_RT_RISETIME_Pos) /*!< 0x0000003F */
#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ #define I2C_RT_RISETIME I2C_RT_RISETIME_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
/****************** Bit definition for I2C_FMPCFG register *******************/
#define I2C_FMPCFG_FMPEN_Pos (0U)
#define I2C_FMPCFG_FMPEN_Msk (0x1U << I2C_FMPCFG_FMPEN_Pos) /*!< 0x0000003F */
#define I2C_FMPCFG_FMPEN I2C_FMPCFG_FMPEN_Msk /*!< Fast mode plus enable */
/******************************************************************************/ /******************************************************************************/
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