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ChibiOS-Contrib
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This commit is contained in:
Nicolas Reinecke 2016-11-08 20:39:45 +01:00
parent a6158cef3c
commit 00f18c55cc
4 changed files with 23 additions and 23 deletions
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16
os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
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@ -194,24 +194,24 @@ void qei_lld_start(QEIDriver *qeip) {
#endif #endif
} }
/* Timer configuration.*/ /* Timer configuration.*/
qeip->tim->CR1 = 0; /* Initially stopped. */ qeip->tim->CR1 = 0; /* Initially stopped. */
qeip->tim->CR2 = 0; qeip->tim->CR2 = 0;
qeip->tim->PSC = 0; qeip->tim->PSC = 0;
qeip->tim->DIER = 0; qeip->tim->DIER = 0;
qeip->tim->ARR = 0xFFFF; qeip->tim->ARR = 0xFFFF;
/* Set Capture Compare 1 and Capture Compare 2 as input. */ /* Set Capture Compare 1 and Capture Compare 2 as input. */
qeip->tim->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; qeip->tim->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
if (qeip->config->mode == QEI_MODE_QUADRATURE) { if (qeip->config->mode == QEI_MODE_QUADRATURE) {
if (qeip->config->resolution == QEI_BOTH_EDGES) if (qeip->config->resolution == QEI_BOTH_EDGES)
qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;
else else
qeip->tim->SMCR = TIM_SMCR_SMS_0; qeip->tim->SMCR = TIM_SMCR_SMS_0;
} else { } else {
/* Direction/Clock mode. /* Direction/Clock mode.
* Direction input on TI1, Clock input on TI2. */ * Direction input on TI1, Clock input on TI2. */
qeip->tim->SMCR = TIM_SMCR_SMS_0; qeip->tim->SMCR = TIM_SMCR_SMS_0;
} }
if (qeip->config->dirinv == QEI_DIRINV_TRUE) if (qeip->config->dirinv == QEI_DIRINV_TRUE)
@ -230,7 +230,7 @@ void qei_lld_start(QEIDriver *qeip) {
void qei_lld_stop(QEIDriver *qeip) { void qei_lld_stop(QEIDriver *qeip) {
if (qeip->state == QEI_READY) { if (qeip->state == QEI_READY) {
qeip->tim->CR1 = 0; /* Timer disabled. */ qeip->tim->CR1 = 0; /* Timer disabled. */
/* Clock deactivation.*/ /* Clock deactivation.*/
#if STM32_QEI_USE_TIM1 #if STM32_QEI_USE_TIM1
@ -275,7 +275,7 @@ void qei_lld_stop(QEIDriver *qeip) {
*/ */
void qei_lld_enable(QEIDriver *qeip) { void qei_lld_enable(QEIDriver *qeip) {
qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */ qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */
} }
/** /**
@ -287,7 +287,7 @@ void qei_lld_enable(QEIDriver *qeip) {
*/ */
void qei_lld_disable(QEIDriver *qeip) { void qei_lld_disable(QEIDriver *qeip) {
qeip->tim->CR1 = 0; /* Timer disabled. */ qeip->tim->CR1 = 0; /* Timer disabled. */
} }
#endif /* HAL_USE_QEI */ #endif /* HAL_USE_QEI */

4
testhal/STM32/STM32F0xx/onewire/Makefile
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@ -75,7 +75,7 @@ endif
PROJECT = ch PROJECT = ch
# Imported source files and paths # Imported source files and paths
CHIBIOS = ../../../../../ChibiOS-RT CHIBIOS = ../../../../../ChibiOS-RT
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
TESTHAL = $(CHIBIOS_CONTRIB)/testhal/common/onewire TESTHAL = $(CHIBIOS_CONTRIB)/testhal/common/onewire
# Startup files. # Startup files.
@ -104,7 +104,7 @@ CSRC = $(STARTUPSRC) \
$(TESTSRC) \ $(TESTSRC) \
main.c \ main.c \
$(TESTHAL)/testhal_onewire.c $(TESTHAL)/testhal_onewire.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global # C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting. # setting.
CPPSRC = CPPSRC =

2
testhal/STM32/STM32F3xx/EEProm/halconf_community.h
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@ -109,7 +109,7 @@
* @note Disabling this option saves both code and data space. * @note Disabling this option saves both code and data space.
*/ */
#define EEPROM_USE_EE24XX TRUE #define EEPROM_USE_EE24XX TRUE
/** /**
* @brief Enables 25xx series SPI eeprom device driver. * @brief Enables 25xx series SPI eeprom device driver.
* @note Disabling this option saves both code and data space. * @note Disabling this option saves both code and data space.
*/ */

24
testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h
View File

@ -48,19 +48,19 @@
/* /*
* USBH driver system settings. * USBH driver system settings.
*/ */
#define STM32_OTG1_CHANNELS_NUMBER 8 #define STM32_OTG1_CHANNELS_NUMBER 8
#define STM32_OTG2_CHANNELS_NUMBER 12 #define STM32_OTG2_CHANNELS_NUMBER 12
#define STM32_USBH_USE_OTG1 1 #define STM32_USBH_USE_OTG1 1
#define STM32_OTG1_RXFIFO_SIZE 1024 #define STM32_OTG1_RXFIFO_SIZE 1024
#define STM32_OTG1_PTXFIFO_SIZE 128 #define STM32_OTG1_PTXFIFO_SIZE 128
#define STM32_OTG1_NPTXFIFO_SIZE 128 #define STM32_OTG1_NPTXFIFO_SIZE 128
#define STM32_USBH_USE_OTG2 0 #define STM32_USBH_USE_OTG2 0
#define STM32_OTG2_RXFIFO_SIZE 2048 #define STM32_OTG2_RXFIFO_SIZE 2048
#define STM32_OTG2_PTXFIFO_SIZE 1024 #define STM32_OTG2_PTXFIFO_SIZE 1024
#define STM32_OTG2_NPTXFIFO_SIZE 1024 #define STM32_OTG2_NPTXFIFO_SIZE 1024
#define STM32_USBH_MIN_QSPACE 4 #define STM32_USBH_MIN_QSPACE 4
#define STM32_USBH_CHANNELS_NP 4 #define STM32_USBH_CHANNELS_NP 4