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Merge pull request #238 from alexclewontin/NUC123-platform 

NUC123SD4AN0 to NUC123
This commit is contained in:
Fabien Poussin 2020-12-14 10:08:24 +01:00 committed by GitHub
parent 7d6e9b8f23 6faa8b96a9
commit 032b4cec7a
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
20 changed files with 65129 additions and 574 deletions
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32378
ext/NUC123AE_v1.svd Executable file
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32352
ext/NUC123AN_v1.svd Executable file
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37
os/common/startup/ARMCMx/compilers/GCC/ld/NUC123SD4AN0.ld → os/common/startup/ARMCMx/compilers/GCC/ld/NUC123xD4xx0.ld
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@ -1,5 +1,5 @@
/* /*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio Copyright (C) 2020 Alex Lewontin
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
@ -15,26 +15,27 @@
*/ */
/* /*
* NUC123SD4AN0 memory setup. * NUC123xD4xx0 memory setup.
* 64k ROM, 20k ram
*/ */
MEMORY MEMORY
{ {
flash0 : org = 0x00000000, len = 64k flash0 (rx) : org = 0x00000000, len = 64k
flash1 : org = 0x00000000, len = 0 flash1 (rx) : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0 flash2 (rx) : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 20k ram0 (wx) : org = 0x20000000, len = 20k
ram1 : org = 0x00000000, len = 0 ram1 (wx) : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0 ram4 (wx) : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0 ram5 (wx) : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0 ram6 (wx) : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0 ram7 (wx) : org = 0x00000000, len = 0
} }
/* For each data/text section two region are defined, a virtual region /* For each data/text section two region are defined, a virtual region

4
os/common/startup/ARMCMx/compilers/GCC/mk/startup_NUC123SD4AN0.mk → os/common/startup/ARMCMx/compilers/GCC/mk/startup_NUC123.mk
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@ -1,10 +1,10 @@
# List of the ChibiOS generic NUC123SD4AN0 startup and CMSIS files. # List of the ChibiOS generic NUC123 startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \ STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/NUC123SD4AN0 \ STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/NUC123 \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \
$(CHIBIOS)/os/common/ext/CMSIS/include \ $(CHIBIOS)/os/common/ext/CMSIS/include \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \

15
os/common/startup/ARMCMx/devices/NUC123SD4AN0/cmparams.h → os/common/startup/ARMCMx/devices/NUC123/cmparams.h
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@ -15,13 +15,13 @@
*/ */
/** /**
* @file NUC123SD4AN0/cmparams.h * @file NUC123/cmparams.h
* @brief ARM Cortex-M0 parameters for the NUC123SD4AN0. * @brief ARM Cortex-M0 parameters for the NUC123.
* *
* @defgroup ARMCMx_NUC123 NUC123SD4AN0 Specific Parameters * @defgroup ARMCMx_NUC123 NUC123 Specific Parameters
* @ingroup ARMCMx_SPECIFIC * @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M0 specific parameters for the * @details This file contains the Cortex-M0 specific parameters for the
* NUC123SD4AN0 platform. * NUC123 platform.
* @{ * @{
*/ */
@ -57,7 +57,12 @@
/* If the device type is not externally defined, for example from the Makefile, /* If the device type is not externally defined, for example from the Makefile,
then a file named board.h is included. This file must contain a device then a file named board.h is included. This file must contain a device
definition compatible with the vendor include file.*/ definition compatible with the vendor include file.*/
#if !defined (NUC123SD4AN0) #if !defined(NUC123SD4AN0) && !defined(NUC123SC2AN1) && \
!defined(NUC123LD4AN0) && !defined(NUC123LC2AN1) && \
!defined(NUC123ZD4AN0) && !defined(NUC123ZC2AN1) && \
!defined(NUC123SD4AE0) && !defined(NUC123SC2AE1) && \
!defined(NUC123LD4AE0) && !defined(NUC123LC2AE1) && \
!defined(NUC123ZD4AE0) && !defined(NUC123ZC2AE1)
#include "board.h" #include "board.h"
#endif #endif

1
os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.h
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@ -27,7 +27,6 @@
#define NUC123SD4AN0 #define NUC123SD4AN0
#define BOARD_NAME "NUTINY SDK NUC123 V2.0" #define BOARD_NAME "NUTINY SDK NUC123 V2.0"
#define NUC123_LSE_BYPASS TRUE
/* /*
* Board specific settings. * Board specific settings.
*/ */

11
os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c
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@ -51,7 +51,6 @@
OSAL_IRQ_HANDLER(NUC123_GPIOAB_HANDLER){ OSAL_IRQ_HANDLER(NUC123_GPIOAB_HANDLER){
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
GPIO_TOGGLE(PB4); GPIO_TOGGLE(PB4);
GPIO_TOGGLE(PB5); GPIO_TOGGLE(PB5);
GPIO_TOGGLE(PB6); GPIO_TOGGLE(PB6);
@ -88,7 +87,7 @@ OSAL_IRQ_HANDLER(NUC123_GPIOCDF_HANDLER){
*/ */
void _pal_lld_init(const PALConfig *config) { void _pal_lld_init(const PALConfig *config) {
//(void)config; /* (void)config; */
/* Turn on GPIO subsystem /* Turn on GPIO subsystem
* Set all GPIO to Input/HZ * Set all GPIO to Input/HZ
* Clear all GPIO Interrupts * Clear all GPIO Interrupts
@ -148,7 +147,7 @@ void _pal_lld_init(const PALConfig *config) {
/* Enable External Crystal Oscillator pins */ /* Enable External Crystal Oscillator pins */
SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN; SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN;
// SYS->GPD_MFP |= SYS_GPD_MFP_PD10_CLKO; /* SYS->GPD_MFP |= SYS_GPD_MFP_PD10_CLKO; */
/* Enable UART1 data pins */ /* Enable UART1 data pins */
SYS->GPB_MFP |= SYS_GPB_MFP_PB1_UART0_TXD | SYS_GPB_MFP_PB0_UART0_RXD; SYS->GPB_MFP |= SYS_GPB_MFP_PB1_UART0_TXD | SYS_GPB_MFP_PB0_UART0_RXD;
@ -181,10 +180,10 @@ void _pal_lld_setgroupmode(ioportid_t port,
else else
nucMode = GPIO_PMD_QUASI; nucMode = GPIO_PMD_QUASI;
// GPIO_SetMode(port, mask, nucMode); /* GPIO_SetMode(port, mask, nucMode); */
for (uint32_t i = 0; i < PAL_IOPORTS_WIDTH; i++) { for (uint32_t i = 0; i < PAL_IOPORTS_WIDTH; i++) {
// for(uint32_t i = 0; i < GPIO_PINSPERPORT_MAX; i++) { /* for (uint32_t i = 0; i < GPIO_PINSPERPORT_MAX; i++) { */
if(mask & (1 << i)) { if (mask & (1 << i)) {
port->PMD = (port->PMD & ~(0x03ul << (i << 1))) | (nucMode << (i << 1)); port->PMD = (port->PMD & ~(0x03ul << (i << 1))) | (nucMode << (i << 1));
} }
} }

495
os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.h
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48
os/hal/ports/NUMICRO/NUC123SD4AN0/hal_lld.c → os/hal/ports/NUMICRO/NUC123/hal_lld.c
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@ -60,7 +60,7 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
register settings. register settings.
This function can be used to retrieve the system core clock frequeny This function can be used to retrieve the system core clock frequeny
after user changed register sittings. */ after user changed register sittings. */
// SystemCoreClock = SYSTEM_CLOCK; /* SystemCoreClock = SYSTEM_CLOCK; */
uint32_t clkFreq; uint32_t clkFreq;
uint32_t PllReg; uint32_t PllReg;
@ -68,7 +68,7 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
uint32_t pllFIN, pllNF, pllNR, pllNO; uint32_t pllFIN, pllNF, pllNR, pllNO;
/* Update PLL Clock */ /* Update PLL Clock */
// PllClock = clks_lld_get_pll_clock_freq(); /* PllClock = clks_lld_get_pll_clock_freq(); */
PllReg = CLK->PLLCON; PllReg = CLK->PLLCON;
if (PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) { if (PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) {
@ -106,19 +106,19 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
/* Pick Clock Source */ /* Pick Clock Source */
switch (CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk) { switch (CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk) {
case 0: // External HF Xtal case 0: /* External HF Xtal */
clkFreq = __HXT; clkFreq = __HXT;
break; break;
case 1: // PLL clock / 2 case 1: /* PLL clock / 2 */
clkFreq = PllClock >> 1; clkFreq = PllClock >> 1;
break; break;
case 3: // Internal 10kHz case 3: /* Internal 10kHz */
clkFreq = __LIRC; clkFreq = __LIRC;
break; break;
case 2: // PLL clock case 2: /* PLL clock */
clkFreq = PllClock; clkFreq = PllClock;
break; break;
case 7: // Internal 22.184MHz case 7: /* Internal 22.184MHz */
clkFreq = __HIRC; clkFreq = __HIRC;
break; break;
default: default:
@ -157,13 +157,13 @@ static inline uint32_t get_pll_clock_freq(void)
PllClock = pllFIN; PllClock = pllFIN;
} else { } else {
switch (((PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)) { switch (((PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)) {
case 0: // OUT_DIV == 00 : NO = 1 case 0: /* OUT_DIV == 00 : NO = 1 */
pllNO = 1; pllNO = 1;
break; break;
case 3: // OUT_DIV == 11 : NO = 4 case 3: /* OUT_DIV == 11 : NO = 4 */
pllNO = 4; pllNO = 4;
break; break;
default: // OUT_DIV == 01 or 10 : NO = 2 default: /* OUT_DIV == 01 or 10 : NO = 2 */
pllNO = 2; pllNO = 2;
break; break;
} }
@ -171,7 +171,7 @@ static inline uint32_t get_pll_clock_freq(void)
pllNF = ((PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2; pllNF = ((PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2;
pllNR = ((PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2; pllNR = ((PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2;
/* shift to avoid overflow condition */ /* Shift to avoid overflow condition */
PllClock = (((pllFIN >> 2) * pllNF) / (pllNR * pllNO) << 2); PllClock = (((pllFIN >> 2) * pllNF) / (pllNR * pllNO) << 2);
} }
} }
@ -181,9 +181,9 @@ static inline uint32_t get_pll_clock_freq(void)
/** /**
* @brief Wait for stable clock * @brief Wait for stable clock
* *
* @description Always wait around 300ms for clock to be stable * @description Always wait around 300ms for clock to be stable
* *
*/ */
static uint32_t wait_for_clock_ready(uint32_t clkMask) static uint32_t wait_for_clock_ready(uint32_t clkMask)
{ {
@ -199,13 +199,13 @@ static uint32_t wait_for_clock_ready(uint32_t clkMask)
} }
/** @brief Set system HCLK /** @brief Set system HCLK
* *
* @description Setup HCLK source and divider * @description Setup HCLK source and divider
* *
* Always switch to a known stable clock source before changing a * Always switch to a known stable clock source before changing a
* system clock, to avoid issues related to the original clock's * system clock, to avoid issues related to the original clock's
* speed/settings. * speed/settings.
* *
*/ */
static void set_HCLK(uint32_t clkSource, uint32_t clkDivider) static void set_HCLK(uint32_t clkSource, uint32_t clkDivider)
{ {
@ -265,13 +265,13 @@ static uint32_t enable_pll(uint32_t pllSrc, uint32_t pllFreq)
/** /**
* Calculate best PLL variables from requested frequency * Calculate best PLL variables from requested frequency
* *
* See NUC123 Technical Reference Manual 5.4.8 PLL Control Register Description, page 124 * See NUC123 Technical Reference Manual 5.4.8 PLL Control Register Description, page 124
* *
* NF 1 * NF 1
* FOUT = FIN x -- x -- * FOUT = FIN x -- x --
* NR NO * NR NO
* *
*/ */
uint32_t NO = 0; uint32_t NO = 0;
@ -328,9 +328,9 @@ static uint32_t enable_pll(uint32_t pllSrc, uint32_t pllFreq)
/** /**
* Loop to calculate best/lowest NR (between 0 or 2 and 31) and best/lowest NF (between 0 and 511) * Loop to calculate best/lowest NR (between 0 or 2 and 31) and best/lowest NF (between 0 and 511)
* *
* Best results are off-by-2 until final equation calculation (to allow use in PLLCON) * Best results are off-by-2 until final equation calculation (to allow use in PLLCON)
* *
*/ */
uint32_t bestNR = 0; uint32_t bestNR = 0;
uint32_t bestNF = 0; uint32_t bestNF = 0;
@ -383,13 +383,13 @@ static uint32_t enable_pll(uint32_t pllSrc, uint32_t pllFreq)
} }
/** @brief Set Core Clock /** @brief Set Core Clock
* *
* @description Set the core system clock some reference speed (Hz). * @description Set the core system clock some reference speed (Hz).
* This should be between 25MHz and 72MHz for the NUC123SD4AN0. * This should be between 25MHz and 72MHz for the NUC123SD4AN0.
* *
* Use either the HXT (exact) or HIRC (nearest using 22.1184MHz) * Use either the HXT (exact) or HIRC (nearest using 22.1184MHz)
* as the clock source. * as the clock source.
* *
*/ */
static uint32_t set_core_clock(uint32_t clkCore) static uint32_t set_core_clock(uint32_t clkCore)
{ {

13
os/hal/ports/NUMICRO/NUC123SD4AN0/hal_lld.h → os/hal/ports/NUMICRO/NUC123/hal_lld.h
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@ -16,8 +16,8 @@
*/ */
/** /**
* @file NUC123SD4AN0/hal_lld.h * @file NUC123/hal_lld.h
* @brief NUC123SD4AN0 HAL subsystem low level driver header. * @brief NUC123 HAL subsystem low level driver header.
* @pre This module requires the following macros to be defined in the * @pre This module requires the following macros to be defined in the
* @p board.h file: * @p board.h file:
* - NUC123_HSECLK. * - NUC123_HSECLK.
@ -41,12 +41,13 @@
*/ */
#if defined(NUC123SD4AN0) || defined(__DOXYGEN__) #if defined(NUC123SD4AN0) || defined(__DOXYGEN__)
#define PLATFORM_NAME "NUC123SD4AN0 NUC123 Cortex M0 USB Micro" #define PLATFORM_NAME "NUC123SD4AN0 NUC123 Cortex M0 USB Micro"
#define NUC123xxxANx
#undef NUC123xxxAEx
#else #else
#error "NUC123 device unsupported or not specified" #error "NUC123 device unsupported or not specified"
#endif #endif
#define NUC123xxxANx /* TODO: Add other NUC123xxxxxx versions */
#undef NUC123xxxAEx
/** @} */ /** @} */
@ -186,8 +187,8 @@
/* /*
* Configuration-related checks. * Configuration-related checks.
*/ */
#if !defined(NUC123SD4AN0_MCUCONF) #if !defined(NUC123_MCUCONF)
#error "Using a wrong mcuconf.h file, NUC123SD4AN0_MCUCONF not defined" #error "Using a wrong mcuconf.h file, NUC123_MCUCONF not defined"
#endif #endif
/* /*

6
os/hal/ports/NUMICRO/NUC123SD4AN0/nuc123_isr.h → os/hal/ports/NUMICRO/NUC123/nuc123_isr.h
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@ -18,7 +18,7 @@
* @file NUMICRO/nuc123_isr.h * @file NUMICRO/nuc123_isr.h
* @brief ISR remapper driver header. * @brief ISR remapper driver header.
* *
* @addtogroup NUC123SD4AN0_ISR * @addtogroup NUC123_ISR
* @{ * @{
*/ */
@ -34,16 +34,14 @@
* @{ * @{
*/ */
/* /*
* GPIO units. * GPIO units.
*/ */
#if defined(NUC123SD4AN0)
#define NUC123_GPIOAB_HANDLER Vector50 #define NUC123_GPIOAB_HANDLER Vector50
#define NUC123_GPIOCDF_HANDLER Vector54 #define NUC123_GPIOCDF_HANDLER Vector54
#define NUC123_GPIOAB_NUMBER GPAB_IRQn #define NUC123_GPIOAB_NUMBER GPAB_IRQn
#define NUC123_GPIOCDF_NUMBER GPCDF_IRQn #define NUC123_GPIOCDF_NUMBER GPCDF_IRQn
#endif
/* /*
* Special ST unit * Special ST unit

27
os/hal/ports/NUMICRO/NUC123SD4AN0/nuc123_registry.h → os/hal/ports/NUMICRO/NUC123/nuc123_registry.h
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@ -15,8 +15,8 @@
*/ */
/** /**
* @file NUC123SD4AN0/nuc123_registry.h * @file NUC123/nuc123_registry.h
* @brief NUC123SD4AN0 capabilities registry. * @brief NUC123 capabilities registry.
* *
* @addtogroup HAL * @addtogroup HAL
* @{ * @{
@ -25,16 +25,12 @@
#ifndef NUC123_REGISTRY_H #ifndef NUC123_REGISTRY_H
#define NUC123_REGISTRY_H #define NUC123_REGISTRY_H
#if !defined(NUC123SD4AN0) || defined(__DOXYGEN__)
#define NUC123SD4AN0
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Platform capabilities. */ /* Platform capabilities. */
/*===========================================================================*/ /*===========================================================================*/
/** /**
* @name NUC123SD4AN0 capabilities * @name NUC123 capabilities
* @{ * @{
*/ */
@ -99,8 +95,8 @@
#define NUC123_HAS_ETH FALSE #define NUC123_HAS_ETH FALSE
/* EXTI attributes.*/ /* EXTI attributes.*/
//#define NUC123_EXTI_NUM_LINES 20 /* #define NUC123_EXTI_NUM_LINES 20 */
//#define NUC123_EXTI_IMR_MASK 0xFFF50000U /* #define NUC123_EXTI_IMR_MASK 0xFFF50000U */
/* GPIO attributes.*/ /* GPIO attributes.*/
#define NUC123_HAS_GPIOA TRUE #define NUC123_HAS_GPIOA TRUE
@ -203,7 +199,7 @@
#define NUC123_HAS_TIM22 FALSE #define NUC123_HAS_TIM22 FALSE
/* USART attributes.*/ /* USART attributes.*/
/*#define NUC123_HAS_USART1 TRUE /* #define NUC123_HAS_USART1 TRUE
#define NUC123_USART1_RX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 1) |\ #define NUC123_USART1_RX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 1) |\
NUC123_DMA_STREAM_ID_MSK(1, 3) |\ NUC123_DMA_STREAM_ID_MSK(1, 3) |\
NUC123_DMA_STREAM_ID_MSK(1, 5)) NUC123_DMA_STREAM_ID_MSK(1, 5))
@ -219,8 +215,8 @@
#define NUC123_USART2_RX_DMA_CHN 0x00090909 #define NUC123_USART2_RX_DMA_CHN 0x00090909
#define NUC123_USART2_TX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 2) |\ #define NUC123_USART2_TX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 2) |\
NUC123_DMA_STREAM_ID_MSK(1, 4)) NUC123_DMA_STREAM_ID_MSK(1, 4))
#define NUC123_USART2_TX_DMA_CHN 0x00009090 #define NUC123_USART2_TX_DMA_CHN 0x00009090 */
*/
#define NUC123_HAS_USART1 FALSE #define NUC123_HAS_USART1 FALSE
#define NUC123_HAS_USART2 FALSE #define NUC123_HAS_USART2 FALSE
#define NUC123_HAS_USART3 FALSE #define NUC123_HAS_USART3 FALSE
@ -253,13 +249,6 @@
#define NUC123_HAS_CRC TRUE #define NUC123_HAS_CRC TRUE
#define NUC123_CRC_PROGRAMMABLE FALSE #define NUC123_CRC_PROGRAMMABLE FALSE
/*
This currently correspond to the header guards, and gets tripped on double inclusion.
This does not seem correct.
#else
#error "NUC123SD4AN0 device not specified"
*/
/** @} */ /** @} */
#endif /* NUC123_REGISTRY_H */ #endif /* NUC123_REGISTRY_H */

6
os/hal/ports/NUMICRO/NUC123SD4AN0/platform.mk → os/hal/ports/NUMICRO/NUC123/platform.mk
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@ -1,9 +1,9 @@
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
$(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123SD4AN0/hal_lld.c $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123/hal_lld.c
# Required include directories. # Required include directories.
PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
$(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123SD4AN0 \ $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123 \
$(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD
# Optional platform files. # Optional platform files.
@ -18,4 +18,4 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/USBv1/driver.mk
# Shared variables # Shared variables
ALLCSRC += $(PLATFORMSRC) ALLCSRC += $(PLATFORMSRC)
ALLINC += $(PLATFORMINC) ALLINC += $(PLATFORMINC)

153
os/hal/ports/NUMICRO/NUC123SD4AN0/system_NUC123SD4AN0.c
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@ -1,153 +0,0 @@
/**************************************************************************//**
* @file system_NUC123SD4AN0.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for
* Device NUC123SD4AN0
* @version V5.00
* @date 13. May 2019
******************************************************************************/
/*
* Copyright (c) 2019 /u/KeepItUnder. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdint.h>
#include "NUC123SD4AN0.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
// #define XTAL (12000000U) /* Oscillator frequency */
// #define SYSTEM_CLOCK (5 * XTAL)
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
achieved after system intitialization.
This means system core clock frequency after call to SystemInit() */
// uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Clock Frequency (Core Clock)*/
// uint32_t CyclesPerUs = (SYSTEM_CLOCK / 1000000); /* Cycles per micro second */
// uint32_t PllClock = SYSTEM_CLOCK; /*!< PLL Clock Frequency */
uint32_t SystemCoreClock = __HSI; /* System Clock Frequency (Core Clock)*/
uint32_t CyclesPerUs = (__HSI / 1000000); /* Cycles per micro second */
uint32_t PllClock = __HSI; /*!< PLL Clock Frequency */
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* ToDo: add code to calculate the system frequency based upon the current
register settings.
This function can be used to retrieve the system core clock frequeny
after user changed register sittings. */
// SystemCoreClock = SYSTEM_CLOCK;
uint32_t clkFreq;
uint32_t PllReg;
uint32_t pllFIN, pllNF, pllNR, pllNO;
/* Update PLL Clock */
// PllClock = clks_lld_get_pll_clock_freq();
PllReg = CLK->PLLCON;
if(PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) {
PllClock = 0; /* PLL is off. */
} else {
if (PllReg & 0x00080000ul) {
pllFIN = __HIRC; /* Use HXT for PLL clock */
} else {
pllFIN = __HXT; /* Use HXT for PLL clock */
}
if (PllReg & CLK_PLLCON_BP_Msk) {
PllClock = pllFIN;
} else {
switch (((PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)) {
case 0b00: /* OUT_DIV == 00 : NO = 1 */
pllNO = 1;
break;
case 0b11: /* OUT_DIV == 11 : NO = 4 */
pllNO = 4;
break;
default: /* OUT_DIV == 01 or 10 : NO = 2 */
pllNO = 2;
break;
}
pllNF = ((PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2;
pllNR = ((PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2;
/* Shift right to avoid overflow condition */
PllClock = (((pllFIN >> 2) * pllNF) / (pllNR * pllNO) << 2);
}
}
/* Pick Clock Source */
switch (CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk) {
case 0: // External HF Xtal
clkFreq = __HXT;
break;
case 1: // PLL clock / 2
clkFreq = PllClock >> 1;
break;
case 3: // Internal 10kHz
clkFreq = __LIRC;
break;
case 2: // PLL clock
clkFreq = PllClock;
break;
case 7: // Internal 22.184MHz
clkFreq = __HIRC;
break;
default:
clkFreq = NULL;
break;
}
SystemCoreClock = clkFreq / ((CLK->CLKDIV & CLK_CLKDIV_HCLK_N_Msk) + 1);
// CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
CyclesPerUs = SystemCoreClock / 1000000;
}
void SystemInit (void)
{
/* ToDo: add code to initialize the system
do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
// SystemCoreClock = SYSTEM_CLOCK;
}
void SystemUnlockReg(void)
{
while(SYS->REGWRPROT != SYS_REGWRPROT_REGPROTDIS_Msk)
{
SYS->REGWRPROT = 0x59ul;
SYS->REGWRPROT = 0x16ul;
SYS->REGWRPROT = 0x88ul;
}
}

6
testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/Makefile
View File

@ -99,10 +99,10 @@ DEPDIR := ./.dep
# Licensing files. # Licensing files.
include $(CHIBIOS)/os/license/license.mk include $(CHIBIOS)/os/license/license.mk
# Startup files. # Startup files.
include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_NUC123SD4AN0.mk include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_NUC123.mk
# HAL-OSAL files (optional). # HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123SD4AN0/platform.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123/platform.mk
include $(CHIBIOS_CONTRIB)/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.mk include $(CHIBIOS_CONTRIB)/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.mk
include $(CHIBIOS)/os/hal/osal/os-less/ARMCMx/osal.mk include $(CHIBIOS)/os/hal/osal/os-less/ARMCMx/osal.mk
# RTOS files (optional). # RTOS files (optional).
@ -116,7 +116,7 @@ include $(CHIBIOS)/tools/mk/autobuild.mk
#include $(CHIBIOS)/test/oslib/oslib_test.mk #include $(CHIBIOS)/test/oslib/oslib_test.mk
# Define linker script file here # Define linker script file here
LDSCRIPT= $(STARTUPLD_CONTRIB)/NUC123SD4AN0.ld LDSCRIPT= $(STARTUPLD_CONTRIB)/NUC123xD4xx0.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global # C sources that can be compiled in ARM or THUMB mode depending on the global
# setting. # setting.

2
testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/cfg/mcuconf.h
View File

@ -29,6 +29,6 @@
#define NUC123_PLLSRC NUC123_PLLSRC_HSE #define NUC123_PLLSRC NUC123_PLLSRC_HSE
#define NUC123_HCLKSRC NUC123_HCLKSRC_PLL #define NUC123_HCLKSRC NUC123_HCLKSRC_PLL
#define NUC123SD4AN0_MCUCONF #define NUC123_MCUCONF
#endif /* _MCUCONF_H_ */ #endif /* _MCUCONF_H_ */

134
testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/cfg/osalconf.h
View File

@ -1,67 +1,67 @@
/* /*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
You may obtain a copy of the License at You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0 http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and See the License for the specific language governing permissions and
limitations under the License. limitations under the License.
*/ */
/** /**
* @file templates/halconf.h * @file templates/halconf.h
* @brief Bare-metal OSAL configuration header. * @brief Bare-metal OSAL configuration header.
* *
* @addtogroup OSAL_CONF * @addtogroup OSAL_CONF
* @{ * @{
*/ */
#ifndef OSALCONF_H #ifndef OSALCONF_H
#define OSALCONF_H #define OSALCONF_H
/** /**
* @brief Frequency in Hertz of the system tick. * @brief Frequency in Hertz of the system tick.
*/ */
#if !defined(OSAL_ST_FREQUENCY) || defined(__DOXYGEN__) #if !defined(OSAL_ST_FREQUENCY) || defined(__DOXYGEN__)
#define OSAL_ST_FREQUENCY 10000 #define OSAL_ST_FREQUENCY 10000
#endif #endif
/** /**
* @brief Enables OSAL assertions. * @brief Enables OSAL assertions.
*/ */
#if !defined(OSAL_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #if !defined(OSAL_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define OSAL_DBG_ENABLE_ASSERTS FALSE #define OSAL_DBG_ENABLE_ASSERTS FALSE
#endif #endif
/** /**
* @brief Enables OSAL functions parameters checks. * @brief Enables OSAL functions parameters checks.
*/ */
#if !defined(OSAL_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #if !defined(OSAL_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define OSAL_DBG_ENABLE_CHECKS FALSE #define OSAL_DBG_ENABLE_CHECKS FALSE
#endif #endif
/** /**
* @brief OSAL initialization hook. * @brief OSAL initialization hook.
*/ */
#if !defined(OSAL_INIT_HOOK) || defined(__DOXYGEN__) #if !defined(OSAL_INIT_HOOK) || defined(__DOXYGEN__)
#define OSAL_INIT_HOOK() { \ #define OSAL_INIT_HOOK() { \
} }
#endif #endif
/** /**
* @brief Idle loop hook macro. * @brief Idle loop hook macro.
*/ */
#if !defined(OSAL_IDLE_HOOK) || defined(__DOXYGEN__) #if !defined(OSAL_IDLE_HOOK) || defined(__DOXYGEN__)
#define OSAL_IDLE_HOOK() { \ #define OSAL_IDLE_HOOK() { \
} }
#endif #endif
#endif /* OSALCONF_H */ #endif /* OSALCONF_H */
/** @} */ /** @} */

5
testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/readme.txt
View File

@ -1,5 +1,5 @@
***************************************************************************** *****************************************************************************
** ChibiOS/HAL - USB driver demo for NUC123. ** ** ChibiOS/HAL - Blinky demo for NUC123. **
***************************************************************************** *****************************************************************************
** TARGET ** ** TARGET **
@ -12,7 +12,6 @@ The application demonstrates the use of the NUC123 platform driver, and a little
bit of the PAL. A successful run of the test involves the on-board LED blinking at .5 Hz bit of the PAL. A successful run of the test involves the on-board LED blinking at .5 Hz
(on for 1 second, then off for one second). (on for 1 second, then off for one second).
** Board Setup ** ** Board Setup **
- None - None
@ -20,4 +19,4 @@ bit of the PAL. A successful run of the test involves the on-board LED blinking
** Build Procedure ** ** Build Procedure **
The demo has been tested using gcc version 9.3.1 (GNU Arm Embedded Toolchain 9-2020-q2-update). The demo has been tested using gcc version 9.3.1 (GNU Arm Embedded Toolchain 9-2020-q2-update).
Just modify the TRGT line in the makefile in order to use different GCC ports. Just modify the TRGT line in the makefile in order to use different GCC ports.

8
testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/PWM/Makefile
View File

@ -99,10 +99,10 @@ DEPDIR := ./.dep
# Licensing files. # Licensing files.
include $(CHIBIOS)/os/license/license.mk include $(CHIBIOS)/os/license/license.mk
# Startup files. # Startup files.
include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_NUC123SD4AN0.mk include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_NUC123.mk
# HAL-OSAL files (optional). # HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123SD4AN0/platform.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123/platform.mk
include $(CHIBIOS_CONTRIB)/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.mk include $(CHIBIOS_CONTRIB)/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.mk
include $(CHIBIOS)/os/hal/osal/os-less/ARMCMx/osal.mk include $(CHIBIOS)/os/hal/osal/os-less/ARMCMx/osal.mk
# RTOS files (optional). # RTOS files (optional).
@ -116,7 +116,7 @@ include $(CHIBIOS)/tools/mk/autobuild.mk
#include $(CHIBIOS)/test/oslib/oslib_test.mk #include $(CHIBIOS)/test/oslib/oslib_test.mk
# Define linker script file here # Define linker script file here
LDSCRIPT= $(STARTUPLD_CONTRIB)/NUC123SD4AN0.ld LDSCRIPT= $(STARTUPLD_CONTRIB)/NUC123xD4xx0.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global # C sources that can be compiled in ARM or THUMB mode depending on the global
# setting. # setting.
@ -200,4 +200,4 @@ flash: $(BUILDDIR)/$(PROJECT).elf
# #
# Custom rules # Custom rules
############################################################################## ##############################################################################

2
testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/PWM/cfg/mcuconf.h
View File

@ -29,6 +29,6 @@
#define NUC123_PLLSRC NUC123_PLLSRC_HSE #define NUC123_PLLSRC NUC123_PLLSRC_HSE
#define NUC123_HCLKSRC NUC123_HCLKSRC_PLL #define NUC123_HCLKSRC NUC123_HCLKSRC_PLL
#define NUC123SD4AN0_MCUCONF #define NUC123_MCUCONF
#endif /* _MCUCONF_H_ */ #endif /* _MCUCONF_H_ */