Rename PWR -> PMU
This commit is contained in:
Stefan Kerkmann
parent
4eef25ac2a
commit
116f34b808
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@ -266,32 +266,32 @@
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/** @} */
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/**
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* @name PWR interface specific RCU operations
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* @name PMU interface specific RCU operations
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* @{
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*/
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/**
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* @brief Enables the PWR interface clock.
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* @brief Enables the PMU interface clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rcuEnablePWRInterface(lp) rcuEnableAPB1(RCU_APB1ENR_PWREN, lp)
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#define rcuEnablePMUInterface(lp) rcuEnableAPB1(RCU_APB1ENR_PMUEN, lp)
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/**
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* @brief Disables PWR interface clock.
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* @brief Disables PMU interface clock.
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*
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* @api
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*/
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#define rcuDisablePWRInterface() rcuDisableAPB1(RCU_APB1ENR_PWREN)
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#define rcuDisablePMUInterface() rcuDisableAPB1(RCU_APB1ENR_PMUEN)
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/**
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* @brief Resets the PWR interface.
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* @brief Resets the PMU interface.
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*
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* @api
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*/
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#define rcuResetPWRInterface() rcuResetAPB1(RCU_APB1RSTR_PWRRST)
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#define rcuResetPMUInterface() rcuResetAPB1(RCU_APB1RSTR_PMURST)
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/** @} */
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/**
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@ -54,7 +54,7 @@ uint32_t SystemCoreClock = GD32_HCLK;
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static void hal_lld_backup_domain_init(void) {
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/* Backup domain access enabled and left open.*/
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PWR->CTL |= PWR_CR_DBP;
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PMU->CTL |= PMU_CR_DBP;
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#if HAL_USE_RTC
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/* Reset BKP domain if different clock source selected.*/
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@ -135,8 +135,8 @@ void hal_lld_init(void) {
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rcuResetAPB1(0xFFFFFFFF);
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rcuResetAPB2(0xFFFFFFFF);
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/* PWR and BD clocks enabled.*/
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rcuEnablePWRInterface(true);
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/* PMU and BD clocks enabled.*/
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rcuEnablePMUInterface(true);
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rcuEnableBKPInterface(true);
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/* Initializes the backup domain.*/
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@ -152,7 +152,7 @@ void hal_lld_init(void) {
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/* Programmable voltage detector enable.*/
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#if GD32_PVD_ENABLE
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PWR->CTL |= PWR_CR_PVDE | (GD32_PLS & GD32_PLS_MASK);
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PMU->CTL |= PMU_CR_PVDE | (GD32_PLS & GD32_PLS_MASK);
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#endif /* GD32_PVD_ENABLE */
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}
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@ -81,7 +81,7 @@
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/** @} */
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/**
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* @name PWR_CR register bits definitions
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* @name PMU_CR register bits definitions
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* @{
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*/
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#define GD32_PLS_MASK (7 << 5) /**< PLS bits mask. */
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@ -108,7 +108,7 @@
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* @{
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*/
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/**
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* @brief Disables the PWR/RCU initialization in the HAL.
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* @brief Disables the PMU/RCU initialization in the HAL.
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*/
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#if !defined(GD32_NO_INIT) || defined(__DOXYGEN__)
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#define GD32_NO_INIT FALSE
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@ -420,9 +420,9 @@ typedef struct
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typedef struct
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{
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__IO uint32_t CR;
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__IO uint32_t CSR;
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} PWR_TypeDef;
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__IO uint32_t CTL;
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__IO uint32_t CS;
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} PMU_TypeDef;
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/**
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* @brief Reset and Clock Control
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@ -667,7 +667,7 @@ typedef struct
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#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
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#define CAN2_BASE (APB1PERIPH_BASE + 0x00006800U)
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//#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
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#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
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#define PMU_BASE (APB1PERIPH_BASE + 0x00007000U)
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//#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
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//#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
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//#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
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@ -723,7 +723,7 @@ typedef struct
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#define USB_OTG_HOST_PORT_BASE 0x00000440U
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#define USB_OTG_HOST_CHANNEL_BASE 0x00000500U
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#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U
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#define USB_OTG_PWRCLKCTL_BASE 0x00000E00U
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#define USB_OTG_PMUCLKCTL_BASE 0x00000E00U
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#define USB_OTG_FIFO_BASE 0x00001000U
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#define USB_OTG_FIFO_SIZE 0x00001000U
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@ -755,7 +755,7 @@ typedef struct
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#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
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#define CAN2 ((CAN_TypeDef *)CAN2_BASE)
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#define BKP ((BKP_TypeDef *)BKP_BASE)
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#define PWR ((PWR_TypeDef *)PWR_BASE)
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#define PMU ((PMU_TypeDef *)PMU_BASE)
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#define DAC1 ((DAC_TypeDef *)DAC_BASE)
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#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
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#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
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@ -837,68 +837,68 @@ typedef struct
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/* */
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/******************************************************************************/
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/******************** Bit definition for PWR_CR register ********************/
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#define PWR_CR_LPDS_Pos (0U)
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#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
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#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
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#define PWR_CR_PDDS_Pos (1U)
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#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
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#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
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#define PWR_CR_CWUF_Pos (2U)
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#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
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#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
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#define PWR_CR_CSBF_Pos (3U)
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#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
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#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
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#define PWR_CR_PVDE_Pos (4U)
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#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
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#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
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/******************** Bit definition for PMU_CR register ********************/
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#define PMU_CR_LPDS_Pos (0U)
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#define PMU_CR_LPDS_Msk (0x1U << PMU_CR_LPDS_Pos) /*!< 0x00000001 */
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#define PMU_CR_LPDS PMU_CR_LPDS_Msk /*!< Low-Power Deepsleep */
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#define PMU_CR_PDDS_Pos (1U)
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#define PMU_CR_PDDS_Msk (0x1U << PMU_CR_PDDS_Pos) /*!< 0x00000002 */
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#define PMU_CR_PDDS PMU_CR_PDDS_Msk /*!< Power Down Deepsleep */
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#define PMU_CR_CWUF_Pos (2U)
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#define PMU_CR_CWUF_Msk (0x1U << PMU_CR_CWUF_Pos) /*!< 0x00000004 */
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#define PMU_CR_CWUF PMU_CR_CWUF_Msk /*!< Clear Wakeup Flag */
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#define PMU_CR_CSBF_Pos (3U)
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#define PMU_CR_CSBF_Msk (0x1U << PMU_CR_CSBF_Pos) /*!< 0x00000008 */
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#define PMU_CR_CSBF PMU_CR_CSBF_Msk /*!< Clear Standby Flag */
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#define PMU_CR_PVDE_Pos (4U)
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#define PMU_CR_PVDE_Msk (0x1U << PMU_CR_PVDE_Pos) /*!< 0x00000010 */
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#define PMU_CR_PVDE PMU_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
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#define PWR_CR_PLS_Pos (5U)
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#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
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#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
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#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
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#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
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#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
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#define PMU_CR_PLS_Pos (5U)
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#define PMU_CR_PLS_Msk (0x7U << PMU_CR_PLS_Pos) /*!< 0x000000E0 */
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#define PMU_CR_PLS PMU_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
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#define PMU_CR_PLS_0 (0x1U << PMU_CR_PLS_Pos) /*!< 0x00000020 */
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#define PMU_CR_PLS_1 (0x2U << PMU_CR_PLS_Pos) /*!< 0x00000040 */
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#define PMU_CR_PLS_2 (0x4U << PMU_CR_PLS_Pos) /*!< 0x00000080 */
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/*!< PVD level configuration */
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#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
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#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
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#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
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#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
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#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
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#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
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#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
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#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
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#define PMU_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
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#define PMU_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
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#define PMU_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
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#define PMU_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
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#define PMU_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
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#define PMU_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
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#define PMU_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
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#define PMU_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
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/* Legacy defines */
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#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
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#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
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#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
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#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
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#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
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#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
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#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
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#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
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#define PMU_CR_PLS_2V2 PMU_CR_PLS_LEV0
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#define PMU_CR_PLS_2V3 PMU_CR_PLS_LEV1
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#define PMU_CR_PLS_2V4 PMU_CR_PLS_LEV2
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#define PMU_CR_PLS_2V5 PMU_CR_PLS_LEV3
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#define PMU_CR_PLS_2V6 PMU_CR_PLS_LEV4
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#define PMU_CR_PLS_2V7 PMU_CR_PLS_LEV5
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#define PMU_CR_PLS_2V8 PMU_CR_PLS_LEV6
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#define PMU_CR_PLS_2V9 PMU_CR_PLS_LEV7
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#define PWR_CR_DBP_Pos (8U)
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#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
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#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
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#define PMU_CR_DBP_Pos (8U)
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#define PMU_CR_DBP_Msk (0x1U << PMU_CR_DBP_Pos) /*!< 0x00000100 */
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#define PMU_CR_DBP PMU_CR_DBP_Msk /*!< Disable Backup Domain write protection */
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/******************* Bit definition for PWR_CSR register ********************/
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#define PWR_CSR_WUF_Pos (0U)
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#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
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#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
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#define PWR_CSR_SBF_Pos (1U)
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#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
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#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
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#define PWR_CSR_PVDO_Pos (2U)
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#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
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#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
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#define PWR_CSR_EWUP_Pos (8U)
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#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
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#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
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/******************* Bit definition for PMU_CSR register ********************/
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#define PMU_CSR_WUF_Pos (0U)
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#define PMU_CSR_WUF_Msk (0x1U << PMU_CSR_WUF_Pos) /*!< 0x00000001 */
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#define PMU_CSR_WUF PMU_CSR_WUF_Msk /*!< Wakeup Flag */
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#define PMU_CSR_SBF_Pos (1U)
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#define PMU_CSR_SBF_Msk (0x1U << PMU_CSR_SBF_Pos) /*!< 0x00000002 */
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#define PMU_CSR_SBF PMU_CSR_SBF_Msk /*!< Standby Flag */
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#define PMU_CSR_PVDO_Pos (2U)
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#define PMU_CSR_PVDO_Msk (0x1U << PMU_CSR_PVDO_Pos) /*!< 0x00000004 */
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#define PMU_CSR_PVDO PMU_CSR_PVDO_Msk /*!< PVD Output */
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#define PMU_CSR_EWUP_Pos (8U)
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#define PMU_CSR_EWUP_Msk (0x1U << PMU_CSR_EWUP_Pos) /*!< 0x00000100 */
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#define PMU_CSR_EWUP PMU_CSR_EWUP_Msk /*!< Enable WKUP pin */
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/******************************************************************************/
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/* */
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@ -1518,9 +1518,9 @@ typedef struct
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#define RCU_APB1RSTR_BKPRST_Pos (27U)
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#define RCU_APB1RSTR_BKPRST_Msk (0x1U << RCU_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
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#define RCU_APB1RSTR_BKPRST RCU_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
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#define RCU_APB1RSTR_PWRRST_Pos (28U)
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#define RCU_APB1RSTR_PWRRST_Msk (0x1U << RCU_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
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#define RCU_APB1RSTR_PWRRST RCU_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
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#define RCU_APB1RSTR_PMURST_Pos (28U)
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#define RCU_APB1RSTR_PMURST_Msk (0x1U << RCU_APB1RSTR_PMURST_Pos) /*!< 0x10000000 */
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#define RCU_APB1RSTR_PMURST RCU_APB1RSTR_PMURST_Msk /*!< Power interface reset */
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#define RCU_APB1RSTR_TIM3RST_Pos (2U)
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#define RCU_APB1RSTR_TIM3RST_Msk (0x1U << RCU_APB1RSTR_TIM3RST_Pos) /*!< 0x00000004 */
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@ -1654,9 +1654,9 @@ typedef struct
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#define RCU_APB1ENR_BKPEN_Pos (27U)
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#define RCU_APB1ENR_BKPEN_Msk (0x1U << RCU_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
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#define RCU_APB1ENR_BKPEN RCU_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
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#define RCU_APB1ENR_PWREN_Pos (28U)
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#define RCU_APB1ENR_PWREN_Msk (0x1U << RCU_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
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#define RCU_APB1ENR_PWREN RCU_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
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#define RCU_APB1ENR_PMUEN_Pos (28U)
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#define RCU_APB1ENR_PMUEN_Msk (0x1U << RCU_APB1ENR_PMUEN_Pos) /*!< 0x10000000 */
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#define RCU_APB1ENR_PMUEN RCU_APB1ENR_PMUEN_Msk /*!< Power interface clock enable */
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#define RCU_APB1ENR_TIM3EN_Pos (2U)
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#define RCU_APB1ENR_TIM3EN_Msk (0x1U << RCU_APB1ENR_TIM3EN_Pos) /*!< 0x00000004 */
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@ -1756,9 +1756,9 @@ typedef struct
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#define RCU_CSR_WWDGRSTF_Pos (30U)
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#define RCU_CSR_WWDGRSTF_Msk (0x1U << RCU_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
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#define RCU_CSR_WWDGRSTF RCU_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
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#define RCU_CSR_LPWRRSTF_Pos (31U)
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#define RCU_CSR_LPWRRSTF_Msk (0x1U << RCU_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
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#define RCU_CSR_LPWRRSTF RCU_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
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#define RCU_CSR_LPMURSTF_Pos (31U)
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#define RCU_CSR_LPMURSTF_Msk (0x1U << RCU_CSR_LPMURSTF_Pos) /*!< 0x80000000 */
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#define RCU_CSR_LPMURSTF RCU_CSR_LPMURSTF_Msk /*!< Low-Power reset flag */
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/******************* Bit definition for RCU_AHBRSTR register ****************/
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#define RCU_AHBRSTR_OTGFSRST_Pos (12U)
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