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sn32: further cleanup the LLD 

SysTick driver is now seperate from CT
stale 240 non B code removed
CMSIS version is now on 1.8R
This commit is contained in:
Dimitris Mantzouranis 2021-10-02 16:16:00 +03:00
parent de5d4799da
commit 11db8a941b
31 changed files with 2914 additions and 4600 deletions
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272
os/hal/ports/SN32/LLD/SN32F24xB/ADC/ADC.c
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@ -1,142 +1,130 @@
/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: ADC related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F200_Def.h>
#include "ADC.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
uint8_t bADC_StartConv;
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : ADC_Init
* Description : Initialization of ADC
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void ADC_Init(void)
{
SN_SYS1->AHBCLKEN |= (0x01 << 11); //Enables HCLK for ADC
//Set ADC PCLK
SN_SYS1->APBCP0 |= (0x00 << 16); //ADC PCLK = HCLK/1
//SN_SYS1->APBCP0 |= (0x01 << 16); //ADC PCLK = HCLK/2
//SN_SYS1->APBCP0 |= (0x02 << 16); //ADC PCLK = HCLK/4
//SN_SYS1->APBCP0 |= (0x03 << 16); //ADC PCLK = HCLK/8
//SN_SYS1->APBCP0 |= (0x04 << 16); //ADC PCLK = HCLK/16
SN_ADC->ADM_b.ADENB = ADC_ADENB_EN; //Enable ADC
UT_DelayNx10us(10); //Delay 100us
SN_ADC->ADM_b.AVREFHSEL = ADC_AVREFHSEL_INTERNAL; //Set ADC high reference voltage source from internal VDD
SN_ADC->ADM_b.GCHS = ADC_GCHS_EN; //Enable ADC global channel
SN_ADC->ADM_b.ADLEN = ADC_ADLEN_12BIT; //Set ADC resolution = 12-bit
SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV32; //ADC_CLK = ADC_PCLK/32
#if ADC_FUNCTION_TYPE == ADC_TYPE
SN_ADC->ADM_b.CHS = ADC_CHS_AIN1; //Set P2.1 as ADC input channel
SN_ADC->IE |= ADC_IE_AIN1; //Enable ADC channel P2.1 interrupt
#endif
#if ADC_FUNCTION_TYPE == TS_TYPE
SN_ADC->ADM_b.TSENB = ADC_TSENB_EN; //Enable Temperature Sensor
SN_ADC->ADM_b.CHS = ADC_CHS_TS; //Set P2.14 as Temperature Sensor channel
SN_ADC->IE |= ADC_IE_TS; //Enable Temperature Sensor interrupt
#endif
ADC_NvicEnable(); //Enable ADC NVIC interrupt
}
/*****************************************************************************
* Function : ADC_Read
* Description : Read ADC converted data
* Input : None
* Output : None
* Return : Data in ADB register
* Note : None
*****************************************************************************/
uint16_t ADC_Read(void)
{
return SN_ADC->ADB;
}
/*****************************************************************************
* Function : ADC_IRQHandler
* Description : ISR of ADC interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void ADC_IRQHandler(void)
{
bADC_StartConv = 0;
SN_ADC->RIS = 0x0; //clear interrupt flag
}
/*****************************************************************************
* Function : ADC_NvicEnable
* Description : Enable ADC interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void ADC_NvicEnable(void)
{
NVIC_ClearPendingIRQ(ADC_IRQn);
NVIC_EnableIRQ(ADC_IRQn);
NVIC_SetPriority(ADC_IRQn,0); // Set interrupt priority (default)
}
/*****************************************************************************
* Function : ADC_NvicDisable
* Description : Disable ADC interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void ADC_NvicDisable(void)
{
NVIC_DisableIRQ(ADC_IRQn);
}
/******************** (C) COPYRIGHT 2017 SONiX *******************************
* COMPANY: SONiX
* DATE: 2017/07
* AUTHOR: SA1
* IC: SN32F240B
* DESCRIPTION: ADC related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2017/07/07 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F200_Def.h>
#include "ADC.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
uint8_t bADC_StartConv;
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : ADC_Init
* Description : Initialization of ADC
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void ADC_Init(void)
{
SN_SYS1->AHBCLKEN_b.ADCCLKEN = 1; //Enables HCLK for ADC
SN_ADC->ADM_b.ADENB = ADC_ADENB_EN; //Enable ADC
UT_DelayNx10us(10); //Delay 100us
SN_ADC->ADM_b.AVREFHSEL = ADC_AVREFHSEL_INTERNAL; //Set ADC high reference voltage source from internal reference
SN_ADC->ADM_b.VHS = ADC_VHS_VDD; //Set ADC high reference voltage source as VDD
SN_ADC->ADM_b.GCHS = ADC_GCHS_EN; //Enable ADC global channel
SN_ADC->ADM_b.ADLEN = ADC_ADLEN_12BIT; //Set ADC resolution = 12-bit
SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV1; //ADC_CLK = ADC_PCLK/1
//SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV2; //ADC_CLK = ADC_PCLK/2
//SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV4; //ADC_CLK = ADC_PCLK/4
//SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV8; //ADC_CLK = ADC_PCLK/8
//SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV16; //ADC_CLK = ADC_PCLK/16
//SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV32; //ADC_CLK = ADC_PCLK/32
SN_ADC->ADM_b.CHS = ADC_CHS_AIN1; //Set P2.1 as ADC input channel
SN_ADC->IE |= ADC_IE_AIN1; //Enable ADC channel P2.1 interrupt
ADC_NvicEnable(); //Enable ADC NVIC interrupt
}
/*****************************************************************************
* Function : ADC_Read
* Description : Read ADC converted data
* Input : None
* Output : None
* Return : Data in ADB register
* Note : None
*****************************************************************************/
uint16_t ADC_Read(void)
{
return SN_ADC->ADB;
}
/*****************************************************************************
* Function : ADC_IRQHandler
* Description : ISR of ADC interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void ADC_IRQHandler(void)
{
bADC_StartConv = 0;
SN_ADC->RIS = 0x0; //clear interrupt flag
}
/*****************************************************************************
* Function : ADC_NvicEnable
* Description : Enable ADC interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void ADC_NvicEnable(void)
{
NVIC_ClearPendingIRQ(ADC_IRQn);
NVIC_EnableIRQ(ADC_IRQn);
NVIC_SetPriority(ADC_IRQn,0); // Set interrupt priority (default)
}
/*****************************************************************************
* Function : ADC_NvicDisable
* Description : Disable ADC interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void ADC_NvicDisable(void)
{
NVIC_DisableIRQ(ADC_IRQn);
}

226
os/hal/ports/SN32/LLD/SN32F24xB/ADC/ADC.h
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@ -1,109 +1,117 @@
#ifndef __SN32F240_ADC_H
#define __SN32F240_ADC_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
//ADC function Type
#define ADC_FUNCTION_TYPE ADC_TYPE //ADC_TYPE, TS_TYPE
#define ADC_TYPE 0 //ADC function
#define TS_TYPE 1 //Temperature Sensor function
//Temperature sensor enable bit
#define ADC_TSENB_DIS 0x0
#define ADC_TSENB_EN 0x1
//ADC high reference voltage source select bit
#define ADC_AVREFHSEL_INTERNAL 0x0
#define ADC_AVREFHSEL_EXTERNAL 0x1
//ADC Enable bit
#define ADC_ADENB_DIS 0x0
#define ADC_ADENB_EN 0x1
//ADC Clock source divider
#define ADC_ADCKS_DIV1 0x0
#define ADC_ADCKS_DIV2 0x1
#define ADC_ADCKS_DIV4 0x2
#define ADC_ADCKS_DIV8 0x3
#define ADC_ADCKS_DIV16 0x5
#define ADC_ADCKS_DIV32 0x6
//ADC resolution control bit
#define ADC_ADLEN_8BIT 0x0
#define ADC_ADLEN_12BIT 0x1
//ADC start control bit
#define ADC_ADS_STOP 0x0
#define ADC_ADS_START 0x1
//ADC global channel select bit
#define ADC_GCHS_DIS 0x0
#define ADC_GCHS_EN 0x1
//ADC input channels select bit
#define ADC_CHS_AIN0 0x0 //P2.0
#define ADC_CHS_AIN1 0x1 //P2.1
#define ADC_CHS_AIN2 0x2 //P2.2
#define ADC_CHS_AIN3 0x3 //P2.3
#define ADC_CHS_AIN4 0x4 //P2.4
#define ADC_CHS_AIN5 0x5 //P2.5
#define ADC_CHS_AIN6 0x6 //P2.6
#define ADC_CHS_AIN7 0x7 //P2.7
#define ADC_CHS_AIN8 0x8 //P2.8
#define ADC_CHS_AIN9 0x9 //P2.9
#define ADC_CHS_AIN10 0xA //P2.10
#define ADC_CHS_AIN11 0xB //P2.11
#define ADC_CHS_AIN12 0xC //P2.12
#define ADC_CHS_AIN13 0xD //P2.13
#define ADC_CHS_TS 0xE //Temperature Sensor
//ADC Interrupt Enable register(ADC_IE)
#define ADC_IE_AIN0 0x0001
#define ADC_IE_AIN1 0x0002
#define ADC_IE_AIN2 0x0004
#define ADC_IE_AIN3 0x0008
#define ADC_IE_AIN4 0x0010
#define ADC_IE_AIN5 0x0020
#define ADC_IE_AIN6 0x0040
#define ADC_IE_AIN7 0x0080
#define ADC_IE_AIN8 0x0100
#define ADC_IE_AIN9 0x0200
#define ADC_IE_AIN10 0x0400
#define ADC_IE_AIN11 0x0800
#define ADC_IE_AIN12 0x1000
#define ADC_IE_AIN13 0x2000
#define ADC_IE_TS 0x4000
//ADC Raw Interrupt Status register(ADC_RIS)
#define mskADC_IF_AIN0 (0x1<<0) //P2.0
#define mskADC_IF_AIN1 (0x1<<1) //P2.1
#define mskADC_IF_AIN2 (0x1<<2) //P2.2
#define mskADC_IF_AIN3 (0x1<<3) //P2.3
#define mskADC_IF_AIN4 (0x1<<4) //P2.4
#define mskADC_IF_AIN5 (0x1<<5) //P2.5
#define mskADC_IF_AIN6 (0x1<<6) //P2.6
#define mskADC_IF_AIN7 (0x1<<7) //P2.7
#define mskADC_IF_AIN8 (0x1<<8) //P2.8
#define mskADC_IF_AIN9 (0x1<<9) //P2.9
#define mskADC_IF_AIN10 (0x1<<10) //P2.10
#define mskADC_IF_AIN11 (0x1<<11) //P2.11
#define mskADC_IF_AIN12 (0x1<<12) //P2.12
#define mskADC_IF_AIN13 (0x1<<13) //P2.13
#define mskADC_IF_TS (0x1<<14) //Temperature Sensor
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern uint8_t bADC_StartConv;
void ADC_Init(void);
uint16_t ADC_Read(void);
void ADC_NvicEnable(void);
void ADC_NvicDisable(void);
#endif /*__SN32F240_ADC_H*/
#ifndef __SN32F240B_ADC_H
#define __SN32F240B_ADC_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
//ADC Internal Reference Voltage level
#define ADC_VHS_INTERNAL_2V 0
#define ADC_VHS_INTERNAL_3V 1
#define ADC_VHS_INTERNAL_4P5V 2
#define ADC_VHS_VDD 7
//ADC high reference voltage source select bit
#define ADC_AVREFHSEL_INTERNAL 0x0
#define ADC_AVREFHSEL_EXTERNAL 0x1
//ADC Enable bit
#define ADC_ADENB_DIS 0x0
#define ADC_ADENB_EN 0x1
//ADC Clock source divider
#define ADC_ADCKS_DIV1 0x0
#define ADC_ADCKS_DIV2 0x1
#define ADC_ADCKS_DIV4 0x2
#define ADC_ADCKS_DIV8 0x3
#define ADC_ADCKS_DIV16 0x5
#define ADC_ADCKS_DIV32 0x6
//ADC resolution control bit
#define ADC_ADLEN_8BIT 0x0
#define ADC_ADLEN_12BIT 0x1
//ADC start control bit
#define ADC_ADS_STOP 0x0
#define ADC_ADS_START 0x1
//ADC global channel select bit
#define ADC_GCHS_DIS 0x0
#define ADC_GCHS_EN 0x1
//ADC input channels select bit
#define ADC_CHS_AIN0 0x0 //P2.0
#define ADC_CHS_AIN1 0x1 //P2.1
#define ADC_CHS_AIN2 0x2 //P2.2
#define ADC_CHS_AIN3 0x3 //P2.3
#define ADC_CHS_AIN4 0x4 //P2.4
#define ADC_CHS_AIN5 0x5 //P2.5
#define ADC_CHS_AIN6 0x6 //P2.6
#define ADC_CHS_AIN7 0x7 //P2.7
#define ADC_CHS_AIN8 0x8 //P2.8
#define ADC_CHS_AIN9 0x9 //P2.9
#define ADC_CHS_AIN10 0xA //P2.10
#define ADC_CHS_AIN11 0xB //P2.11
#define ADC_CHS_AIN12 0xC //P2.12
#define ADC_CHS_AIN13 0xD //P2.13
#define ADC_CHS_AIN14 0xE //P2.14
#define ADC_CHS_AIN15 0xF //P2.15
#define ADC_CHS_AIN16 0x10 //Internal Ref. Voltage
#define ADC_CHS_AIN17 0x11 //VDD
#define ADC_CHS_AIN18 0x12 //VSS
//ADC Interrupt Enable register(ADC_IE)
#define ADC_IE_AIN0 0x00001
#define ADC_IE_AIN1 0x00002
#define ADC_IE_AIN2 0x00004
#define ADC_IE_AIN3 0x00008
#define ADC_IE_AIN4 0x00010
#define ADC_IE_AIN5 0x00020
#define ADC_IE_AIN6 0x00040
#define ADC_IE_AIN7 0x00080
#define ADC_IE_AIN8 0x00100
#define ADC_IE_AIN9 0x00200
#define ADC_IE_AIN10 0x00400
#define ADC_IE_AIN11 0x00800
#define ADC_IE_AIN12 0x01000
#define ADC_IE_AIN13 0x02000
#define ADC_IE_AIN14 0x04000
#define ADC_IE_AIN15 0x08000
#define ADC_IE_AIN16 0x10000
#define ADC_IE_AIN17 0x20000
#define ADC_IE_AIN18 0x40000
//ADC Raw Interrupt Status register(ADC_RIS)
#define mskADC_IF_AIN0 (0x1<<0) //P2.0
#define mskADC_IF_AIN1 (0x1<<1) //P2.1
#define mskADC_IF_AIN2 (0x1<<2) //P2.2
#define mskADC_IF_AIN3 (0x1<<3) //P2.3
#define mskADC_IF_AIN4 (0x1<<4) //P2.4
#define mskADC_IF_AIN5 (0x1<<5) //P2.5
#define mskADC_IF_AIN6 (0x1<<6) //P2.6
#define mskADC_IF_AIN7 (0x1<<7) //P2.7
#define mskADC_IF_AIN8 (0x1<<8) //P2.8
#define mskADC_IF_AIN9 (0x1<<9) //P2.9
#define mskADC_IF_AIN10 (0x1<<10) //P2.10
#define mskADC_IF_AIN11 (0x1<<11) //P2.11
#define mskADC_IF_AIN12 (0x1<<12) //P2.12
#define mskADC_IF_AIN13 (0x1<<13) //P2.13
#define mskADC_IF_AIN14 (0x1<<14) //P2.14
#define mskADC_IF_AIN15 (0x1<<15) //P2.15
#define mskADC_IF_AIN16 (0x1<<16) //Internal Ref. Voltage
#define mskADC_IF_AIN17 (0x1<<17) //VDD
#define mskADC_IF_AIN18 (0x1<<18) //VSS
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern uint8_t bADC_StartConv;
void ADC_Init(void);
uint16_t ADC_Read(void);
void ADC_NvicEnable(void);
void ADC_NvicDisable(void);
#endif /*__SN32F240B_ADC_H*/

8
os/hal/ports/SN32/LLD/SN32F24xB/CT/driver.mk
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@ -1,11 +1,11 @@
ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_CT TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/hal_st_lld.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16B0.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16B1.c
endif
else
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/hal_st_lld.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16B0.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16B1.c
endif
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16B1.c
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT

1589
os/hal/ports/SN32/LLD/SN32F24xB/GPIO/GPIO.c
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224
os/hal/ports/SN32/LLD/SN32F24xB/GPIO/GPIO.h
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@ -1,114 +1,110 @@
#ifndef __SN32F240_GPIO_H
#define __SN32F240_GPIO_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4004 4000 (GPIO 0)
0x4004 6000 (GPIO 1)
0x4004 8000 (GPIO 2)
0x4004 A000 (GPIO 3)
*/
/* GPIO Port n Data register <GPIOn_DATA> (0x00) */
/* GPIO Port n Mode register <GPIOn_MODE> (0x04) */
#define GPIO_MODE_INPUT 0
#define GPIO_MODE_OUTPUT 1
#define GPIO_CURRENT_10MA 0
#define GPIO_CURRENT_20MA 1
/* GPIO Port n Configuration register <GPIOn_CFG> (0x08) */
#define GPIO_CFG_PULL_UP 0
#define GPIO_CFG_PULL_DOWN 1
#define GPIO_CFG_PULL_INACTIVE 2
#define GPIO_CFG_REPEATER_MODE 3
/* GPIO Port n Interrupt Sense register <GPIOn_IS> (0x0C) */
#define GPIO_IS_EDGE 0
#define GPIO_IS_EVENT 1
/* GPIO Port n Interrupt Both-edge Sense registe <GPIOn_IBS> (0x10) */
#define GPIO_IBS_EDGE_TRIGGER 0
#define GPIO_IBS_BOTH_EDGE_TRIGGER 1
/* GPIO Port n Interrupt Event register <GPIOn_IEV> (0x14) */
#define GPIO_IEV_RISING_EDGE 0
#define GPIO_IEV_FALLING_EDGE 1
/* GPIO Port n Interrupt Enable register <GPIOn_IE> (0x18) */
#define GPIO_IE_DIS 0
#define GPIO_IE_EN 1
/* GPIO Port n Raw Interrupt Status register <GPIOn_RIS/GPIOn_IC> (0x1C/0x20) */
#define mskPIN0IF (0x1<<0)
#define mskPIN1IF (0x1<<1)
#define mskPIN2IF (0x1<<2)
#define mskPIN3IF (0x1<<3)
#define mskPIN4IF (0x1<<4)
#define mskPIN5IF (0x1<<5)
#define mskPIN6IF (0x1<<6)
#define mskPIN7IF (0x1<<7)
#define mskPIN8IF (0x1<<8)
#define mskPIN9IF (0x1<<9)
#define mskPIN10IF (0x1<<10)
#define mskPIN11IF (0x1<<11)
#define mskPIN12IF (0x1<<12)
#define mskPIN13IF (0x1<<13)
#define mskPIN14IF (0x1<<14)
#define mskPIN15IF (0x1<<15)
/* GPIO Port Name Define */
//GPIO name define
#define GPIO_PORT0 0
#define GPIO_PORT1 1
#define GPIO_PORT2 2
#define GPIO_PORT3 3
/* GPIO Pin Name Define */
#define GPIO_PIN0 0
#define GPIO_PIN1 1
#define GPIO_PIN2 2
#define GPIO_PIN3 3
#define GPIO_PIN4 4
#define GPIO_PIN5 5
#define GPIO_PIN6 6
#define GPIO_PIN7 7
#define GPIO_PIN8 8
#define GPIO_PIN9 9
#define GPIO_PIN10 10
#define GPIO_PIN11 11
#define GPIO_PIN12 12
#define GPIO_PIN13 13
#define GPIO_PIN14 14
#define GPIO_PIN15 15
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
void GPIO_Init (void);
void GPIO_Mode(uint32_t port_number, uint32_t pin_number, uint32_t mode);
void GPIO_Set(uint32_t port_number, uint32_t pin_number);
void GPIO_Clr(uint32_t port_number, uint32_t pin_number);
void GPIO_P0Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev);
void GPIO_P1Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev);
void GPIO_P2Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev);
void GPIO_P3Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev);
void GPIO_Interrupt(uint32_t port_number, uint32_t pin_number, uint32_t enable);
void GPIO_IntClr(uint32_t port_number, uint32_t pin_number);
void GPIO_Config(uint32_t port_number, uint32_t pin_number, uint32_t value);
void GPIO_OpenDrain(uint32_t port_number, uint32_t pin_number, uint32_t value);
uint32_t GPIO_IntStatus(uint32_t port_number, uint32_t pin_number);
#endif /*__SN32F240_GPIO_H*/
#ifndef __SN32F240B_GPIO_H
#define __SN32F240B_GPIO_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4004 4000 (GPIO 0)
0x4004 6000 (GPIO 1)
0x4004 8000 (GPIO 2)
0x4004 A000 (GPIO 3)
*/
/* GPIO Port n Data register <GPIOn_DATA> (0x00) */
/* GPIO Port n Mode register <GPIOn_MODE> (0x04) */
#define GPIO_MODE_INPUT 0
#define GPIO_MODE_OUTPUT 1
/* GPIO Port n Configuration register <GPIOn_CFG> (0x08) */
#define GPIO_CFG_PULL_UP 0
#define GPIO_CFG_INACTIVE_Schmitt_EN 2
#define GPIO_CFG_INACTIVE_Schmitt_DIS 3
/* GPIO Port n Interrupt Sense register <GPIOn_IS> (0x0C) */
#define GPIO_IS_EDGE 0
#define GPIO_IS_EVENT 1
/* GPIO Port n Interrupt Both-edge Sense registe <GPIOn_IBS> (0x10) */
#define GPIO_IBS_EDGE_TRIGGER 0
#define GPIO_IBS_BOTH_EDGE_TRIGGER 1
/* GPIO Port n Interrupt Event register <GPIOn_IEV> (0x14) */
#define GPIO_IEV_RISING_EDGE 0
#define GPIO_IEV_FALLING_EDGE 1
/* GPIO Port n Interrupt Enable register <GPIOn_IE> (0x18) */
#define GPIO_IE_DIS 0
#define GPIO_IE_EN 1
/* GPIO Port n Raw Interrupt Status register <GPIOn_RIS/GPIOn_IC> (0x1C/0x20) */
#define mskPIN0IF (0x1<<0)
#define mskPIN1IF (0x1<<1)
#define mskPIN2IF (0x1<<2)
#define mskPIN3IF (0x1<<3)
#define mskPIN4IF (0x1<<4)
#define mskPIN5IF (0x1<<5)
#define mskPIN6IF (0x1<<6)
#define mskPIN7IF (0x1<<7)
#define mskPIN8IF (0x1<<8)
#define mskPIN9IF (0x1<<9)
#define mskPIN10IF (0x1<<10)
#define mskPIN11IF (0x1<<11)
#define mskPIN12IF (0x1<<12)
#define mskPIN13IF (0x1<<13)
#define mskPIN14IF (0x1<<14)
#define mskPIN15IF (0x1<<15)
/* GPIO Port Name Define */
//GPIO name define
#define GPIO_PORT0 0
#define GPIO_PORT1 1
#define GPIO_PORT2 2
#define GPIO_PORT3 3
/* GPIO Pin Name Define */
#define GPIO_PIN0 0
#define GPIO_PIN1 1
#define GPIO_PIN2 2
#define GPIO_PIN3 3
#define GPIO_PIN4 4
#define GPIO_PIN5 5
#define GPIO_PIN6 6
#define GPIO_PIN7 7
#define GPIO_PIN8 8
#define GPIO_PIN9 9
#define GPIO_PIN10 10
#define GPIO_PIN11 11
#define GPIO_PIN12 12
#define GPIO_PIN13 13
#define GPIO_PIN14 14
#define GPIO_PIN15 15
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
void GPIO_Init (void);
void GPIO_Mode(uint32_t port_number, uint32_t pin_number, uint32_t mode);
void GPIO_Set(uint32_t port_number, uint32_t pin_number);
void GPIO_Clr(uint32_t port_number, uint32_t pin_number);
void GPIO_P0Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev);
void GPIO_P1Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev);
void GPIO_P2Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev);
void GPIO_P3Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev);
void GPIO_Interrupt(uint32_t port_number, uint32_t pin_number, uint32_t enable);
void GPIO_IntClr(uint32_t port_number, uint32_t pin_number);
void GPIO_Config(uint32_t port_number, uint32_t pin_number, uint32_t value);
void GPIO_OpenDrain(uint32_t port_number, uint32_t pin_number, uint32_t value);
uint32_t GPIO_IntStatus(uint32_t port_number, uint32_t pin_number);
#endif /*__SN32F240B_GPIO_H*/

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os/hal/ports/SN32/LLD/SN32F24xB/I2C/I2C.c Normal file
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/******************** (C) COPYRIGHT 2017 SONiX *******************************
* COMPANY: SONiX
* DATE: 2017/07
* AUTHOR: SA1
* IC: SN32F240B
* DESCRIPTION: I2C0 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2017/07/07 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F200_Def.h>
#include "I2C.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
uint8_t bI2C_RxFIFO[I2C_RX_FIFO_LENGTH];
uint8_t bI2C_TxFIFO[I2C_TX_FIFO_LENGTH] = {0};
uint8_t bI2C_RxFIFO_cnts, bI2C_Rx_cnts;
uint8_t bI2C_TxFIFO_cnts, bI2C_Tx_cnts;
uint8_t *bTX_ptr;
uint8_t EEPROM_ADR_H, EEPROM_ADR_L;
uint8_t EEPROM_WR; // 0 : write
// 1 : read
uint8_t Busy = 1, Error = 0;
uint8_t Read_Down = 0;
uint8_t Send_Address;
uint8_t temp = 0;
volatile uint8_t Timeout = 0;
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : I2C_Init
* Description : Initialization of I2C
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C_Init (void)
{
SN_SYS1->AHBCLKEN_b.I2C0CLKEN = 1; //Enables HCLK for I2C0
//I2C speed
SN_I2C0->SCLHT = I2C0_SCLHT;
SN_I2C0->SCLLT = I2C0_SCLLT;
SN_I2C0->CTRL_b.I2CEN = 1; //Enable I2C
//===NVIC===
NVIC_ClearPendingIRQ(I2C0_IRQn);
NVIC_EnableIRQ(I2C0_IRQn);
}
/*****************************************************************************
* Function : I2C_Start
* Description : transmit a START bit
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C_Start(void)
{
SN_I2C0->CTRL_b.STA = 1;
}
/*****************************************************************************
* Function : I2C_Stop
* Description : transmit a STOP condition in master mode
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C_Stop(void)
{
SN_I2C0->CTRL_b.STO = 1;
}
/*****************************************************************************
* Function : I2C_Read
* Description : read N Byte data from EEPROM
* Input : eeprom_adr - data word address
* : read_num - byte length
* Output : None
* Return : OK or Fail
* Note : None
*****************************************************************************/
uint8_t I2C_Read(uint16_t eeprom_adr, uint8_t read_num)
{
bI2C_Rx_cnts = 0;
EEPROM_ADR_H = eeprom_adr >> 8; //data word address low byte
EEPROM_ADR_L = eeprom_adr & 0x00ff; //data word address high byte
bI2C_RxFIFO_cnts = read_num; //byte length
Busy = 1;
EEPROM_WR = 0; //write
I2C_Start(); //I2C start
SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
Send_Address = 1; //data word address setting flag
while(Busy == 1 && Timeout == 0);
SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt
if(Error == 1 || Timeout == 1) return FALSE;
#if (EEPROM_less_than_32K == 0)
SN_I2C0->TXDATA = EEPROM_ADR_H; //data word address high byte
SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
Busy = 1;
while(Busy == 1 && Timeout == 0);
SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt
if(Error == 1 || Timeout == 1) return FALSE;
#endif
SN_I2C0->TXDATA = EEPROM_ADR_L; //data word address low byte
SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
Busy = 1;
while(Busy == 1 && Timeout == 0);
SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt
if(Error == 1 || Timeout == 1) return FALSE;
Read_Down = 0;
Send_Address = 0;
EEPROM_WR = 1; //read
I2C_Start(); //I2C start
SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
while(Read_Down == 0 && Timeout == 0);
SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt
Read_Down = 0;
if(Error == 1 || Timeout == 1) return FALSE;
return TRUE;
}
/*****************************************************************************
* Function : I2C_Write
* Description : write N Byte data to EEPROM
* Input : eeprom_adr - data word address
* : write_num - byte length
* Output : None
* Return : OK or Fail
* Note : None
*****************************************************************************/
uint8_t I2C_Write(uint16_t eeprom_adr, uint8_t write_num)
{
Timeout = 0;
bI2C_Tx_cnts = 0;
bTX_ptr = &bI2C_TxFIFO[0]; //write data buffer
EEPROM_ADR_H = eeprom_adr >> 8; //data word address high byte
EEPROM_ADR_L = eeprom_adr & 0x00ff; //data word address low byte
bI2C_TxFIFO_cnts = write_num; //byte length
Busy = 1;
EEPROM_WR = 0; //write
SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
I2C_Start(); //I2C start
Send_Address = 1; //data word address setting flag
while(Busy == 1 && Timeout == 0);
SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt
if(Error == 1 || Timeout == 1) return FALSE;
#if (EEPROM_less_than_32K == 0)
SN_I2C0->TXDATA = EEPROM_ADR_H; //data word address high byte
SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
Busy = 1;
while(Busy == 1 && Timeout == 0);
SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt
if(Error == 1 || Timeout == 1) return FALSE;
#endif
SN_I2C0->TXDATA = EEPROM_ADR_L; //data word address low byte
SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
Busy = 1;
while(Busy == 1 && Timeout == 0);
if(Error == 1 || Timeout == 1 ) return FALSE;
SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt
Send_Address = 0;
SN_I2C0->TXDATA = *bTX_ptr++; //write data
SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
Busy = 1;
while(Busy == 1 && Timeout == 0);
if(Error == 1 || Timeout == 1) return FALSE;
SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt
Busy = 1;
I2C_Stop();
SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
while(Busy == 1 && Timeout == 0);
if(Error == 1 || Timeout == 1) return FALSE;
SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt
return TRUE;
}
/*****************************************************************************
* Function : I2C_IRQHandler
* Description : I2C interrupt service routine
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void I2C0_IRQHandler(void)
{
if(((SN_I2C0->STAT) & (mskI2C_LOST_ARB_LOST_ARBITRATION)) == Lost_Arbitration)
{
SN_I2C0->STAT_b.I2CIF = 1;
SN_I2C0->CTRL_b.I2CEN = 0; //Disable I2C
SN_I2C0->CTRL_b.I2CEN = 1; //Enable I2C
I2C_Start(); //Re-start
}
/* Stop Done */
else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == STOP_DONE)
{
Busy = 0;
SN_I2C0->STAT_b.I2CIF = 1;
if(EEPROM_WR == 1)
Read_Down = 1;
}
else
{
SN_I2C0->STAT_b.I2CIF = 1;
switch (SN_I2C0->STAT)
{
case (Lost_Arbitration | mskI2C_MST_MASTER):
I2C_Start();
break;
/* RX with ACK/NACK transfer is down */
case (RX_DONE | mskI2C_MST_MASTER):
bI2C_RxFIFO[bI2C_Rx_cnts++] = SN_I2C0->RXDATA;
if(bI2C_Rx_cnts < (bI2C_RxFIFO_cnts - 1))
SN_I2C0->CTRL_b.ACK = 1;
else if(bI2C_Rx_cnts == (bI2C_RxFIFO_cnts - 1))
SN_I2C0->CTRL_b.NACK = 1;
else if(bI2C_Rx_cnts == bI2C_RxFIFO_cnts)
I2C_Stop();
Busy = 0;
break;
/* SLA+W or Data has been transmitted and ACK has been received */
case (ACK_DONE | mskI2C_MST_MASTER):
if(EEPROM_WR == 1)
{
Busy = 0;
if(bI2C_RxFIFO_cnts == 1)
SN_I2C0->CTRL_b.NACK = 1;
else
SN_I2C0->CTRL_b.ACK = 1;
}
if(EEPROM_WR == 0)
{
if(Send_Address == 0)
{
bI2C_Tx_cnts++;
if(bI2C_Tx_cnts < bI2C_TxFIFO_cnts)
SN_I2C0->TXDATA = *bTX_ptr++;
else if(bI2C_Tx_cnts == bI2C_TxFIFO_cnts)
Busy = 0;
}
else
Busy = 0;
}
break;
/* SLA+W or Data has been transmitted and NACK has been received */
case (NACK_DONE | mskI2C_MST_MASTER):
SN_I2C0->CTRL_b.STO = 1;
Error = 1;
break;
/* START has been transmitted and prepare SLA+W/SLA+R */
case (START_DONE | mskI2C_MST_MASTER):
#if (EEPROM_less_than_32K == 1)
SN_I2C0->TXDATA = Device_ADDRESS | (EEPROM_ADR_H << 1) | EEPROM_WR;
#else
SN_I2C0->TXDATA = Device_ADDRESS | EEPROM_WR;
#endif
break;
default:
SN_I2C0->CTRL_b.I2CEN = 0;
SN_I2C0->CTRL_b.I2CEN = 1;
SN_I2C0->CTRL_b.STA = 1;
break;
}
}
}

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os/hal/ports/SN32/LLD/SN32F24xB/I2C/I2C.h
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#ifndef __SN32F240_I2C_H
#define __SN32F240_I2C_H
/*_____ I N C L U D E S ____________________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4001 8000 (I2C0)
0x4005 A000 (I2C1)
*/
/* I2C n Control register <I2Cn_CTRL> (0x00) */
//[1:1]Assert NACK (HIGH level to SDA) flag
#define I2C_NACK_NOFUNCTION 0 //No function
#define I2C_NACK 1 //An NACK will be returned during the acknowledge clock pulse on SCLn
#define mskI2C_NACK_NOFUNCTION (I2C_NACK_NOFUNCTION<<1)
#define mskI2C_NACK (I2C_NACK<<1)
//[2:2]Assert ACK (Low level to SDA) flag
#define I2C_ACK_NOFUNCTION 0 //No function
#define I2C_ACK 1 //An ACK will be returned during the acknowledge clock pulse on SCLn
#define mskI2C_ACK_NOFUNCTION (I2C_ACK_NOFUNCTION<<2)
#define mskI2C_ACK (I2C_ACK<<2)
//[4:4]STOP flag
#define I2C_STO_IDLE 0 //Stop condition idle
#define I2C_STO_STOP 1 //Transmit a STOP condition in master mode, or recover from an error condition in slave mode.
#define mskI2C_STO_IDLE (I2C_STO_IDLE<<4)
#define mskI2C_STO_STOP (I2C_STO_STOP<<4)
//[5:5]START bit
#define I2C_STA_IDLE 0 //No START condition or Repeated START condition will be generated
#define I2C_STA_START 1 //transmit a START or a Repeated START condition
#define mskI2C_STA_IDLE (I2C_STA_IDLE<<5)
#define mskI2C_STA_START (I2C_STA_START<<5)
#define I2C_I2CEN_DIS 0 //[8:8]I2C Interface enable bit
#define I2C_I2CEN_EN 1
#define mskI2C_I2CEN_DIS (I2C_I2CEN_DIS<<8)
#define mskI2C_I2CEN_EN (I2C_I2CEN_EN<<8)
/* I2C n Status register <I2Cn_STAT> (0x04) */
//[0:0]RX done status
#define I2C_RX_DN_NO_HANDSHAKE 0 //No RX with ACK/NACK transfer
#define I2C_RX_DN_HANDSHAKE 1 //8-bit RX with ACK/NACK transfer is done
#define mskI2C_RX_DN_NO_HANDSHAKE (I2C_RX_DN_NO_HANDSHAKE<<0)
#define mskI2C_RX_DN_HANDSHAKE (I2C_RX_DN_HANDSHAKE<<0)
//[1:1]ACK done status
#define I2C_ACK_STAT_NO_RECEIVED_ACK 0 //Not received an ACK
#define I2C_ACK_STAT_RECEIVED_ACK 1 //Received an ACK
#define mskI2C_ACK_STAT_NO_RECEIVED_ACK (I2C_ACK_STAT_NO_RECEIVED_ACK<<1)
#define mskI2C_ACK_STAT_RECEIVED_ACK (I2C_ACK_STAT_RECEIVED_ACK<<1)
//[2:2]NACK done status
#define I2C_NACK_STAT_NO_RECEIVED_NACK 0 //Not received a NACK
#define I2C_NACK_STAT_RECEIVED_NACK 1 //Received a NACK
#define mskI2C_NACK_STAT_NO_RECEIVED_NACK (I2C_NACK_STAT_NO_RECEIVED_NACK<<2)
#define mskI2C_NACK_STAT_RECEIVED_NACK (I2C_NACK_STAT_RECEIVED_NACK<<2)
//[3:3]Stop done status
#define I2C_STOP_DN_NO_STOP 0 //No STOP bit
#define I2C_STOP_DN_STOP 1 //MASTER mode, a STOP condition was issued
//SLAVE mode, a STOP condition was received
#define mskI2C_STOP_DN_NO_STOP (I2C_STOP_DN_NO_STOP<<3)
#define mskI2C_STOP_DN_STOP (I2C_STOP_DN_STOP<<3)
//[4:4]Start done status
#define I2C_START_DN_NO_START 0 //No START bit
#define I2C_START_DN_START 1 //MASTER mode, a START bit was issued
//SLAVE mode, a START bit was received
#define mskI2C_START_DN_NO_START (I2C_START_DN_NO_START<<4)
#define mskI2C_START_DN_START (I2C_START_DN_START<<4)
#define I2C_MST_SLAVE 0 //[5:5]Master/Slave status
#define I2C_MST_MASTER 1
#define mskI2C_MST_SLAVE (I2C_MST_SLAVE<<5)
#define mskI2C_MST_MASTER (I2C_MST_MASTER<<5)
#define mskI2C_STA_STA_STO ((I2C_START_DN_START<<4)|(I2C_STOP_DN_STOP<<3))
#define mskI2C_STA_MASTER_STA_STO ((I2C_MST_MASTER<<5)|(I2C_START_DN_START<<4)|(I2C_STOP_DN_STOP<<3))
//[6:6]Slave address check
#define I2C_SLV_RX_NO_MATCH_ADDR 0 //No matched slave address
#define I2C_SLV_RX_MATCH_ADDR 1 //Slave address hit, and is called for RX in slave mode
#define mskI2C_SLV_RX_NO_MATCH_ADDR (I2C_SLV_RX_NO_MATCH_ADDR<<6)
#define mskI2C_SLV_RX_MATCH_ADDR (I2C_SLV_RX_MATCH_ADDR<<6)
//[7:7]Slave address check
#define I2C_SLV_TX_NO_MATCH_ADDR 0 //No matched slave address
#define I2C_SLV_TX_MATCH_ADDR 1 //Slave address hit, and is called for TX in slave mode.
#define mskI2C_SLV_TX_NO_MATCH_ADDR (I2C_SLV_TX_NO_MATCH_ADDR<<7)
#define mskI2C_SLV_TX_MATCH_ADDR (I2C_SLV_TX_MATCH_ADDR<<7)
//[8:8]Lost arbitration
#define I2C_LOST_ARB_NO_LOST 0 //Not lost arbitration
#define I2C_LOST_ARB_LOST_ARBITRATION 1 //Lost arbitration
#define mskI2C_LOST_ARB_NO_LOST (I2C_LOST_ARB_NO_LOST<<8)
#define mskI2C_LOST_ARB_LOST_ARBITRATION (I2C_LOST_ARB_LOST_ARBITRATION<<8)
//[9:9]Time-out status
#define I2C_TIMEOUT_NO_TIMEOUT 0 //No Timeout
#define I2C_TIMEOUT_TIMEOUT 1 //Timeout
#define mskI2C_TIMEOUT_TIMEOUT (I2C_TIMEOUT_TIMEOUT<<9)
#define mskI2C_TIMEOUT_NO_TIMEOUT (I2C_TIMEOUT_NO_TIMEOUT<<9)
//[15:15]I2C Interrupt flag
#define I2C_I2CIF_STAUS_NO_CHANGE 0 //I2C status doesn’t change
#define I2C_I2CIF_INTERRUPT 1 //Read, I2C status changes
//Write, Clear this flag
#define mskI2C_I2CIF_STAUS_NO_CHANGE (I2C_I2CIF_STAUS_NO_CHANGE<<15)
#define mskI2C_I2CIF_INTERRUPT (I2C_I2CIF_INTERRUPT<<15)
/* I2C n TX Data register <I2Cn_TXDATA> (0x08) */
/* I2C n RX Data register <I2Cn_RXDATA> (0x0C) */
/* I2C n Slave Address 0 register <I2Cn_SLVADDR0> (0x10) */
//[9:0]The I2C slave address
#define I2C_ADDR_SLAVE_ADDR0 0x07 //ADD[9:0] is valid when ADD_MODE = 1
//ADD[7:1] is valid when ADD_MODE = 0
//[30:30]General call address enable bit
#define I2C_GCEN_DIS 0 //Disable
#define I2C_GCEN_EN 1 //Enable general call address (0x0)
#define mskI2C_GCEN_DIS (I2C_GCEN_DIS<<30)
#define mskI2C_GCEN_EN (I2C_GCEN_EN<<30)
//[31:31]Slave address mode
#define I2C_ADD_MODE_7BIT 0 //7-bit address mode
#define I2C_ADD_MODE_10BIT 1 //10-bit address mode
#define mskI2C_ADD_MODE_7BIT (I2C_ADD_MODE_7BIT<<31)
#define mskI2C_ADD_MODE_10BIT (I2C_ADD_MODE_10BIT<<31)
/* I2C n Slave Address 1~3 register <I2Cn_SLVADDR1~3> (0x14/0x18/0x1C) */
//The I2C slave address 1~3
//ADD[9:0] is valid when ADD_MODE = 1
//ADD[7:1] is valid when ADD_MODE = 0
#define I2C_ADDR_SLAVE_ADDR1 0x0A //The I2C slave address 1
#define I2C_ADDR_SLAVE_ADDR2 0 //The I2C slave address 2
#define I2C_ADDR_SLAVE_ADDR3 0 //The I2C slave address 3
#define I2C_SLAVE0 0 //Slave Number 0
#define I2C_SLAVE1 1 //Slave Number 1
#define I2C_SLAVE2 2 //Slave Number 2
#define I2C_SLAVE3 3 //Slave Number 3
/* I2C n SCL High Time register <(I2Cn_SCLHT> (0x20) */
#define I2C0_SCLHT 14 //[7:0], Count for SCL High Period time
#define I2C1_SCLHT 4 //SCL High Period Time = (SCLH+1) * I2C0_PCLK cycle
/* I2C n SCL Low Time register <(I2Cn_SCLLT> (0x24) */
#define I2C0_SCLLT 14 //[7:0], Count for SCL Low Period time
#define I2C1_SCLLT 4 //SCL Loq Period Time = (SCLH+1) * I2C0_PCLK cycle
/* I2C n Timeout Control register <I2Cn_TOCTRL> (0x2C) */
#define I2C_TO_DIS 0 //[15:0], Count for checking Timeout
#define I2C_TO_PERIOD_TIME 0 //N: Timeout period time = N*I2Cn_PCLK cycle
/* I2C n Monitor Mode Control register <I2Cn_MMCTRL> (0x30) */
#define I2C_MMEN_MONITOR_DIS 0 //[0:0]Monitor mode enable bit
#define I2C_MMEN_MONITOR_EN 1
#define mskI2C_MMEN_MONITOR_DIS (I2C_MMEN_MONITOR_DIS<<0) //Monitor mode enable bit
#define mskI2C_MMEN_MONITOR_EN (I2C_MMEN_MONITOR_EN<<0)
//[1:1]SCL output enable bit
#define I2C_SCLOEN_DIS 0 //SCL output will be forced high
#define I2C_SCLOEN_EN 1 //I2C holds the clock line low until it has had time to respond to an I2C interrupt
#define mskI2C_SCLOEN_DIS (I2C_SCLOEN_DIS<<1) //SCL output enable bit
#define mskI2C_SCLOEN_EN (I2C_SCLOEN_EN<<1)
//[2:2]Match address selection
#define I2C_MATCH_ALL_ADDR0_3 0 //Interrupt will only be generated when the address matches
#define I2C_MATCH_ALL_ANY_ADDR 1 //In monitor mode, an interrupt will be generated on ANY address received
#define mskI2C_MATCH_ALL_ADDR0_3 (I2C_MATCH_ALL_ADDR0_3<<2)
#define mskI2C_MATCH_ALL_ANY_ADDR (I2C_MATCH_ALL_ANY_ADDR<<2)
#define I2C_ERROR 0x00001
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
//------------------I2C-------------------------
//Address
extern uint16_t hwI2C_Device_Addr_I2C0;
extern uint16_t hwI2C_Device_Addr_I2C1;
//Check Flag
extern uint32_t wI2C_TimeoutFlag;
extern uint32_t wI2C_ArbitrationFlag;
//Error Flag
extern uint32_t wI2C_RegisterCheckError;
extern uint32_t wI2C_TotalError;
//------------------Master Tx-------------------------
//TX FIFO
extern uint8_t bI2C_MasTxData[10];
//Control Flag
extern uint8_t bI2C_MasTxPointer;
extern uint32_t wI2C_MasTxCtr;
//------------------Master Rx-------------------------
//RX FIFO
extern uint8_t bI2C_MasRxData[10];
//Rx Control Flag
extern uint8_t bI2C_MasRxPointer;
extern uint32_t wI2C_ReturnNackFlag;
extern uint32_t wI2C_RxControlFlag;
//------------------Slave Rx-------------------------
//RX FIFO
extern uint8_t bI2C_SlaRxData[10];
//Rx Control Flag
extern uint8_t bI2C_SlaRxPointer;
//extern volatile uint8_t bEndSRxFlagI2C;
//------------------Slave Tx-------------------------
//TX FIFO
extern uint8_t bI2C_SlaTxData[10];
//Tx Control Flag
extern uint8_t bI2C_SlaTxPointer;
//extern volatile uint8_t bEndSTxFlagI2C;
void I2C0_Init(void);
void I2C1_Init(void);
void I2C0_Timeout_Ctrl(uint32_t wI2CTo);
void I2C1_Timeout_Ctrl(uint32_t wI2CTo);
void I2C0_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen);
void I2C1_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen);
void Set_I2C0_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable);
void Set_I2C1_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable);
extern void I2C0_Enable(void);
extern void I2C0_Disable(void);
extern void I2C1_Enable(void);
extern void I2C1_Disable(void);
void I2C0_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum);
void I2C0_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum);
void I2C1_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum);
void I2C1_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum);
void I2C1_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack);
void I2C1_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop);
void I2C1_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop);
void I2C0_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack);
void I2C0_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop);
void I2C0_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop);
#endif /*__SN32F240_I2C_H*/
#ifndef __SN32F240B_I2C_H
#define __SN32F240B_I2C_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define EEPROM_less_than_32K 1 // 1: for EEPROM size less than 32K bits (4096x8)
// 0: for EEPROM size more than or equal to 32K bits (4096x8)
#define Device_ADDRESS 0xA0
#define Lost_Arbitration 0x100
#define SLAVE_ADDRESS_HIT_TX 0x80
#define SLAVE_ADDRESS_HIT_RX 0x40
#define START_DONE 0x10
#define STOP_DONE 0x08
#define NACK_DONE 0x04
#define ACK_DONE 0x02
#define RX_DONE 0x01
/* I2C n SCL High Time register <(I2Cn_SCLHT> (0x20) */
#define I2C0_SCLHT 14 //[7:0], Count for SCL High Period time
//SCL High Period Time = (SCLH+1) * I2C0_PCLK cycle
#define I2C0_SCLLT 14 //[7:0], Count for SCL Low Period time
//SCL Loq Period Time = (SCLL+1) * I2C0_PCLK cycle
/* I2C n Status register <I2Cn_STAT> (0x04) */
//[0:0]RX done status
#define I2C_RX_DN_NO_HANDSHAKE 0 //No RX with ACK/NACK transfer
#define I2C_RX_DN_HANDSHAKE 1 //8-bit RX with ACK/NACK transfer is done
#define mskI2C_RX_DN_NO_HANDSHAKE (I2C_RX_DN_NO_HANDSHAKE<<0)
#define mskI2C_RX_DN_HANDSHAKE (I2C_RX_DN_HANDSHAKE<<0)
//[1:1]ACK done status
#define I2C_ACK_STAT_NO_RECEIVED_ACK 0 //Not received an ACK
#define I2C_ACK_STAT_RECEIVED_ACK 1 //Received an ACK
#define mskI2C_ACK_STAT_NO_RECEIVED_ACK (I2C_ACK_STAT_NO_RECEIVED_ACK<<1)
#define mskI2C_ACK_STAT_RECEIVED_ACK (I2C_ACK_STAT_RECEIVED_ACK<<1)
//[2:2]NACK done status
#define I2C_NACK_STAT_NO_RECEIVED_NACK 0 //Not received a NACK
#define I2C_NACK_STAT_RECEIVED_NACK 1 //Received a NACK
#define mskI2C_NACK_STAT_NO_RECEIVED_NACK (I2C_NACK_STAT_NO_RECEIVED_NACK<<2)
#define mskI2C_NACK_STAT_RECEIVED_NACK (I2C_NACK_STAT_RECEIVED_NACK<<2)
//[3:3]Stop done status
#define I2C_STOP_DN_NO_STOP 0 //No STOP bit
#define I2C_STOP_DN_STOP 1 //MASTER mode, a STOP condition was issued
//SLAVE mode, a STOP condition was received
#define mskI2C_STOP_DN_NO_STOP (I2C_STOP_DN_NO_STOP<<3)
#define mskI2C_STOP_DN_STOP (I2C_STOP_DN_STOP<<3)
//[4:4]Start done status
#define I2C_START_DN_NO_START 0 //No START bit
#define I2C_START_DN_START 1 //MASTER mode, a START bit was issued
//SLAVE mode, a START bit was received
#define mskI2C_START_DN_NO_START (I2C_START_DN_NO_START<<4)
#define mskI2C_START_DN_START (I2C_START_DN_START<<4)
#define I2C_MST_SLAVE 0 //[5:5]Master/Slave status
#define I2C_MST_MASTER 1
#define mskI2C_MST_SLAVE (I2C_MST_SLAVE<<5)
#define mskI2C_MST_MASTER (I2C_MST_MASTER<<5)
#define mskI2C_STA_STA_STO ((I2C_START_DN_START<<4)|(I2C_STOP_DN_STOP<<3))
#define mskI2C_STA_MASTER_STA_STO ((I2C_MST_MASTER<<5)|(I2C_START_DN_START<<4)|(I2C_STOP_DN_STOP<<3))
//[6:6]Slave address check
#define I2C_SLV_RX_NO_MATCH_ADDR 0 //No matched slave address
#define I2C_SLV_RX_MATCH_ADDR 1 //Slave address hit, and is called for RX in slave mode
#define mskI2C_SLV_RX_NO_MATCH_ADDR (I2C_SLV_RX_NO_MATCH_ADDR<<6)
#define mskI2C_SLV_RX_MATCH_ADDR (I2C_SLV_RX_MATCH_ADDR<<6)
//[7:7]Slave address check
#define I2C_SLV_TX_NO_MATCH_ADDR 0 //No matched slave address
#define I2C_SLV_TX_MATCH_ADDR 1 //Slave address hit, and is called for TX in slave mode.
#define mskI2C_SLV_TX_NO_MATCH_ADDR (I2C_SLV_TX_NO_MATCH_ADDR<<7)
#define mskI2C_SLV_TX_MATCH_ADDR (I2C_SLV_TX_MATCH_ADDR<<7)
//[8:8]Lost arbitration
#define I2C_LOST_ARB_NO_LOST 0 //Not lost arbitration
#define I2C_LOST_ARB_LOST_ARBITRATION 1 //Lost arbitration
#define mskI2C_LOST_ARB_NO_LOST (I2C_LOST_ARB_NO_LOST<<8)
#define mskI2C_LOST_ARB_LOST_ARBITRATION (I2C_LOST_ARB_LOST_ARBITRATION<<8)
//[9:9]Time-out status
#define I2C_TIMEOUT_NO_TIMEOUT 0 //No Timeout
#define I2C_TIMEOUT_TIMEOUT 1 //Timeout
#define mskI2C_TIMEOUT_TIMEOUT (I2C_TIMEOUT_TIMEOUT<<9)
#define mskI2C_TIMEOUT_NO_TIMEOUT (I2C_TIMEOUT_NO_TIMEOUT<<9)
//[15:15]I2C Interrupt flag
#define I2C_I2CIF_STAUS_NO_CHANGE 0 //I2C status doesn’t change
#define I2C_I2CIF_INTERRUPT 1 //Read, I2C status changes
//Write, Clear this flag
#define mskI2C_I2CIF_STAUS_NO_CHANGE (I2C_I2CIF_STAUS_NO_CHANGE<<15)
#define mskI2C_I2CIF_INTERRUPT (I2C_I2CIF_INTERRUPT<<15)
//Recv FIFO
#define I2C_RX_FIFO_LENGTH 32
//TX FIFO
#define I2C_TX_FIFO_LENGTH 32
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
void I2C_Init(void);
void I2C_Start(void);
void I2C_Stop(void);
uint8_t I2C_Read(uint16_t eeprom_adr, uint8_t read_num);
uint8_t I2C_Write(uint16_t eeprom_adr, uint8_t write_num);
#endif

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os/hal/ports/SN32/LLD/SN32F24xB/I2C/I2C0.c
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@ -1,720 +0,0 @@
/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: I2C0 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include "I2C.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
//------------------I2C-------------------------
//Address
uint16_t hwI2C_Device_Addr_I2C0 = 0x00;
uint16_t hwI2C_Device_Addr_I2C1 = 0x00;
//Check Flag
uint32_t wI2C_TimeoutFlag = 0;
uint32_t wI2C_ArbitrationFlag = 0;
//Error Flag
uint32_t wI2C_RegisterCheckError = 0;
uint32_t wI2C_TotalError = 0;
//------------------Master Tx-------------------------
//TX FIFO
uint8_t bI2C_MasTxData[10];
//Tx Control Flag
uint8_t bI2C_MasTxPointer=0;
uint32_t wI2C_MasTxCtr=0;
//------------------Master Rx-------------------------
//RX FIFO
uint8_t bI2C_MasRxData[10];
//Rx Control Flag
uint8_t bI2C_MasRxPointer=0;
uint32_t wI2C_ReturnNackFlag=0;
uint32_t wI2C_RxControlFlag=0;
//------------------Slave Rx-------------------------
//RX FIFO
uint8_t bI2C_SlaRxData[10];
//Rx Control Flag
uint8_t bI2C_SlaRxPointer=0;
//------------------Slave Tx-------------------------
//TX FIFO
uint8_t bI2C_SlaTxData[10];
//Tx Control Flag
uint8_t bI2C_SlaTxPointer=0;
//Mointer Mode
uint8_t bI2C0_MointerAddress = 0x00;
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : I2C0_Init
* Description : Set specified value to specified bits of assigned register
* Input : wI2C0SCLH - SCL High Time
* wI2C0SCLL - SCL Low Time
* wI2C0Mode - 0: Standard/Fast mode.1: Fast-mode Plus
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Init(void)
{
//I2C0 interrupt enable
NVIC_ClearPendingIRQ(I2C0_IRQn);
NVIC_EnableIRQ(I2C0_IRQn);
NVIC_SetPriority(I2C0_IRQn,0);
//Enable HCLK for I2C0
SN_SYS1->AHBCLKEN |= (0x1 << 21); //Enable clock for I2C0
//I2C speed
SN_I2C0->SCLHT = I2C0_SCLHT;
SN_I2C0->SCLLT = I2C0_SCLLT;
//Mointer mode
//SN_I2C0->MMCTRL = 0x00;
SN_I2C0->MMCTRL = mskI2C_MATCH_ALL_ADDR0_3|
mskI2C_SCLOEN_DIS|
mskI2C_MMEN_MONITOR_DIS;
//I2C enable
SN_I2C0->CTRL_b.I2CEN = I2C_I2CEN_EN;
}
/*****************************************************************************
* Function : I2C0_Timeout_Ctrl
* Description : Set specified value to specified bits of assigned register
* Input : wI2CTo - TimeOut Value: wI2CTo * 32 * I2C_PCLK cycle
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Timeout_Ctrl(uint32_t wI2CTo)
{
SN_I2C0->TOCTRL = wI2CTo;
}
/*****************************************************************************
* Function : I2C0_Monitor_Mode_Ctrl
* Description : Set specified value to specified bits of assigned register
* Input : wI2CmatchAll - 0: No use. 1: Interrupt will be generated on ANY address received.
* wI2Cscloen - 0: No use. 1: Let I2C holds the clock line low to get data.
* wI2Cmmen - 0: No use. 1: Monitor mode enable bit.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen)
{
SN_I2C0->TOCTRL = (wI2CmatchAll << 2) | (wI2Cscloen << 1) | (wI2Cmmen << 0);
}
/*****************************************************************************
* Function : Set_I2C0_Address
* Description : Set specified value to specified bits of assigned register
* Input : bI2CaddMode - 7 bits address is 0, 10 bits address is 1
* bSlaveNo - Slave address number 0, 1, 2, 3
* bSlaveAddr - Slave value
* bGCEnable - Genral call enable is 1
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void Set_I2C0_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable)
{
volatile uint16_t hwAddressCom=0;
if(bI2CaddMode == 0)
{
hwAddressCom = bSlaveAddr << 1;
}
else
{
hwAddressCom = bSlaveAddr;
}
if(bGCEnable == 1)
{
SN_I2C0->SLVADDR0_b.GCEN = I2C_GCEN_EN;
}
else
{
SN_I2C0->SLVADDR0_b.GCEN = I2C_GCEN_DIS;
}
if(bI2CaddMode == 1)
{
SN_I2C0->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_10BIT;
}
else
{
SN_I2C0->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_7BIT;
}
switch (bSlaveNo)
{
case 0:
SN_I2C0->SLVADDR0 = hwAddressCom;
break;
case 1:
SN_I2C0->SLVADDR1 = hwAddressCom;
break;
case 2:
SN_I2C0->SLVADDR2 = hwAddressCom;
break;
case 3:
SN_I2C0->SLVADDR3 = hwAddressCom;
break;
default:
break;
}
}
/*****************************************************************************
* Function : I2C0_Enable
* Description : I2C0 enable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Enable(void)
{
//Enable HCLK for I2C0
SN_SYS1->AHBCLKEN |= (0x1 << 21); //Enable clock for I2C0
SN_I2C0->CTRL_b.I2CEN = I2C_I2CEN_EN; //I2C enable
}
/*****************************************************************************
* Function : I2C0_Disable
* Description : I2C0 disable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Disable(void)
{
SN_I2C0->CTRL_b.I2CEN = I2C_I2CEN_DIS; //I2C disable
//Disable HCLK for I2C0
SN_SYS1->AHBCLKEN &=~ (0x1 << 21); //Disable clock for I2C0
}
/*****************************************************************************
* Function : I2C0_Master_Tx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare TX FIFO Register
* *bPointerFIFO - Declare TX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* bSlaveAddress - Set the Slave adress
* wTxNum - Set the Number of sending Data
* wRepeatTX - 0 : No use. 1: Next transfer with a Repated Start condition. 2: Work next transfer.
* wReTxNum - Send (wReTxNum + 1) Data when wRepeatTX is 1.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum)
{
//wReTxNum = 0, Repeat once; wReTxNum = 1, Repeat twice
//if(((I2C_STAT) & (mskI2C_TIMEOUT_TIMEOUT)) != 0x00) //Timeout State
if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bPointerFIFO = 0x00;
wI2C_MasTxCtr = 0x00;
*bCommStop = 1;
}
else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
SN_I2C0->TXDATA = (bSlaveAddress << 0x01);
}
else
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C0->STAT)
{
/* START has been transmitted and prepare SLA+W */
case (mskI2C_MST_MASTER|mskI2C_START_DN_START):
SN_I2C0->TXDATA = (bSlaveAddress << 0x01);
break;
/* SLA+W or Data has been transmitted and ACK has been received */
case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK):
if ((*bPointerFIFO < wTxNum)&&(wI2C_MasTxCtr == 0x00))
{
SN_I2C0->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
}
else if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00))
{
if(wRepeatTX == 0) //No Repeat
{
SN_I2C0->CTRL |= mskI2C_STO_STOP;
}
else if(wRepeatTX == 1) //Repeat Start
{
SN_I2C0->CTRL |= mskI2C_STA_START;
wI2C_MasTxCtr++;
}
else if(wRepeatTX == 2) //Repeat Both
{
SN_I2C0->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START);
wI2C_MasTxCtr++;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
}
else if ((*bPointerFIFO < (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01))
{
SN_I2C0->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
}
else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01))
{
SN_I2C0->CTRL |= mskI2C_STO_STOP;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
break;
/* SLA+W or Data has been transmitted and NACK has been received */
case (mskI2C_MST_MASTER|mskI2C_NACK_STAT_RECEIVED_NACK):
if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00))
{
if(wRepeatTX == 0) //No Repeat
{
SN_I2C0->CTRL |= mskI2C_STO_STOP;
}
else if(wRepeatTX == 1) //Repeat Start
{
SN_I2C0->CTRL |= mskI2C_STA_START;
wI2C_MasTxCtr++;
}
else if(wRepeatTX == 2) //Repeat Both
{
SN_I2C0->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START);
wI2C_MasTxCtr++;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
}
else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01))
{
SN_I2C0->CTRL |= mskI2C_STO_STOP;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C0_Master_Rx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare RX FIFO Register
* *bPointerFIFO - Declare RX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* bSlaveAddress - Set the Slave adress
* wRxNum - Set the Number of getting Data
* wRepeatRX - 0 : No use. 1: Next transfer with a Repated Start condition 2: Work next transfer.
* wReRxNum - Get (wReRxNum + 1) data when wRepeatRX is 1.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum)
{
uint32_t wDeboundNum = 0;
//if(((I2C_STAT) & (mskI2C_TIMEOUT_TIMEOUT)) != 0x00) //Timeout State
if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if(((SN_I2C0->STAT) & (mskI2C_STA_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bPointerFIFO = 0x00;
wI2C_MasTxCtr = 0x00;
*bCommStop = 1;
wI2C_RxControlFlag = 0x00;
wI2C_ReturnNackFlag = 0x00;
}
else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
SN_I2C0->TXDATA = (bSlaveAddress << 0x01) | 0x01;
}
else
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C0->STAT)
{
/* START has been transmitted and prepare to send address */
case (mskI2C_MST_MASTER|mskI2C_START_DN_START):
SN_I2C0->TXDATA = (bSlaveAddress << 0x01) | 0x01;
break;
/* Received an ACK */
case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK):
if((wRxNum == 1) && (wI2C_ReturnNackFlag == 0))
{
SN_I2C0->CTRL |= mskI2C_NACK; //NACK
wI2C_ReturnNackFlag++;
}
else if((wReRxNum == 0) && (wI2C_ReturnNackFlag == 1))
{
SN_I2C0->CTRL |= mskI2C_NACK; //NACK
wI2C_ReturnNackFlag++;
}
else
{
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
}
break;
/* RX with ACK/NACK transfer is down */
case (mskI2C_MST_MASTER|mskI2C_RX_DN_HANDSHAKE):
*bDataFIFO = SN_I2C0->RXDATA;
*bPointerFIFO = *bPointerFIFO + 1;
if(wI2C_ReturnNackFlag == 0x00)
{
wDeboundNum = wRxNum-1;
}
else if(wI2C_ReturnNackFlag == 0x01)
{
wDeboundNum = wRxNum+wReRxNum;
}
if(wI2C_ReturnNackFlag == 0x02)
{
SN_I2C0->CTRL |= mskI2C_STO_STOP;
}
else if((wI2C_ReturnNackFlag == 0x01) && (wI2C_RxControlFlag == 0x00))
{
if(wRepeatRX == 0) //No Repeat
{
SN_I2C0->CTRL |= mskI2C_STO_STOP;
}
else if(wRepeatRX == 1) //Repeat Start
{
SN_I2C0->CTRL |= mskI2C_STA_START;
}
else if(wRepeatRX == 2) //Repeat Both
{
SN_I2C0->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START);
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
wI2C_RxControlFlag = 1;
}
else if((*bPointerFIFO < (wDeboundNum)))
{
//Return ACK
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
}
else if((*bPointerFIFO >= (wDeboundNum)))
{
//Return NACK
SN_I2C0->CTRL |= mskI2C_NACK; //NACK
wI2C_ReturnNackFlag++;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C0_Slave_Rx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare RX FIFO Register
* *bPointerFIFO - Declare RX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* wNumForNack - Return NACK when getting the number of data is wNumForNack.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack)
{
if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if( SN_I2C0->STAT & mskI2C_STOP_DN_STOP) //Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bCommStop = 0x01;
}
else
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C0->STAT)
{
/* Slave addess hit for Rx */
case mskI2C_SLV_RX_MATCH_ADDR:
if(wNumForNack == 0)
{
SN_I2C0->CTRL |= mskI2C_ACK;; //ACK
}
else if(wNumForNack == 1)
{
SN_I2C0->CTRL |= mskI2C_NACK; //NACK
}
else
{
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
}
break;
/* DATA has been received and ACK/NACK has been returned */
case mskI2C_RX_DN_HANDSHAKE:
*bDataFIFO = SN_I2C0->RXDATA ;
*bPointerFIFO = *bPointerFIFO + 1;
if(wNumForNack == 0)
{
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
}
else if(*bPointerFIFO == (wNumForNack-1))
{
SN_I2C0->CTRL |= mskI2C_NACK; //NACK
}
else
{
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
}
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C0_Slave_Tx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare TX FIFO Register
* *bPointerFIFO - Declare TX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop)
{
if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if( SN_I2C0->STAT & mskI2C_STOP_DN_STOP) //Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bCommStop = 0x01;
}
else
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C0->STAT)
{
/* Slave addess hit for Tx */
case mskI2C_SLV_TX_MATCH_ADDR:
SN_I2C0->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
break;
/* Received ACK */
case mskI2C_ACK_STAT_RECEIVED_ACK:
SN_I2C0->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
break;
/* Received NACK */
case mskI2C_NACK_STAT_RECEIVED_NACK:
SN_I2C0->CTRL |= mskI2C_ACK; //For release SCL and SDA
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C0_Mointer_Mode
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare RX FIFO Register
* *bPointerFIFO - Declare RX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop)
{
if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if( SN_I2C0->STAT & mskI2C_STOP_DN_STOP) //Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bCommStop = 0x01;
}
else
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C0->STAT)
{
/* Slave addess hit for Rx */
case mskI2C_SLV_RX_MATCH_ADDR:
bI2C0_MointerAddress = SN_I2C0->RXDATA;
bI2C0_MointerAddress = bI2C0_MointerAddress >> 1;
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
break;
/* Slave addess hit for Tx */
case mskI2C_SLV_TX_MATCH_ADDR:
bI2C0_MointerAddress = SN_I2C0->RXDATA;
bI2C0_MointerAddress = bI2C0_MointerAddress >> 1;
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
break;
/* DATA has been received*/
case I2C_RX_DN_HANDSHAKE:
*bDataFIFO = SN_I2C0->RXDATA;
*bPointerFIFO = *bPointerFIFO + 1;
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}

675
os/hal/ports/SN32/LLD/SN32F24xB/I2C/I2C1.c
View File

@ -1,675 +0,0 @@
/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: I2C1 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include "I2C.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
//Mointer Mode
uint8_t bI2C1_MointerAddress = 0x00;
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : I2C1_Init
* Description : Set specified value to specified bits of assigned register
* Input : wI2C1SCLH - SCL High Time
* wI2C1SCLL - SCL Low Time
* wI2C1Mode - 0: Standard/Fast mode.1: Fast-mode Plus
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Init(void)
{
//I2C1 interrupt enable
NVIC_ClearPendingIRQ(I2C1_IRQn);
NVIC_EnableIRQ(I2C1_IRQn);
NVIC_SetPriority(I2C1_IRQn,0);
//Enable HCLK for I2C1
SN_SYS1->AHBCLKEN |= (0x1 << 20); //Enable clock for I2C1
//I2C speed
SN_I2C1->SCLHT = I2C1_SCLHT;
SN_I2C1->SCLLT = I2C1_SCLLT;
//I2C enable
SN_I2C1->CTRL_b.I2CEN = I2C_I2CEN_EN;
//I2C1 address set
Set_I2C1_Address(I2C_ADD_MODE_7BIT, I2C_SLAVE0, I2C_ADDR_SLAVE_ADDR0, I2C_GCEN_DIS);
Set_I2C1_Address(I2C_ADD_MODE_7BIT, I2C_SLAVE1, I2C_ADDR_SLAVE_ADDR1, I2C_GCEN_DIS);
}
/*****************************************************************************
* Function : I2C1_Timeout_Ctrl
* Description : Set specified value to specified bits of assigned register
* Input : wI2CTo - TimeOut Value: wI2CTo * 32 * I2C_PCLK cycle
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C01_Timeout_Ctrl(uint32_t wI2CTo)
{
SN_I2C1->TOCTRL = wI2CTo;
}
/*****************************************************************************
* Function : I2C1_Monitor_Mode_Ctrl
* Description : Set specified value to specified bits of assigned register
* Input : wI2CmatchAll - 0: No use. 1: Interrupt will be generated on ANY address received.
* wI2Cscloen - 0: No use. 1: Let I2C holds the clock line low to get data.
* wI2Cmmen - 0: No use. 1: Monitor mode enable bit.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen)
{
SN_I2C1->TOCTRL = (wI2CmatchAll << 2) | (wI2Cscloen << 1) | (wI2Cmmen << 0);
}
/*****************************************************************************
* Function : Set_I2C1_Address
* Description : Set specified value to specified bits of assigned register
* Input : bI2CaddMode - 7 bits address is 0, 10 bits address is 1
* bSlaveNo - Slave address number 0, 1, 2, 3
* bSlaveAddr - Slave value
* bGCEnable - Genral call enable is 1
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void Set_I2C1_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable)
{
volatile uint16_t hwAddressCom=0;
if(bI2CaddMode == 0)
{
hwAddressCom = bSlaveAddr << 1;
}
else
{
hwAddressCom = bSlaveAddr;
}
if(bGCEnable == 1)
{
SN_I2C1->SLVADDR0_b.GCEN = I2C_GCEN_EN;
}
else
{
SN_I2C1->SLVADDR0_b.GCEN = I2C_GCEN_DIS;
}
if(bI2CaddMode == 1)
{
SN_I2C1->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_10BIT;
}
else
{
SN_I2C1->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_7BIT;
}
switch (bSlaveNo)
{
case 0:
SN_I2C1->SLVADDR0 = hwAddressCom;
break;
case 1:
SN_I2C1->SLVADDR1 = hwAddressCom;
break;
case 2:
SN_I2C1->SLVADDR2 = hwAddressCom;
break;
case 3:
SN_I2C1->SLVADDR3 = hwAddressCom;
break;
default:
break;
}
}
/*****************************************************************************
* Function : I2C1_Enable
* Description : I2C1 enable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Enable(void)
{
//Enable HCLK for I2C1
SN_SYS1->AHBCLKEN |= (0x1 << 20); //Enable clock for I2C1
SN_I2C1->CTRL_b.I2CEN = I2C_I2CEN_EN; //I2C1 enable
}
/*****************************************************************************
* Function : I2C1_Disable
* Description : I2C1 disable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Disable(void)
{
SN_I2C1->CTRL_b.I2CEN = I2C_I2CEN_DIS; //I2C1 disable
//Disable HCLK for I2C1
SN_SYS1->AHBCLKEN &=~ (0x1 << 20); //Disable clock for I2C1
}
/*****************************************************************************
* Function : I2C1_Master_Tx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare TX FIFO Register
* *bPointerFIFO - Declare TX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* bSlaveAddress - Set the Slave adress
* wTxNum - Set the Number of sending Data
* wRepeatTX - 0 : No use. 1: Next transfer with a Repated Start condition. 2: Work next transfer.
* wReTxNum - Send (wReTxNum + 1) Data when wRepeatTX is 1.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum)
{
//wReTxNum = 0, Repeat once; wReTxNum = 1, Repeat twice
if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if(((SN_I2C1->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bPointerFIFO = 0x00;
wI2C_MasTxCtr = 0x00;
*bCommStop = 1;
}
else if(((SN_I2C1->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
SN_I2C1->TXDATA = (bSlaveAddress << 0x01);
}
else
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C1->STAT)
{
/* START has been transmitted and prepare SLA+W */
case (mskI2C_MST_MASTER|mskI2C_START_DN_START):
SN_I2C1->TXDATA = (bSlaveAddress << 0x01);
break;
/* SLA+W or Data has been transmitted and ACK has been received */
case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK):
if ((*bPointerFIFO < wTxNum)&&(wI2C_MasTxCtr == 0x00))
{
SN_I2C1->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
}
else if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00))
{
if(wRepeatTX == 0) //No Repeat
{
SN_I2C1->CTRL |= mskI2C_STO_STOP;
}
else if(wRepeatTX == 1) //Repeat Start
{
SN_I2C1->CTRL |= mskI2C_STA_START;
wI2C_MasTxCtr++;
}
else if(wRepeatTX == 2) //Repeat Both
{
SN_I2C1->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START);
wI2C_MasTxCtr++;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
}
else if ((*bPointerFIFO < (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01))
{
SN_I2C1->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
}
else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01))
{
SN_I2C1->CTRL |= mskI2C_STO_STOP;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
break;
/* SLA+W or Data has been transmitted and NACK has been received */
case (mskI2C_MST_MASTER|mskI2C_NACK_STAT_RECEIVED_NACK):
if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00))
{
if(wRepeatTX == 0) //No Repeat
{
SN_I2C1->CTRL |= mskI2C_STO_STOP;
}
else if(wRepeatTX == 1) //Repeat Start
{
SN_I2C1->CTRL |= mskI2C_STA_START;
wI2C_MasTxCtr++;
}
else if(wRepeatTX == 2) //Repeat Both
{
SN_I2C1->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START);
wI2C_MasTxCtr++;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
}
else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01))
{
SN_I2C1->CTRL |= mskI2C_STO_STOP;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C1_Master_Rx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare RX FIFO Register
* *bPointerFIFO - Declare RX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* bSlaveAddress - Set the Slave adress
* wRxNum - Set the Number of getting Data
* wRepeatRX - 0 : No use. 1: Next transfer with a Repated Start condition 2: Work next transfer.
* wReRxNum - Get (wReRxNum + 1) data when wRepeatRX is 1.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum)
{
uint32_t wDeboundNum = 0;
if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if(((SN_I2C1->STAT) & (mskI2C_STA_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bPointerFIFO = 0x00;
wI2C_MasTxCtr = 0x00;
*bCommStop = 1;
wI2C_RxControlFlag = 0x00;
wI2C_ReturnNackFlag = 0x00;
}
else if(((SN_I2C1->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
SN_I2C1->TXDATA = (bSlaveAddress << 0x01) | 0x01;
}
else
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C1->STAT)
{
/* START has been transmitted and prepare to send address */
case (mskI2C_MST_MASTER|mskI2C_START_DN_START):
SN_I2C1->TXDATA = (bSlaveAddress << 0x01) | 0x01;
break;
/* Received an ACK */
case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK):
if((wRxNum == 1) && (wI2C_ReturnNackFlag == 0))
{
SN_I2C1->CTRL |= mskI2C_NACK; //NACK
wI2C_ReturnNackFlag++;
}
else if((wReRxNum == 0) && (wI2C_ReturnNackFlag == 1))
{
SN_I2C1->CTRL |= mskI2C_NACK; //NACK
wI2C_ReturnNackFlag++;
}
else
{
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
}
break;
/* RX with ACK/NACK transfer is down */
case (mskI2C_MST_MASTER|mskI2C_RX_DN_HANDSHAKE):
*bDataFIFO = SN_I2C1->RXDATA;
*bPointerFIFO = *bPointerFIFO + 1;
if(wI2C_ReturnNackFlag == 0x00)
{
wDeboundNum = wRxNum-1;
}
else if(wI2C_ReturnNackFlag == 0x01)
{
wDeboundNum = wRxNum+wReRxNum;
}
if(wI2C_ReturnNackFlag == 0x02)
{
SN_I2C1->CTRL |= mskI2C_STO_STOP;
}
else if((wI2C_ReturnNackFlag == 0x01) && (wI2C_RxControlFlag == 0x00))
{
if(wRepeatRX == 0) //No Repeat
{
SN_I2C1->CTRL |= mskI2C_STO_STOP;
}
else if(wRepeatRX == 1) //Repeat Start
{
SN_I2C1->CTRL |= mskI2C_STA_START;
}
else if(wRepeatRX == 2) //Repeat Both
{
SN_I2C1->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START);
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
wI2C_RxControlFlag = 1;
}
else if((*bPointerFIFO < (wDeboundNum)))
{
//Return ACK
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
}
else if((*bPointerFIFO >= (wDeboundNum)))
{
//Return NACK
SN_I2C1->CTRL |= mskI2C_NACK; //NACK
wI2C_ReturnNackFlag++;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C1_Slave_Rx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare RX FIFO Register
* *bPointerFIFO - Declare RX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* wNumForNack - Return NACK when getting the number of data is wNumForNack.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack)
{
if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if( SN_I2C1->STAT & mskI2C_STOP_DN_STOP) //Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bCommStop = 0x01;
}
else
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C1->STAT)
{
/* Slave addess hit for Rx */
case mskI2C_SLV_RX_MATCH_ADDR:
if(wNumForNack == 0)
{
SN_I2C1->CTRL |= mskI2C_ACK;; //ACK
}
else if(wNumForNack == 1)
{
SN_I2C1->CTRL |= mskI2C_NACK; //NACK
}
else
{
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
}
break;
/* DATA has been received and ACK/NACK has been returned */
case mskI2C_RX_DN_HANDSHAKE:
*bDataFIFO = SN_I2C1->RXDATA ;
*bPointerFIFO = *bPointerFIFO + 1;
if(wNumForNack == 0)
{
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
}
else if(*bPointerFIFO == (wNumForNack-1))
{
SN_I2C1->CTRL |= mskI2C_NACK; //NACK
}
else
{
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
}
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C1_Slave_Tx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare TX FIFO Register
* *bPointerFIFO - Declare TX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop)
{
if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if( SN_I2C1->STAT & mskI2C_STOP_DN_STOP) //Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bCommStop = 0x01;
}
else
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C1->STAT)
{
/* Slave addess hit for Tx */
case mskI2C_SLV_TX_MATCH_ADDR:
SN_I2C1->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
break;
/* Received ACK */
case mskI2C_ACK_STAT_RECEIVED_ACK:
SN_I2C1->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
break;
/* Received NACK */
case mskI2C_NACK_STAT_RECEIVED_NACK:
SN_I2C1->CTRL |= mskI2C_ACK; //For release SCL and SDA
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C1_Mointer_Mode
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare RX FIFO Register
* *bPointerFIFO - Declare RX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop)
{
if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if( SN_I2C1->STAT & mskI2C_STOP_DN_STOP) //Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bCommStop = 0x01;
}
else
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C1->STAT)
{
/* Slave addess hit for Rx */
case mskI2C_SLV_RX_MATCH_ADDR:
bI2C1_MointerAddress = SN_I2C1->RXDATA;
bI2C1_MointerAddress = bI2C1_MointerAddress >> 1;
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
break;
/* Slave addess hit for Tx */
case mskI2C_SLV_TX_MATCH_ADDR:
bI2C1_MointerAddress = SN_I2C1->RXDATA;
bI2C1_MointerAddress = bI2C1_MointerAddress >> 1;
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
break;
/* DATA has been received*/
case I2C_RX_DN_HANDSHAKE:
*bDataFIFO = SN_I2C1->RXDATA;
*bPointerFIFO = *bPointerFIFO + 1;
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}

181
os/hal/ports/SN32/LLD/SN32F24xB/LCD/LCD.c
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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: LCD related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include "LCD.h"
#include "..\..\System\SYS_con_drive.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
#if LCD_TYPE == LCD_R_TYPE
/***********************************************************************************
* Function : LCD_RtypeInit
* Description : Initialization of R-type LCD driver
* Input : None
* Output : None
* Return : None
* Note : User shall follow the notice in 16.6 R-TYPE LCD APPLICATION CIRCUIT
* to take care of the circuit.
***********************************************************************************/
void LCD_RtypeInit(void)
{
__LCD_ENABLE_LCDHCLK; //Enable HCLK for LCD
//<-------------------- TODO: User modify on demand BEGIN -------------------->
//Setup LCD Driving ability, Clock rate, Duty, Bias, Type
SN_LCD->CTRL = (mskLCD_DRIVEP_LOW|mskLCD_RATE_DIV64|mskLCD_ONE_FOURTH_DUTY|mskLCD_ONE_THIRD_BIAS|mskLCD_R_TYPE);
LCD_SelectClockSource(LCD_CLOCK_ILRC); //Setup LCD Clock source
//Setup ITB bit, R-type resistance
SN_LCD->CTRL1 = (0|mskLCD_REF_400K); //Only value 0 is allowed for ITB bit
__LCD_SEGMENT_GROUP1_ENABLE; //Enable SEG12~23 (P0.10~P0.15, P1.0~P1.5) as LCD pins
__LCD_SEGMENT_GROUP2_ENABLE; //Enable SEG24~31 (P0.0~P0.7) as LCD pins
//<-------------------- TODO: User modify on demand END -------------------->
__LCD_ENABLE; //Enable LCD
}
#endif
#if LCD_TYPE == LCD_1C_TYPE
/***********************************************************************************
* Function : LCD_1CtypeInit
* Description : Initialization of 1C-type LCD driver
* Input : None
* Output : None
* Return : None
* Note : User shall follow the notice in 16.7 C-TYPE LCD APPLICATION CIRCUIT
* to take care of the circuit.
***********************************************************************************/
void LCD_1CtypeInit(void)
{
__LCD_ENABLE_LCDHCLK; //Enable HCLK for LCD
//<-------------------- TODO: User modify on demand BEGIN -------------------->
//Setup LCD Driving ability, Clock rate, Duty, Bias, Type
SN_LCD->CTRL = (mskLCD_DRIVEP_LOW|mskLCD_RATE_DIV64|mskLCD_ONE_FOURTH_DUTY|
mskLCD_ONE_THIRD_BIAS|mskLCD_1C_TYPE);
LCD_SelectClockSource(LCD_CLOCK_ILRC); //Setup LCD Clock source
//Setup IT1 bits, IT2 bits, VCP
SN_LCD->CCTRL1 = (0x44020000|mskLCD_1C_VCP_3P3V);
__LCD_SEGMENT_GROUP1_ENABLE; //Enable SEG12~23 (P0.10~P0.15, P1.0~P1.5) as LCD pins
__LCD_SEGMENT_GROUP2_ENABLE; //Enable SEG24~31 (P0.0~P0.7) as LCD pins
//<-------------------- TODO: User modify on demand END -------------------->
SN_LCD->CCTRL2 = 4; //Only value 0x4 is allowed
__LCD_ENABLE; //Enable LCD
}
#endif
#if LCD_TYPE == LCD_4C_TYPE
/***********************************************************************************
* Function : LCD_4CtypeInit
* Description : Initialization of 4C-type LCD driver
* Input : None
* Output : None
* Return : None
* Note : User shall follow the notice in 16.7 C-TYPE LCD APPLICATION CIRCUIT
* to take care of the circuit.
***********************************************************************************/
void LCD_4CtypeInit(void)
{
__LCD_ENABLE_LCDHCLK; //Enable HCLK for LCD
//<-------------------- TODO: User modify on demand BEGIN -------------------->
//Setup LCD Driving ability, Clock rate, Duty, Bias, Type
SN_LCD->CTRL = (mskLCD_DRIVEP_LOW|mskLCD_RATE_DIV64|mskLCD_ONE_FOURTH_DUTY|
mskLCD_ONE_THIRD_BIAS|mskLCD_4C_TYPE);
LCD_SelectClockSource(LCD_CLOCK_ILRC); //Setup LCD Clock source
//Setup IT1 bits, IT2 bits, VCP
SN_LCD->CCTRL1 = (0x44020000|mskLCD_4C_VCP_3P0V);
__LCD_SEGMENT_GROUP1_ENABLE; //Enable SEG12~23 (P0.10~P0.15, P1.0~P1.5) as LCD pins
__LCD_SEGMENT_GROUP2_ENABLE; //Enable SEG24~31 (P0.0~P0.7) as LCD pins
//<-------------------- TODO: User modify on demand END -------------------->
SN_LCD->CCTRL2 = 4; //Only value 0x4 is allowed
__LCD_ENABLE; //Enable LCD
}
#endif
/***********************************************************************************
* Function : LCD_SelectClockSource
* Description : Select LCD clcok source
* Input : LCD clock source - LCD_CLOCK_ILRC or LCD_CLOCK_ELS
* Output : None
* Return : None
* Note : None
***********************************************************************************/
void LCD_SelectClockSource(uint32_t src)
{
if (src == LCD_CLOCK_ELS)
SYS0_EnableELSXtal();
SN_LCD->CTRL_b.LCDCLK = src;
}
/***********************************************************************************
* Function : LCD_FrameInterruptEnable
* Description : LCD Frame interrupt enable function
* Input : CEN - Enable/Disable counter (ENABLE or DISABLE)
* FCT - Frame counter threshold value
* IE - LCD interrupt Enable/Disable (ENABLE or DISABLE)
* Output : None
* Return : None
* Note : 0 < FCT < 32
***********************************************************************************/
void LCD_SetFrameCounterInterrupt(uint32_t CEN, uint32_t FCT, uint32_t IE)
{
if (IE == ENABLE)
{
NVIC_ClearPendingIRQ(LCD_IRQn);
NVIC_EnableIRQ(LCD_IRQn);
}
SN_LCD->FCC = (CEN | (FCT<<1) | (IE<<7));
}
/*****************************************************************************
* Function : LCD_IRQHandler
* Description : ISR of LCD frame interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void LCD_IRQHandler(void)
{
SN_LCD->RIS = 0; //Write 0 to clear LCD interurpt flag
}

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#ifndef __SN32F240_LCD_H
#define __SN32F240_LCD_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F200_Def.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define LCD_TYPE LCD_R_TYPE //LCD_R_TYPE, LCD_1C_TYPE, or LCD_4C_TYPE
//LCD Panel driving ability
#define LCD_DRIVEP_STRONG 0
#define LCD_DRIVEP_MEDIUM 1
#define LCD_DRIVEP_LOW 3
#define mskLCD_DRIVEP_STRONG (LCD_DRIVEP_STRONG<<28)
#define mskLCD_DRIVEP_MEDIUM (LCD_DRIVEP_MEDIUM<<28)
#define mskLCD_DRIVEP_LOW (LCD_DRIVEP_LOW<<28)
//LCD_PCLK rate
#define LCD_RATE_DIV64 0
#define LCD_RATE_DIV128 1
#define mskLCD_RATE_DIV64 (LCD_RATE_DIV64<<11)
#define mskLCD_RATE_DIV128 (LCD_RATE_DIV128<<11)
//LCD Clock source
#define LCD_CLOCK_ILRC 0
#define LCD_CLOCK_ELS 1
#define mskLCD_CLOCK_ILRC (LCD_CLOCK_ILRC<<10)
#define mskLCD_CLOCK_ELS (LCD_CLOCK_ELS<<10)
//LCD Duty
#define LCD_HALF_DUTY 1 // 1/2 duty
#define LCD_ONE_THIRD_DUTY 2 // 1/3 duty
#define LCD_ONE_FOURTH_DUTY 3 // 1/4 duty
#define mskLCD_HALF_DUTY (LCD_HALF_DUTY<<8)
#define mskLCD_ONE_THIRD_DUTY (LCD_ONE_THIRD_DUTY<<8)
#define mskLCD_ONE_FOURTH_DUTY (LCD_ONE_FOURTH_DUTY<<8)
//LCD Bias
#define LCD_ONE_THIRD_BIAS 0 // 1/3 bias
#define LCD_HALF_BIAS 1 // 1/2 bias
#define mskLCD_ONE_THIRD_BIAS (LCD_ONE_THIRD_BIAS<<4)
#define mskLCD_HALF_BIAS (LCD_HALF_BIAS<<4)
//LCD Type
#define LCD_R_TYPE 0
#define LCD_4C_TYPE 1
#define LCD_1C_TYPE 2
#define mskLCD_R_TYPE (LCD_R_TYPE<<2)
#define mskLCD_4C_TYPE (LCD_4C_TYPE<<2)
#define mskLCD_1C_TYPE (LCD_1C_TYPE<<2)
//LCD R-type resistance
#define LCD_REF_400K 0
#define LCD_REF_200K 1
#define LCD_REF_100K 2
#define LCD_REF_35K 3
#define mskLCD_REF_400K (LCD_REF_400K<<1)
#define mskLCD_REF_200K (LCD_REF_200K<<1)
#define mskLCD_REF_100K (LCD_REF_100K<<1)
#define mskLCD_REF_35K (LCD_REF_35K<<1)
//LCD 1C-type VCP
#define mskLCD_1C_VCP_2P7V 0
#define mskLCD_1C_VCP_2P8V 1
#define mskLCD_1C_VCP_2P9V 2
#define mskLCD_1C_VCP_3P0V 3
#define mskLCD_1C_VCP_3P1V 4
#define mskLCD_1C_VCP_3P2V 5
#define mskLCD_1C_VCP_3P3V 6
#define mskLCD_1C_VCP_3P4V 7
//LCD 4C-type VCP
#define mskLCD_4C_VCP_2P7V 0
#define mskLCD_4C_VCP_2P8V 1
#define mskLCD_4C_VCP_2P9V 2
#define mskLCD_4C_VCP_3P0V 3
#define mskLCD_4C_VCP_3P06V 4
#define mskLCD_4C_VCP_3P14V 5
#define mskLCD_4C_VCP_3P2V 6
#define mskLCD_4C_VCP_3P3V 7
#define mskLCD_4C_VCP_3P4V 8
#define mskLCD_4C_VCP_3P6V 9
#define mskLCD_4C_VCP_3P8V 10
#define mskLCD_4C_VCP_4P0V 11
#define mskLCD_4C_VCP_4P2V 12
#define mskLCD_4C_VCP_4P4V 13
#define mskLCD_4C_VCP_4P7V 14
#define mskLCD_4C_VCP_5P0V 15
//LCD Frame Interrupt Enable/Disable
#define LCD_FRAME_IE_ENABLE 1
#define LCD_FRAME_IE_DISABLE 0
#define mskLCD_FRAME_IE_ENABLE (LCD_FRAME_IE_ENABLE<<7)
#define mskLCD_FRAME_IE_DISABLE (LCD_FRAME_IE_DISABLE<<7)
//LCD Frame Counter Enable/Disable
#define LCD_FRAME_COUNTER_ENABLE 1
#define LCD_FRAME_COUNTER_DISABLE 0
#define mskLCD_FRAME_COUNTER_ENABLE LCD_FRAME_COUNTER_ENABLE
#define mskLCD_FRAME_COUNTER_DISABLE LCD_FRAME_COUNTER_DISABLE
//LCD Frame Counter Threshold
#define LCD_FRAME_COUNTER_THRESHOLD 31 //0 < LCD_FRAME_COUNTER_THRESHOLD < 32
/*_____ M A C R O S ________________________________________________________*/
//LCD HCLK Enable/Disable
#define __LCD_ENABLE_LCDHCLK SN_SYS1->AHBCLKEN |= (1<<2)
#define __LCD_DISABLE_LCDHCLK SN_SYS1->AHBCLKEN &= ~(1<<2)
//LCD Driver Enable/Disable
#define __LCD_ENABLE SN_LCD->CTRL |= 0x1
#define __LCD_DISENABLE SN_LCD->CTRL &= ~0x1
//LCD SEGMENT Group 2 Enable/Disable
#define __LCD_SEGMENT_GROUP2_ENABLE SN_LCD->CTRL_b.SEGSEL2 = ENABLE
#define __LCD_SEGMENT_GROUP2_DISABLE SN_LCD->CTRL_b.SEGSEL2 = DISABLE
//LCD SEGMENT Group 1 Enable/Disable
#define __LCD_SEGMENT_GROUP1_ENABLE SN_LCD->CTRL_b.SEGSEL1 = ENABLE
#define __LCD_SEGMENT_GROUP1_DISABLE SN_LCD->CTRL_b.SEGSEL1 = DISABLE
//LCD Blank mode Enable/Disable
#define __LCD_DISPLAY_BLANK_ENABLE SN_LCD->CTRL1_b.LCDBNK = ENABLE
#define __LCD_DISPLAY_BLANK_DISABLE SN_LCD->CTRL1_b.LCDBNK = DISABLE
/*_____ D E C L A R A T I O N S ____________________________________________*/
void LCD_RtypeInit(void);
void LCD_1CtypeInit(void);
void LCD_4CtypeInit(void);
void LCD_SelectClockSource(uint32_t src);
void LCD_SetFrameCounterInterrupt(uint32_t CEN, uint32_t FCT, uint32_t IE);
#endif /*__SN32F760_PMU_H*/

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/******************** (C) COPYRIGHT 2017 SONiX *******************************
* COMPANY: SONiX
* DATE: 2017/07
* AUTHOR: SA1
* IC: SN32F240B
* DESCRIPTION: PMU related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2017/07/07 SA1 1. First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/***************************************************************************************************
* Function : PMU_Setting
* Description : Setting and enter specified Low power mode
* Input : mode - specified Low power mode (PMU_SLEEP, PMU_DEEP_SLEEP, PMU_DEEP_PWR_DOWN)
* Output : None
* Return : None
* Note : None
****************************************************************************************************/
void PMU_Setting(uint16_t mode)
{
SN_PMU->CTRL = mode;
__WFI();
SN_PMU->CTRL = 0x0;
}

18
os/hal/ports/SN32/LLD/SN32F24xB/PMU/PMU_drive.h Normal file
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@ -0,0 +1,18 @@
#ifndef __SN32F240B_PMU_H
#define __SN32F240B_PMU_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define PMU_SLEEP 4
#define PMU_DEEP_SLEEP 2
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
void PMU_Setting(uint16_t mode_sel);
#endif /*__SN32F240B_PMU_H*/

153
os/hal/ports/SN32/LLD/SN32F24xB/RTC/RTC.c
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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: RTC related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include "RTC.h"
#include "..\..\System\SYS_con_drive.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : RTC_IRQHandler
* Description : None
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void RTC_IRQHandler(void)
{
if(SN_RTC->RIS & mskRTC_SECIF)
{
SN_GPIO0->DATA_b.DATA0 = ~SN_GPIO0->DATA_b.DATA0;
SN_RTC->IC = mskRTC_SECIC; //Clear Second interrupt status
}
if(SN_RTC->RIS & mskRTC_ALMIF)
{
SN_GPIO0->DATA_b.DATA1 = ~SN_GPIO0->DATA_b.DATA1;
SN_RTC->IC = mskRTC_ALMIC; //Clear Alarm interrupt status
}
if(SN_RTC->RIS & mskRTC_OVFIF)
{
SN_GPIO0->DATA_b.DATA2 = ~SN_GPIO0->DATA_b.DATA2;
SN_RTC->IC = mskRTC_OVFIC; //Clear Overflow interrupt status
}
}
/*****************************************************************************
* Function : RTC_Initial
* Description : RTC initial set
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void RTC_Init(void)
{
__RTC_ENABLE_RTCHCLK; //Enable HCLK for RTC
#if RTC_MODE == SECOND //Second will occur every 1 second
RTC_SelectClockSource(RTC_CLKSEL_ELS); //Clock Source select
SN_RTC->IE = mskRTC_SECIE_ENABLE; //Enable Second Interrupt
__RTC_SECCNTV(32767); //Second counter reload value
#endif
#if RTC_MODE == ALARM //Alarm will occur after 10 seconds
RTC_SelectClockSource(RTC_CLKSEL_ELS); //Clock Source select
SN_RTC->IE = mskRTC_ALMIE_ENABLE; //Enable Alarm Interrupt
__RTC_SECCNTV(32767); //Second counter reload value
__RTC_ALMCNTV(9); //Alarm counter reload value
#endif
#if RTC_MODE == OVERFLOW //Overflow will occur in 54975.58139 seconds(15.271 hours)
RTC_SelectClockSource(RTC_CLKSEL_EHS); //Clock Source select
SN_RTC->IE =
(mskRTC_OVFIE_ENABLE | mskRTC_ALMIE_ENABLE); //Enable Overflow Interrupt
__RTC_SECCNTV(1); //Second counter reload value & Second will occur in 12.8u second
__RTC_ALMCNTV(75000000); //Alarm counter reload value & Alarm will occur in 960 seconds(16 minutes)
#endif
//Enable RTC NVIC interrupt
RTC_NvicEnable();
__RTC_ENABLE; //Enable RTC
}
/***********************************************************************************
* Function : RTC_SelectClockSource
* Description : Select RTC clcok source
* Input : RTC clock source -
RTC_CLKSEL_ILRC or RTC_CLKSEL_ELS or RTC_CLKSEL_EHS
* Output : None
* Return : None
* Note : None
***********************************************************************************/
void RTC_SelectClockSource(uint32_t src)
{
if (src == RTC_CLKSEL_ELS)
SYS0_EnableELSXtal();
else if (src == RTC_CLKSEL_EHS)
SYS0_EnableEHSXtal(SYS0_EHS_FREQ_DRIVE_HIGH);
SN_RTC->CLKS = src; //clock source select
}
/*****************************************************************************
* Function : RTC_NvicEnable
* Description : Enable RTC interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void RTC_NvicEnable(void)
{
NVIC_ClearPendingIRQ(RTC_IRQn);
NVIC_EnableIRQ(RTC_IRQn);
NVIC_SetPriority(RTC_IRQn,0); // Set interrupt priority (default)
}
/*****************************************************************************
* Function : RTC_NvicDisable
* Description : Disable RTC interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void RTC_NvicDisable(void)
{
NVIC_DisableIRQ(RTC_IRQn);
}

66
os/hal/ports/SN32/LLD/SN32F24xB/RTC/RTC.h
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@ -1,66 +0,0 @@
#ifndef __SN32F240_RTC_H
#define __SN32F240_RTC_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define SECOND 0
#define ALARM 1
#define OVERFLOW 2
#define RTC_MODE SECOND //SECOND, ALARM, OVERFLOW
//RTC enable
#define mskRTC_RTCEN_DISABLE 0
#define mskRTC_RTCEN_ENABLE 1
//RTC Clock source
#define RTC_CLKSEL_ILRC 0
#define RTC_CLKSEL_ELS 1
#define RTC_CLKSEL_EHS 3
//RTC Interrupt Enable/Disable
#define RTC_IE_ENABLE 1
#define RTC_IE_DISABLE 0
#define mskRTC_SECIE_ENABLE RTC_IE_ENABLE
#define mskRTC_SECIE_DISABLE RTC_IE_DISABLE
#define mskRTC_ALMIE_ENABLE (RTC_IE_ENABLE<<1)
#define mskRTC_ALMIE_DISABLE (RTC_IE_DISABLE<<1)
#define mskRTC_OVFIE_ENABLE (RTC_IE_ENABLE<<2)
#define mskRTC_OVFIE_DISABLE (RTC_IE_DISABLE<<2)
#define mskRTC_SECIF (0x1<<0) //Interrupt flag for Second
#define mskRTC_ALMIF (0x1<<1) //Interrupt flag for Alarm
#define mskRTC_OVFIF (0x1<<2) //Interrupt flag for Overflow
#define mskRTC_SECIC mskRTC_SECIF
#define mskRTC_ALMIC mskRTC_ALMIF
#define mskRTC_OVFIC mskRTC_OVFIF
/*_____ M A C R O S ________________________________________________________*/
//LCD HCLK Enable/Disable
#define __RTC_ENABLE_RTCHCLK (SN_SYS1->AHBCLKEN |= (1<<23))
#define __RTC_DISABLE_RTCHCLK (SN_SYS1->AHBCLKEN &= ~(1<<23))
//RTC Enable/Disable
#define __RTC_ENABLE (SN_RTC->CTRL |= mskRTC_RTCEN_ENABLE)
#define __RTC_SECCNTV(value) (SN_RTC->SECCNTV = value)
#define __RTC_ALMCNTV(value) (SN_RTC->ALMCNTV = value)
/*_____ D E C L A R A T I O N S ____________________________________________*/
void RTC_Init(void);
void RTC_SelectClockSource(uint32_t src);
void RTC_NvicEnable(void);
void RTC_NvicDisable(void);
#endif /*__SN32F240_RTC_H*/

142
os/hal/ports/SN32/LLD/SN32F24xB/SysTick/SysTick.c
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@ -1,71 +1,71 @@
/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: SysTick related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include "SysTick.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : SysTick_Init
* Description : Initialization of SysTick timer
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SysTick_Init (void)
{
SystemCoreClockUpdate();
__SYSTICK_SET_TIMER_PERIOD(10); //RELOAD = (system tick clock frequency ¡Ñ 10 ms)/1000 -1
__SYSTICK_CLEAR_COUNTER_AND_FLAG;
#if SYSTICK_IRQ == INTERRUPT_METHOD
SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
#else
SysTick->CTRL = 0x5; //Enable SysTick timer ONLY
#endif
}
/*****************************************************************************
* Function : SysTick_Handler
* Description : ISR of SysTick interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void SysTick_Handler(void)
{
__SYSTICK_CLEAR_COUNTER_AND_FLAG;
}
/******************** (C) COPYRIGHT 2017 SONiX *******************************
* COMPANY: SONiX
* DATE: 2017/07
* AUTHOR: SA1
* IC: SN32F240B
* DESCRIPTION: SysTick related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2017/07/07 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include "SysTick.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : SysTick_Init
* Description : Initialization of SysTick timer
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SysTick_Init (void)
{
SystemCoreClockUpdate();
__SYSTICK_SET_TIMER_PERIOD(10); //RELOAD = (system tick clock frequency ¡Ñ 10 ms)/1000 -1
__SYSTICK_CLEAR_COUNTER_AND_FLAG;
#if SYSTICK_IRQ == INTERRUPT_METHOD
SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
#else
SysTick->CTRL = 0x5; //Enable SysTick timer ONLY
#endif
}
/*****************************************************************************
* Function : SysTick_Handler
* Description : ISR of SysTick interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void SysTick_Handler(void)
{
__SYSTICK_CLEAR_COUNTER_AND_FLAG;
}

46
os/hal/ports/SN32/LLD/SN32F24xB/SysTick/SysTick.h
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@ -1,23 +1,23 @@
#ifndef __SN32F240_SYSTICK_H
#define __SN32F240_SYSTICK_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F200_Def.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define SYSTICK_IRQ POLLING_METHOD //INTERRUPT_METHOD: Enable SysTick timer and interrupt
//POLLING_METHOD: Enable SysTick timer ONLY
/*_____ M A C R O S ________________________________________________________*/
#define __SYSTICK_SET_TIMER_PERIOD(ms) SysTick->LOAD = SystemCoreClock * ms /1000 - 1
#define __SYSTICK_CLEAR_COUNTER_AND_FLAG SysTick->VAL = 0xFF
/*_____ D E C L A R A T I O N S ____________________________________________*/
void SysTick_Init(void);
#endif /*__SN32F240_SYSTICK_H*/
#ifndef __SN32F240B_SYSTICK_H
#define __SN32F240B_SYSTICK_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F200_Def.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define SYSTICK_IRQ POLLING_METHOD //INTERRUPT_METHOD: Enable SysTick timer and interrupt
//POLLING_METHOD: Enable SysTick timer ONLY
/*_____ M A C R O S ________________________________________________________*/
#define __SYSTICK_SET_TIMER_PERIOD(ms) SysTick->LOAD = SystemCoreClock * ms /1000 - 1
#define __SYSTICK_CLEAR_COUNTER_AND_FLAG SysTick->VAL = 0xFF
/*_____ D E C L A R A T I O N S ____________________________________________*/
void SysTick_Init(void);
#endif /*__SN32F240B_SYSTICK_H*/

9
os/hal/ports/SN32/LLD/SN32F24xB/SysTick/driver.mk Normal file
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ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_SYSTICK TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/SysTick/hal_st_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/SysTick/hal_st_lld.c
endif
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/SysTick

0
os/hal/ports/SN32/LLD/SN32F24xB/CT/hal_st_lld.c → os/hal/ports/SN32/LLD/SN32F24xB/SysTick/hal_st_lld.c
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0
os/hal/ports/SN32/LLD/SN32F24xB/CT/hal_st_lld.h → os/hal/ports/SN32/LLD/SN32F24xB/SysTick/hal_st_lld.h
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184
os/hal/ports/SN32/LLD/SN32F24xB/UART/UART.h Normal file
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#ifndef __SN32F240B_UART_H
#define __SN32F240B_UART_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4001 6000 (UART0)
0x4001 4000 (UART1)
0x4001 2000 (UART1)
*/
#define UART0_CLK_EN (0x01<<16)
#define UART1_CLK_EN (0x01<<17)
#define UART2_CLK_EN (0x01<<18)
/**************Line Control Define******/
#define UART_CHARACTER_LEN5BIT (0x00)
#define UART_CHARACTER_LEN6BIT (0x01)
#define UART_CHARACTER_LEN7BIT (0x02)
#define UART_CHARACTER_LEN8BIT (0x03)
/***********************/
#define UART_STOPBIT_1BIT (0x0<<2)
#define UART_STOPBIT_2BIT (0x1<<2)
/***********************/
#define UART_PARITY_BIT_DISEN (0x0<<3)
#define UART_PARITY_BIT_EN (0x1<<3)
/***********************/
#define UART_PARITY_SELECTODD (0x00<<4)
#define UART_PARITY_SELECTEVEN (0x01<<4)
#define UART_PARITY_SELECTFORC1 (0x02<<4)
#define UART_PARITY_SELECTFORC0 (0x03<<4)
/***********************/
#define UART_BREAK_DISEN (0x0<<6)
#define UART_BREAK_EN (0x1<<6)
/***********************/
#define UART_DIVISOR_DISEN (0x0<<7)
#define UART_DIVISOR_EN (0x1<<7)
#define UART_OVER_SAMPLE_16 (0x0<<8)
#define UART_OVER_SAMPLE_8 (0x1<<8)
/***Baud rate pre-scaler multilier = MULVAL+1***/
#define UART_MULVAL_0 (0x0000<<4)
#define UART_MULVAL_1 (0x0001<<4)
#define UART_MULVAL_2 (0x0002<<4)
#define UART_MULVAL_3 (0x0003<<4)
#define UART_MULVAL_4 (0x0004<<4)
#define UART_MULVAL_5 (0x0005<<4)
#define UART_MULVAL_6 (0x0006<<4)
#define UART_MULVAL_7 (0x0007<<4)
#define UART_MULVAL_8 (0x0008<<4)
#define UART_MULVAL_9 (0x0009<<4)
#define UART_MULVAL_10 (0x000A<<4)
#define UART_MULVAL_11 (0x000B<<4)
#define UART_MULVAL_12 (0x000C<<4)
#define UART_MULVAL_13 (0x000D<<4)
#define UART_MULVAL_14 (0x000E<<4)
#define UART_MULVAL_15 (0x000F<<4)
/***Buad rate pre-scaler divisor value********/
#define UART_DIVADDVAL_0 (0x000)
#define UART_DIVADDVAL_1 (0x001)
#define UART_DIVADDVAL_2 (0x002)
#define UART_DIVADDVAL_3 (0x003)
#define UART_DIVADDVAL_4 (0x004)
#define UART_DIVADDVAL_5 (0x005)
#define UART_DIVADDVAL_6 (0x006)
#define UART_DIVADDVAL_7 (0x007)
#define UART_DIVADDVAL_8 (0x008)
#define UART_DIVADDVAL_9 (0x009)
#define UART_DIVADDVAL_10 (0x00A)
#define UART_DIVADDVAL_11 (0x00B)
#define UART_DIVADDVAL_12 (0x00C)
#define UART_DIVADDVAL_13 (0x00D)
#define UART_DIVADDVAL_14 (0x00E)
#define UART_DIVADDVAL_15 (0x00F)
/***UART divisor latch MSB reg[7:0]. determines the baud rate***/
/***UART divisor latch LSB reg[7:0]. determines the baud rate***/
#define UART_FIFO_ENABLE (0x01)
#define UART_RXFIFO_RESET (0x01<<1)
#define UART_TXFIFO_RESET (0x01<<2)
#define UART_RXTRIGGER_LEVEL1 (0x00<<6)
/***UART Interrupt Enable register***/
#define UART_ABTOIE_EN (0x01<<9) //auto-buad time out INT
#define UART_ABEOIE_EN (0x01<<8) //End of auto-buad INT
#define UART_TEMTIE_EN (0x01<<4) //Transmitter empty flag
#define UART_RLSIE_EN (0x01<<2) //Rx Receive line status(RLS) INT
#define UART_THREIE_EN (0x01<<1) //Transmitter holding register empty flag INT
#define UART_RDAIE_EN (0x01) //character receive(RDA) time-out INT
/*** UARTn_CTRL************/
#define UART_EN (0x01)
#define UART_RX_EN (0x01<<6)
#define UART_TX_EN (0x01<<7)
#define UART_CTRL_EN 1
#define UART_CTRL_DIS 0
#define UART_FIFOCTRL_RESET 1
/*** UARTn_ABCCTRL************/
#define UART_ABCCTRL_START (0x01) //START:1(Auto-baud is running), START:0(Auto-baud is not running)
#define UART_ABCCTRL_MODE0 (0x00<<1)
#define UART_ABCCTRL_MODE1 (0x01<<1)
#define UART_ABCCTRL_RESTART (0x01<<2)
#define UART_ABEO_EN (0x01<<8)
#define UART_ABTO_EN (0x01<<9)
/*** Line status register************/
#define UART_LS_RDR (0x01) //receiver data ready flag
#define UART_LS_OE (0x01<<1) //overrun error flag
#define UART_LS_PE (0x01<<2) //parity error flag
#define UART_LS_FE (0x01<<3) //framing error flag
#define UART_LS_BI (0x01<<4) //break interrupt flag
#define UART_LS_THRE (0x01<<5) //transmitter holding register empty flag
#define UART_LS_TEMT (0x01<<6) //transmitter empty flag
#define UART_LS_RXFE (0x01<<7) //error in RX FIFO flag
#define mskUART_LS_RDR (0x01)
#define mskUART_LS_OE (0x01<<1)
#define mskUART_LS_PE (0x01<<2)
#define mskUART_LS_FE (0x01<<3)
#define mskUART_LS_BI (0x01<<4)
#define mskUART_LS_THRE (0x01<<5)
#define mskUART_LS_TEMT (0x01<<6)
#define mskUART_LS_RXFE (0x01<<7)
/*** Interrupt Identification register************/
#define UART_RLS 3
#define UART_RDA 2
#define UART_THRE 1
#define UART_TEMT 7
#define UART_II_STATUS 0 //the INTstatus can be determined by UARTn_II[3:1]
#define UART_II_ABEOIF (0x01<<8) //end of auto-baud interrupt flag
#define UART_II_ABTOIF (0x01<<9) //auto-baud time-out interrupt flag
#define mskUART_INTID_STATUS 7 //interrupt corresponding to the UARTn RX FIFO
#define mskUART_II_STATUS (0x01)
#define mskUART_II_ABEOIF (0x01<<8)
#define mskUART_II_ABTOIF (0x01<<9)
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern uint32_t GulNum;
extern uint8_t bUART0_RecvFIFO[];
extern uint32_t GulNum1;
extern uint8_t bUART1_RecvFIFO[];
extern uint32_t GulNum2;
extern uint8_t bUART2_RecvFIFO[];
extern volatile uint8_t bUART0_RecvNew;
extern volatile uint8_t bUART1_RecvNew;
extern volatile uint8_t bUART2_RecvNew;
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern void UART0_Init(void);
extern void UART0_SendByte (uint8_t ucDat);
extern void UART0_Enable(void);
extern void UART0_Disable(void);
extern void UART0_InterruptEnable(void);
extern void UART0_AutoBaudrateInit(void);
extern void UART1_Init(void);
extern void UART1_SendByte (uint8_t ucDat);
extern void UART1_Enable(void);
extern void UART1_Disable(void);
extern void UART1_InterruptEnable(void);
extern void UART1_AutoBaudrateInit(void);
void UART2_Init(void);
void UART2_SendByte (uint8_t ucDat);
void UART2_Enable(void);
void UART2_Disable(void);
void UART2_InterruptEnable(void);
void UART2_AutoBaudrateInit(void);
#endif /*__SN32F240B_UART_H*/

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/******************** (C) COPYRIGHT 2017 SONiX *******************************
* COMPANY: SONiX
* DATE: 2017/07
* AUTHOR: SA1
* IC: SN32F240B
* DESCRIPTION: UART0 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2017/07/07 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include "UART.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint8_t bUART0_RecvNew;
uint32_t GulNum;
uint8_t bUART0_RecvFIFO[56];
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : UART0_IRQHandler
* Description : UART0 interrupt service routine
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void UART0_IRQHandler (void)
{
uint32_t II_Buf, LS_Buf;
volatile uint32_t Null_Buf;
II_Buf = SN_UART0->II;
while ((II_Buf & mskUART_II_STATUS) == UART_II_STATUS) //check interrupt status, the INT can be determined by USARTn_II[3:1]
{
switch ((II_Buf>>1) & mskUART_INTID_STATUS)
{
case UART_RLS: //Receive Line Status
LS_Buf = SN_UART0->LS;
if((LS_Buf & mskUART_LS_OE) == UART_LS_OE) //Overrun Error
{ }
if((LS_Buf & mskUART_LS_RXFE) == UART_LS_RXFE)//RX FIFO Error
{
if((LS_Buf & mskUART_LS_PE) == UART_LS_PE)//Parity Error
Null_Buf = SN_UART0->RB; //Clear interrupt
if((LS_Buf & mskUART_LS_FE) == UART_LS_FE) //Framing Error
Null_Buf = SN_UART0->RB; //Clear interrupt
if((LS_Buf & mskUART_LS_BI) == UART_LS_BI) //Break Interrupt
Null_Buf = SN_UART0->RB; //Clear interrupt
}
break;
case UART_RDA: //Receive Data Available
LS_Buf = SN_UART0->LS;
bUART0_RecvNew = 1;
if((LS_Buf & mskUART_LS_RDR) == UART_LS_RDR)//Receiver Data Ready
{
bUART0_RecvFIFO[GulNum] = SN_UART0->RB;
GulNum++;
}
if(GulNum == 56)
GulNum = 0;
break;
case UART_THRE: //THRE interrupt
LS_Buf = SN_UART0->LS;
if((LS_Buf & mskUART_LS_THRE) == UART_LS_THRE)//THRE empty
{ //SN_UART0->TH = Null_Buf; //Clear interrupt
}
break;
case UART_TEMT: //TEMT interrupt
LS_Buf = SN_UART0->LS;
if((LS_Buf & mskUART_LS_TEMT) == UART_LS_TEMT)
{ //SN_UART0->TH = Null_Buf; //Clear interrupt
}
break;
default:
break;
} //end switch ((II_Buf>>1) & mskUART_INTID_STATUS)
II_Buf = SN_UART0->II;
} //end while ((II_Buf&0x01) == mskUART_II_STATUS)
if ((II_Buf & mskUART_II_ABEOIF) == UART_II_ABEOIF) //Auto Baud interrupt
SN_UART0->ABCTRL |= UART_ABEO_EN;
else if((II_Buf & mskUART_II_ABTOIF) == UART_II_ABTOIF) //Auto Baud time-out interrupt
SN_UART0->ABCTRL |= UART_ABTO_EN;
}
/*****************************************************************************
* Function : UART0_Init
* Description : Initialization of UART0
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART0_Init (void)
{
SN_SYS1->AHBCLKEN |= UART0_CLK_EN; //Enables clock for UART0
//===Line Control===
//setting character Word length(5/6/7/8 bit)
SN_UART0->LC = (UART_CHARACTER_LEN8BIT //8bit character length.
| UART_STOPBIT_1BIT //stop bit of 1 bit
| UART_PARITY_BIT_DISEN //parity bit is disable
| UART_PARITY_SELECTODD //parity bit is odd
| UART_BREAK_DISEN //Break Transmission control disable
| UART_DIVISOR_EN); //Divisor Latch Access enable
//===Baud Rate Calculation===
//UART PCLK = 12MHz, Baud rate = 115200
SN_UART0->FD = (UART_OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5);
SN_UART0->DLM = 0;
SN_UART0->DLL = 4;
/*
//UART PCLK = 12MHz, Baud rate = 57600
SN_UART0->FD = (OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5);
SN_UART0->DLM = 0;
SN_UART0->DLL = 8;
*/
SN_UART0->LC &= ~(UART_DIVISOR_EN); //Disable divisor latch
//===Auto Baud Rate===
//UART0_Autobaudrate_Init(); //Auto buad rate initial
//===FIFO Control===
SN_UART0->FIFOCTRL =(UART_FIFO_ENABLE //Enable USART FIFOs
| UART_RXFIFO_RESET //RX FIFO Reset
| UART_TXFIFO_RESET //TX FIFO Reset
| UART_RXTRIGGER_LEVEL1); //RX Trigger Level(1 characters)
//===Oversampling===
//SN_UART0->FD |= UART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16
//===Half-duplex===
//SN_UART0->HDEN = 1; //Half-duplex mode enable
//===Interrupt Enable===
UART0_InterruptEnable();
//===UART Control===
SN_UART0->CTRL =(UART_EN //Enable USART0
| UART_RX_EN //Enable RX
| UART_TX_EN); //Enable TX
//===NVIC===
NVIC_EnableIRQ(UART0_IRQn); //Enable USART0 INT
}
/*****************************************************************************
* Function : UART0_SendByte
* Description : MCU sends Byte through UTXD0
* Input : ucDat - data to be sent
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART0_SendByte (uint8_t ucDat)
{
SN_UART0->TH = ucDat;
while ((SN_UART0->LS & 0x40) == 0);
}
/*****************************************************************************
* Function : UART0_AutoBaudrateInit
* Description : Initialization of UART0 Auto baud rate.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART0_AutoBaudrateInit(void)
{
SN_UART0->ABCTRL =(UART_ABTO_EN //Clear Auto Baud Time-out interrupt
| UART_ABEO_EN //Clear Auto Baud interrupt
| UART_ABCCTRL_RESTART //Restart in case of time-out
| UART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1
| UART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running)
}
/*****************************************************************************
* Function : UART0_Enable
* Description : Enable UART0
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART0_Enable(void)
{
//Enable HCLK for UART0
SN_SYS1->AHBCLKEN |= UART0_CLK_EN; //Enables clock for UART0
SN_UART0->CTRL_b.UARTEN = UART_CTRL_EN; //UART enable bit
}
/*****************************************************************************
* Function : UART0_Disable
* Description : Disable UART0
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART0_Disable(void)
{
SN_UART0->CTRL_b.UARTEN = UART_CTRL_DIS; //UART disable
//Disable HCLK for UART0
SN_SYS1->AHBCLKEN &= ~(UART0_CLK_EN); //Disable clock for UART0
}
/*****************************************************************************
* Function : UART0_InterruptEnable
* Description : Interrupt Enable
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART0_InterruptEnable(void)
{
SN_UART0->IE =(UART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt
| UART_THREIE_EN //Enable THRE interrupt
| UART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt
| UART_TEMTIE_EN //Enable TEMT interrupt
| UART_ABEOIE_EN //Enable Auto Baud interrupt
| UART_ABTOIE_EN); //Enable Auto Baud time-out interrupt
}

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os/hal/ports/SN32/LLD/SN32F24xB/UART/UART1.c Normal file
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/******************** (C) COPYRIGHT 2017 SONiX *******************************
* COMPANY: SONiX
* DATE: 2017/07
* AUTHOR: SA1
* IC: SN32F240B
* DESCRIPTION: UART1 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2017/07/07 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include "UART.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint8_t bUART1_RecvNew;
uint32_t GulNum1;
uint8_t bUART1_RecvFIFO[56];
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : UART1_IRQHandler
* Description : UART1 interrupt service routine
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void UART1_IRQHandler (void)
{
uint32_t II_Buf, LS_Buf;
volatile uint32_t Null_Buf;
II_Buf = SN_UART1->II;
while ((II_Buf & mskUART_II_STATUS) == UART_II_STATUS) //check interrupt status, the INT can be determined by UARTn_II[3:1]
{
switch ((II_Buf>>1) & mskUART_INTID_STATUS)
{
case UART_RLS: //Receive Line Status
LS_Buf = SN_UART1->LS;
if((LS_Buf & mskUART_LS_OE) == UART_LS_OE) //Overrun Error
{ }
if((LS_Buf & mskUART_LS_RXFE) == UART_LS_RXFE)//RX FIFO Error
{
if((LS_Buf & mskUART_LS_PE) == UART_LS_PE)//Parity Error
Null_Buf = SN_UART1->RB; //Clear interrupt
if((LS_Buf & mskUART_LS_FE) == UART_LS_FE) //Framing Error
Null_Buf = SN_UART1->RB; //Clear interrupt
if((LS_Buf & mskUART_LS_BI) == UART_LS_BI) //Break Interrupt
Null_Buf = SN_UART1->RB; //Clear interrupt
}
break;
case UART_RDA: //Receive Data Available
LS_Buf = SN_UART1->LS;
bUART1_RecvNew = 1;
if((LS_Buf & mskUART_LS_RDR) == UART_LS_RDR)//Receiver Data Ready
{
bUART1_RecvFIFO[GulNum1] = SN_UART1->RB;
GulNum1++;
}
if(GulNum1 == 56)
GulNum1 = 0;
break;
case UART_THRE: //THRE interrupt
LS_Buf = SN_UART1->LS;
if((LS_Buf & mskUART_LS_THRE) == UART_LS_THRE)//THRE empty
{ //SN_UART1->TH = Null_Buf; //Clear interrupt
}
break;
case UART_TEMT: //TEMT interrupt
LS_Buf = SN_UART1->LS;
if((LS_Buf & mskUART_LS_TEMT) == UART_LS_TEMT)
{ //SN_UART1->TH = Null_Buf; //Clear interrupt
}
break;
default:
break;
} //end switch ((II_Buf>>1) & mskUART_INTID_STATUS)
II_Buf = SN_UART1->II;
} //end while ((II_Buf&0x01) == mskUART_II_STATUS)
if ((II_Buf & mskUART_II_ABEOIF) == UART_II_ABEOIF) //Auto Baud interrupt
SN_UART1->ABCTRL |= UART_ABEO_EN;
else if((II_Buf & mskUART_II_ABTOIF) == UART_II_ABTOIF) //Auto Baud time-out interrupt
SN_UART1->ABCTRL |= UART_ABTO_EN;
}
/*****************************************************************************
* Function : UART1_Init
* Description : Initialization of UART1
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART1_Init (void)
{
SN_SYS1->AHBCLKEN |= UART1_CLK_EN; //Enables clock for UART1
//===Line Control===
//setting character Word length(5/6/7/8 bit)
SN_UART1->LC = (UART_CHARACTER_LEN8BIT //8bit character length.
| UART_STOPBIT_1BIT //stop bit of 1 bit
| UART_PARITY_BIT_DISEN //parity bit is disable
| UART_PARITY_SELECTODD //parity bit is odd
| UART_BREAK_DISEN //Break Transmission control disable
| UART_DIVISOR_EN); //Divisor Latch Access enable
//===Baud Rate Calculation===
//UART PCLK = 12MHz, Baud rate = 115200
SN_UART1->FD = (UART_OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5);
SN_UART1->DLM = 0;
SN_UART1->DLL = 4;
/*
//UART PCLK = 12MHz, Baud rate = 57600
SN_UART1->FD = (OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5);
SN_UART1->DLM = 0;
SN_UART1->DLL = 8;
*/
SN_UART1->LC &= ~(UART_DIVISOR_EN); //Disable divisor latch
//===Auto Baud Rate===
//UART1_Autobaudrate_Init(); //Auto buad rate initial
//===FIFO Control===
SN_UART1->FIFOCTRL =(UART_FIFO_ENABLE //Enable UART FIFOs
| UART_RXFIFO_RESET //RX FIFO Reset
| UART_TXFIFO_RESET //TX FIFO Reset
| UART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters)
//===Scratch Pad===
//SN_UART1->SP = 0; //A readable, writable byte
//===Oversampling===
//SN_UART1->FD |= UART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16
//===Half-duplex===
//SN_UART1->HDEN = 1; //Half-duplex mode enable
//===Interrupt Enable===
UART1_InterruptEnable();
//===UART Control===
SN_UART1->CTRL =(UART_EN //Enable UART0
| UART_RX_EN //Enable RX
| UART_TX_EN); //Enable TX
//===NVIC===
NVIC_EnableIRQ(UART1_IRQn); //Enable UART1 INT
}
/*****************************************************************************
* Function : UART1_SendByte
* Description : MCU sends Byte through UTXD1
* Input : ucDat - data to be sent
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART1_SendByte (uint8_t ucDat)
{
SN_UART1->TH = ucDat;
while ((SN_UART1->LS & 0x40) == 0);
}
/*****************************************************************************
* Function : UART1_AutoBaudrateInit
* Description : Initialization of UART1 Auto baud rate.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART1_AutoBaudrateInit(void)
{
SN_UART1->ABCTRL =(UART_ABTO_EN //Clear Auto Baud Time-out interrupt
| UART_ABEO_EN //Clear Auto Baud interrupt
| UART_ABCCTRL_RESTART //Restart in case of time-out
| UART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1
| UART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running)
}
/*****************************************************************************
* Function : UART1_Enable
* Description : Enable UART1
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART1_Enable(void)
{
//Enable HCLK for UART1
SN_SYS1->AHBCLKEN |= UART1_CLK_EN; //Enables clock for UART1
SN_UART1->CTRL_b.UARTEN = UART_CTRL_EN; //UART enable bit
}
/*****************************************************************************
* Function : UART1_Disable
* Description : Disable UART1
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART1_Disable(void)
{
SN_UART1->CTRL_b.UARTEN = UART_CTRL_DIS; //UART disable
//Disable HCLK for UART1
SN_SYS1->AHBCLKEN &= ~(UART1_CLK_EN); //Disable clock for UART1
}
/*****************************************************************************
* Function : UART1_InterruptEnable
* Description : Interrupt Enable
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART1_InterruptEnable(void)
{
SN_UART1->IE =(UART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt
| UART_THREIE_EN //Enable THRE interrupt
| UART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt
| UART_TEMTIE_EN //Enable TEMT interrupt
| UART_ABEOIE_EN //Enable Auto Baud interrupt
| UART_ABTOIE_EN); //Enable Auto Baud time-out interrupt
}

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os/hal/ports/SN32/LLD/SN32F24xB/UART/UART2.c Normal file
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/******************** (C) COPYRIGHT 2017 SONiX *******************************
* COMPANY: SONiX
* DATE: 2017/07
* AUTHOR: SA1
* IC: SN32F240B
* DESCRIPTION: UART2 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2017/07/07 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include "UART.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint8_t bUART2_RecvNew;
uint32_t GulNum2;
uint8_t bUART2_RecvFIFO[56];
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : UART2_IRQHandler
* Description : UART2 interrupt service routine
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void UART2_IRQHandler (void)
{
uint32_t II_Buf, LS_Buf;
volatile uint32_t Null_Buf;
II_Buf = SN_UART2->II;
while ((II_Buf & mskUART_II_STATUS) == UART_II_STATUS) //check interrupt status, the INT can be determined by UARTn_II[3:1]
{
switch ((II_Buf>>1) & mskUART_INTID_STATUS)
{
case UART_RLS: //Receive Line Status
LS_Buf = SN_UART2->LS;
if((LS_Buf & mskUART_LS_OE) == UART_LS_OE) //Overrun Error
{ }
if((LS_Buf & mskUART_LS_RXFE) == UART_LS_RXFE)//RX FIFO Error
{
if((LS_Buf & mskUART_LS_PE) == UART_LS_PE)//Parity Error
Null_Buf = SN_UART2->RB; //Clear interrupt
if((LS_Buf & mskUART_LS_FE) == UART_LS_FE) //Framing Error
Null_Buf = SN_UART2->RB; //Clear interrupt
if((LS_Buf & mskUART_LS_BI) == UART_LS_BI) //Break Interrupt
Null_Buf = SN_UART2->RB; //Clear interrupt
}
break;
case UART_RDA: //Receive Data Available
LS_Buf = SN_UART2->LS;
bUART2_RecvNew = 1;
if((LS_Buf & mskUART_LS_RDR) == UART_LS_RDR)//Receiver Data Ready
{
bUART2_RecvFIFO[GulNum2] = SN_UART2->RB;
GulNum2++;
}
if(GulNum2 == 56)
GulNum2 = 0;
break;
case UART_THRE: //THRE interrupt
LS_Buf = SN_UART2->LS;
if((LS_Buf & mskUART_LS_THRE) == UART_LS_THRE)//THRE empty
{ //SN_UART2->TH = Null_Buf; //Clear interrupt
}
break;
case UART_TEMT: //TEMT interrupt
LS_Buf = SN_UART2->LS;
if((LS_Buf & mskUART_LS_TEMT) == UART_LS_TEMT)
{ //SN_UART2->TH = Null_Buf; //Clear interrupt
}
break;
default:
break;
} //end switch ((II_Buf>>1) & mskUART_INTID_STATUS)
II_Buf = SN_UART2->II;
} //end while ((II_Buf&0x01) == mskUART_II_STATUS)
if ((II_Buf & mskUART_II_ABEOIF) == UART_II_ABEOIF) //Auto Baud interrupt
SN_UART2->ABCTRL |= UART_ABEO_EN;
else if((II_Buf & mskUART_II_ABTOIF) == UART_II_ABTOIF) //Auto Baud time-out interrupt
SN_UART2->ABCTRL |= UART_ABTO_EN;
}
/*****************************************************************************
* Function : UART2_Init
* Description : Initialization of UART2
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART2_Init (void)
{
SN_SYS1->AHBCLKEN |= UART2_CLK_EN; //Enables clock for UART2
//===Line Control===
//setting character Word length(5/6/7/8 bit)
SN_UART2->LC = (UART_CHARACTER_LEN8BIT //8bit character length.
| UART_STOPBIT_1BIT //stop bit of 1 bit
| UART_PARITY_BIT_DISEN //parity bit is disable
| UART_PARITY_SELECTODD //parity bit is odd
| UART_BREAK_DISEN //Break Transmission control disable
| UART_DIVISOR_EN); //Divisor Latch Access enable
//===Baud Rate Calculation===
//UART PCLK = 12MHz, Baud rate = 115200
SN_UART2->FD = (UART_OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5);
SN_UART2->DLM = 0;
SN_UART2->DLL = 4;
/*
//UART PCLK = 12MHz, Baud rate = 57600
SN_UART2->FD = (OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5);
SN_UART2->DLM = 0;
SN_UART2->DLL = 8;
*/
SN_UART2->LC &= ~(UART_DIVISOR_EN); //Disable divisor latch
//===Auto Baud Rate===
//UART2_Autobaudrate_Init(); //Auto buad rate initial
//===FIFO Control===
SN_UART2->FIFOCTRL =(UART_FIFO_ENABLE //Enable UART FIFOs
| UART_RXFIFO_RESET //RX FIFO Reset
| UART_TXFIFO_RESET //TX FIFO Reset
| UART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters)
//===Scratch Pad===
//SN_UART2->SP = 0; //A readable, writable byte
//===Oversampling===
//SN_UART2->FD |= UART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16
//===Half-duplex===
//SN_UART2->HDEN = 1; //Half-duplex mode enable
//===Interrupt Enable===
UART2_InterruptEnable();
//===UART Control===
SN_UART2->CTRL =(UART_EN //Enable UART0
| UART_RX_EN //Enable RX
| UART_TX_EN); //Enable TX
//===NVIC===
NVIC_EnableIRQ(UART2_IRQn); //Enable UART2 INT
}
/*****************************************************************************
* Function : UART2_SendByte
* Description : MCU sends Byte through UTXD1
* Input : ucDat - data to be sent
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART2_SendByte (uint8_t ucDat)
{
SN_UART2->TH = ucDat;
while ((SN_UART2->LS & 0x40) == 0);
}
/*****************************************************************************
* Function : UART2_AutoBaudrateInit
* Description : Initialization of UART2 Auto baud rate.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART2_AutoBaudrateInit(void)
{
SN_UART2->ABCTRL =(UART_ABTO_EN //Clear Auto Baud Time-out interrupt
| UART_ABEO_EN //Clear Auto Baud interrupt
| UART_ABCCTRL_RESTART //Restart in case of time-out
| UART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1
| UART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running)
}
/*****************************************************************************
* Function : UART2_Enable
* Description : Enable UART2
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART2_Enable(void)
{
//Enable HCLK for UART2
SN_SYS1->AHBCLKEN |= UART2_CLK_EN; //Enables clock for UART2
SN_UART2->CTRL_b.UARTEN = UART_CTRL_EN; //UART enable bit
}
/*****************************************************************************
* Function : UART2_Disable
* Description : Disable UART2
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART2_Disable(void)
{
SN_UART2->CTRL_b.UARTEN = UART_CTRL_DIS; //UART disable
//Disable HCLK for UART2
SN_SYS1->AHBCLKEN &= ~(UART2_CLK_EN); //Disable clock for UART2
}
/*****************************************************************************
* Function : UART2_InterruptEnable
* Description : Interrupt Enable
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void UART2_InterruptEnable(void)
{
SN_UART2->IE =(UART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt
| UART_THREIE_EN //Enable THRE interrupt
| UART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt
| UART_TEMTIE_EN //Enable TEMT interrupt
| UART_ABEOIE_EN //Enable Auto Baud interrupt
| UART_ABTOIE_EN); //Enable Auto Baud time-out interrupt
}

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os/hal/ports/SN32/LLD/SN32F24xB/USART/USART.h
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#ifndef __SN32F240_USART_H
#define __SN32F240_USART_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4001 6000 (USART0)
0x4005 6000 (USART1)
*/
#define USART0_CLK_EN (0x01<<16)
#define USART1_CLK_EN (0x01<<17)
#define USART0_PLKSEL_DIV1 (0x00)
#define USART0_PLKSEL_DIV2 (0x01)
#define USART0_PLKSEL_DIV4 (0x02)
#define USART0_PLKSEL_DIV8 (0x03)
#define USART0_PLKSEL_DIV16 (0x04)
#define USART1_PLKSEL_DIV1 (0x00<<4)
#define USART1_PLKSEL_DIV2 (0x01<<4)
#define USART1_PLKSEL_DIV4 (0x02<<4)
#define USART1_PLKSEL_DIV8 (0x03<<4)
#define USART1_PLKSEL_DIV16 (0x04<<4)
/**************Line Control Define******/
#define USART_CHARACTER_LEN5BIT (0x00)
#define USART_CHARACTER_LEN6BIT (0x01)
#define USART_CHARACTER_LEN7BIT (0x02)
#define USART_CHARACTER_LEN8BIT (0x03)
/***********************/
#define USART_STOPBIT_1BIT (0x0<<2)
#define USART_STOPBIT_2BIT (0x1<<2)
/***********************/
#define USART_PARITY_BIT_DISEN (0x0<<3)
#define USART_PARITY_BIT_EN (0x1<<3)
/***********************/
#define USART_PARITY_SELECTODD (0x00<<4)
#define USART_PARITY_SELECTEVEN (0x01<<4)
#define USART_PARITY_SELECTFORC1 (0x02<<4)
#define USART_PARITY_SELECTFORC0 (0x03<<4)
/***********************/
#define USART_BREAK_DISEN (0x0<<6)
#define USART_BREAK_EN (0x1<<6)
/***********************/
#define USART_DIVISOR_DISEN (0x0<<7)
#define USART_DIVISOR_EN (0x1<<7)
#define USART_OVER_SAMPLE_16 (0x0<<8)
#define USART_OVER_SAMPLE_8 (0x1<<8)
/***Baud rate pre-scaler multilier = MULVAL+1***/
#define USART_MULVAL_0 (0x0000<<4)
#define USART_MULVAL_1 (0x0001<<4)
#define USART_MULVAL_2 (0x0002<<4)
#define USART_MULVAL_3 (0x0003<<4)
#define USART_MULVAL_4 (0x0004<<4)
#define USART_MULVAL_5 (0x0005<<4)
#define USART_MULVAL_6 (0x0006<<4)
#define USART_MULVAL_7 (0x0007<<4)
#define USART_MULVAL_8 (0x0008<<4)
#define USART_MULVAL_9 (0x0009<<4)
#define USART_MULVAL_10 (0x000A<<4)
#define USART_MULVAL_11 (0x000B<<4)
#define USART_MULVAL_12 (0x000C<<4)
#define USART_MULVAL_13 (0x000D<<4)
#define USART_MULVAL_14 (0x000E<<4)
#define USART_MULVAL_15 (0x000F<<4)
/***Buad rate pre-scaler divisor value********/
#define USART_DIVADDVAL_0 (0x000)
#define USART_DIVADDVAL_1 (0x001)
#define USART_DIVADDVAL_2 (0x002)
#define USART_DIVADDVAL_3 (0x003)
#define USART_DIVADDVAL_4 (0x004)
#define USART_DIVADDVAL_5 (0x005)
#define USART_DIVADDVAL_6 (0x006)
#define USART_DIVADDVAL_7 (0x007)
#define USART_DIVADDVAL_8 (0x008)
#define USART_DIVADDVAL_9 (0x009)
#define USART_DIVADDVAL_10 (0x00A)
#define USART_DIVADDVAL_11 (0x00B)
#define USART_DIVADDVAL_12 (0x00C)
#define USART_DIVADDVAL_13 (0x00D)
#define USART_DIVADDVAL_14 (0x00E)
#define USART_DIVADDVAL_15 (0x00F)
/***USART divisor latch MSB reg[7:0]. determines the baud rate***/
/***USART divisor latch LSB reg[7:0]. determines the baud rate***/
#define USART_FIFO_ENABLE (0x01)
#define USART_RXFIFO_RESET (0x01<<1)
#define USART_TXFIFO_RESET (0x01<<2)
#define USART_RXTRIGGER_LEVEL1 (0x00<<6)
#define USART_RXTRIGGER_LEVEL4 (0x01<<6)
#define USART_RXTRIGGER_LEVEL8 (0x02<<6)
#define USART_RXTRIGGER_LEVEL14 (0x03<<6)
/***USART Interrupt Enable register***/
#define USART_TXERRIE_EN (0x01<<10) //Tx error flag INT
#define USART_ABTOIE_EN (0x01<<9) //auto-buad time out INT
#define USART_ABEOIE_EN (0x01<<8) //End of auto-buad INT
#define USART_TEMTIE_EN (0x01<<4) //Transmitter empty flag
#define USART_MSIE_EN (0x01<<3) //Modem status INT
#define USART_RLSIE_EN (0x01<<2) //Rx Receive line status(RLS) INT
#define USART_THREIE_EN (0x01<<1) //Transmitter holding register empty flag INT
#define USART_RDAIE_EN (0x01) //character receive(RDA) time-out INT
/*** USARTn_CTRL************/
#define USART_EN (0x01)
#define USART_MODE_UART (0x00<<1)
#define USART_MODE_MODEN (0x01<<1)
#define USART_MODE_SMARTCARD (0x03<<1)
#define USART_MODE_SYNCH (0x04<<1)
#define USART_MODE_RS485 (0x05<<1)
#define USART_RX_EN (0x01<<6)
#define USART_TX_EN (0x01<<7)
#define USART_CTRL_EN 1
#define USART_CTRL_DIS 0
#define USART_FIFOCTRL_RESET 1
/*** USARTn_ABCCTRL************/
#define USART_ABCCTRL_START (0x01) //START:1(Auto-baud is running), START:0(Auto-baud is not running)
#define USART_ABCCTRL_MODE0 (0x00<<1)
#define USART_ABCCTRL_MODE1 (0x01<<1)
#define USART_ABCCTRL_RESTART (0x01<<2)
#define USART_ABEO_EN (0x01<<8)
#define USART_ABTO_EN (0x01<<9)
/*** USARTn_MC(modem contro)************/
#define USART_MC_RTSCTRL (0x01<<1) //Source for modem output pin RTS
#define USART_MCCTS_EN (0x01<<6) //Auto-CTS 1:enable 0:disable
#define USART_MCRTS_EN (0x01<<7) //Auto-RTS 1:enable 0:disable
/*** USARTn_RS485(modem contro)************/
#define USART_NMM_EN (0x01) //Normal Multidrop Mode(NMM) 1:enable 0:disable
#define USART_485RX_EN (0x01<<1) //RS-485 Receiver bit 1:enalbe 0:disable
#define USART_AAD_EN (0x01<<2) //Auto address detect(AAD) bit 1:enable 0:disable
#define USART_ADC_EN (0x01<<4) //Auto Direction control bit 1:enable 0:disable
#define USART_OINV_SEL1 (0x01<<5)
#define USART_OINV_SEL0 (0x00<<5)
#define RS485_ADDRESS 40
#define RS485_DELAY_TIME 40
/*** USARTn_Synchronous Mode(modem contro)************/
#define USART_SCLK_LOW (0x0<<1) //SCLK idle low
#define USART_SCLK_HIGH (0x1<<1) //SCLK idle high
#define USART_POLAR_RISING (0x0<<2) //sample on Rising edge
#define USART_POLAR_FALLING (0x1<<2) //sample on Falling edge
/*** Line status register************/
#define USART_LS_RDR (0x01) //receiver data ready flag
#define USART_LS_OE (0x01<<1) //overrun error flag
#define USART_LS_PE (0x01<<2) //parity error flag
#define USART_LS_FE (0x01<<3) //framing error flag
#define USART_LS_BI (0x01<<4) //break interrupt flag
#define USART_LS_THRE (0x01<<5) //transmitter holding register empty flag
#define USART_LS_TEMT (0x01<<6) //transmitter empty flag
#define USART_LS_RXFE (0x01<<7) //error in RX FIFO flag
#define USART_LS_THERR (0x01<<8) //TX error flag
#define mskUSART_LS_RDR (0x01)
#define mskUSART_LS_OE (0x01<<1)
#define mskUSART_LS_PE (0x01<<2)
#define mskUSART_LS_FE (0x01<<3)
#define mskUSART_LS_BI (0x01<<4)
#define mskUSART_LS_THRE (0x01<<5)
#define mskUSART_LS_TEMT (0x01<<6)
#define mskUSART_LS_RXFE (0x01<<7)
#define mskUSART_LS_TXERR (0x01<<8)
/*** Line status register************/
#define USART_MS_DCTS (0x01)
#define USART_MS_CTS (0x01<<4)
#define mskUSART_MS_DCTS (0x01)
#define mskUSART_MS_CTS (0x01<<4)
/*** Interrupt Identification register************/
#define USART_RLS 3
#define USART_RDA 2
#define USART_CTI 6
#define USART_THRE 1
#define USART_MODEM 0
#define USART_TEMT 7
#define USART_II_STATUS 0 //the INTstatus can be determined by USARTn_II[3:1]
#define USART_II_ABEOIF (0x01<<8) //end of auto-baud interrupt flag
#define USART_II_ABTOIF (0x01<<9) //auto-baud time-out interrupt flag
#define USART_II_TXERRIF (0x01<<10) //TXERR interrupt flag
#define mskUSART_INTID_STATUS 7 //interrupt corresponding to the USARTn RX FIFO
#define mskUSART_II_STATUS (0x01)
#define mskUSART_II_ABEOIF (0x01<<8)
#define mskUSART_II_ABTOIF (0x01<<9)
#define mskUSART_II_TXERRIF (0x01<<10)
/*_____ M A C R O S ________________________________________________________*/
#define __USART0_RXFIFO_RESET (SN_USART0->FIFOCTRL_b.RXFIFORST = USART_FIFOCTRL_RESET)
#define __USART0_TXFIFO_RESET (SN_USART0->FIFOCTRL_b.TXFIFORST = USART_FIFOCTRL_RESET)
#define __USART1_RXFIFO_RESET (SN_USART1->FIFOCTRL_b.RXFIFORST = USART_FIFOCTRL_RESET)
#define __USART1_TXFIFO_RESET (SN_USART1->FIFOCTRL_b.TXFIFORST = USART_FIFOCTRL_RESET)
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern uint32_t GulNum;
extern uint8_t bUSART0_RecvFIFO[16];
extern uint32_t GulNum1;
extern uint8_t bUSART1_RecvFIFO[16];
extern volatile uint8_t bUSART0_RecvNew;
extern volatile uint8_t bUSART1_RecvNew;
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern void USART0_Init(void);
extern void USART0_SendByte(void);
extern void USART0_Enable(void);
extern void USART0_Disable(void);
extern void USART0_InterruptEnable(void);
extern void USART0_AutoBaudrateInit(void);
extern void USART1_Init(void);
extern void USART1_SendByte(void);
extern void USART1_Enable(void);
extern void USART1_Disable(void);
extern void USART1_InterruptEnable(void);
extern void USART1_AutoBaudrateInit(void);
extern void USART0_Modem_Init(void);
extern void USART0_RS485_Init(void);
extern void USART0_SyncMode_Init(void);
#endif /*__SN32F240_USART_H*/

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os/hal/ports/SN32/LLD/SN32F24xB/USART/USART0.c
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/******************** (C) COPYRIGHT 2015 SONiX *******************************
* COMPANY: SONiX
* DATE: 2015/05
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: USART0 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
* 1.1 2014/01/20 SA1 1. Modify USART0_SendByte sub function
* 1.2 2014/02/27 SA1 1. Fix typing errors.
* 1.22 2014/05/23 SA1 1. Fix USART0_Init for BR=115200
* 2.0 2015/05/29 SA1 1. Fix USART0_Init for BR=115200 & 57600 @ PCLK=12MHz
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include "USART.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint8_t bUSART0_RecvNew;
uint32_t GulNum;
uint8_t bUSART0_RecvFIFO[16];
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : UART0_IRQHandler
* Description : USART0 interrupt service routine
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void USART0_IRQHandler (void)
{
uint32_t II_Buf, LS_Buf, MS_Buf;
volatile uint32_t Null_Buf;
II_Buf = SN_USART0->II;
while ((II_Buf & mskUSART_II_STATUS) == USART_II_STATUS) //check interrupt status, the INT can be determined by USARTn_II[3:1]
{
switch ((II_Buf>>1) & mskUSART_INTID_STATUS)
{
case USART_RLS: //Receive Line Status
LS_Buf = SN_USART0->LS;
if((LS_Buf & mskUSART_LS_OE) == USART_LS_OE) //Overrun Error
{ }
if((LS_Buf & mskUSART_LS_RXFE) == USART_LS_RXFE)//RX FIFO Error
{
if((LS_Buf & mskUSART_LS_PE) == USART_LS_PE)//Parity Error
Null_Buf = SN_USART0->RB; //Clear interrupt
if((LS_Buf & mskUSART_LS_FE) == USART_LS_FE) //Framing Error
Null_Buf = SN_USART0->RB; //Clear interrupt
if((LS_Buf & mskUSART_LS_BI) == USART_LS_BI) //Break Interrupt
Null_Buf = SN_USART0->RB; //Clear interrupt
}
break;
case USART_RDA: //Receive Data Available
case USART_CTI: //Character Time-out Indicator
LS_Buf = SN_USART0->LS;
bUSART0_RecvNew = 1;
if((LS_Buf & mskUSART_LS_RDR) == USART_LS_RDR)//Receiver Data Ready
{
bUSART0_RecvFIFO[GulNum] = SN_USART0->RB;
GulNum++;
}
if(GulNum == 16)
GulNum = 0;
break;
case USART_THRE: //THRE interrupt
LS_Buf = SN_USART0->LS;
if((LS_Buf & mskUSART_LS_THRE) == USART_LS_THRE)//THRE empty
{ //SN_USART0->TH = Null_Buf; //Clear interrupt
}
break;
case USART_TEMT: //TEMT interrupt
LS_Buf = SN_USART0->LS;
if((LS_Buf & mskUSART_LS_TEMT) == USART_LS_TEMT)
{ //SN_USART0->TH = Null_Buf; //Clear interrupt
}
break;
case USART_MODEM: //Modem status
MS_Buf = SN_USART0->MS;
if((MS_Buf & mskUSART_MS_DCTS) == USART_MS_DCTS)//Delta CTS
{
if((MS_Buf & mskUSART_MS_CTS) == USART_MS_CTS)
{ //Low to High transition
}
else
{ //High to Low transition
}
}
break;
default:
break;
} //end switch ((II_Buf>>1) & mskUSART_INTID_STATUS)
II_Buf = SN_USART0->II;
//LS_Buf = SN_USART0->LS;
} //end while ((II_Buf&0x01) == mskUSART_II_STATUS)
if ((II_Buf & mskUSART_II_ABEOIF) == USART_II_ABEOIF) //Auto Baud interrupt
SN_USART0->ABCTRL |= USART_ABEO_EN;
else if((II_Buf & mskUSART_II_ABTOIF) == USART_II_ABTOIF) //Auto Baud time-out interrupt
SN_USART0->ABCTRL |= USART_ABTO_EN;
if((II_Buf & mskUSART_II_TXERRIF) == USART_II_TXERRIF)//TXERR interrupt
{
LS_Buf = SN_USART0->LS;
if ((LS_Buf & mskUSART_LS_TXERR) == USART_LS_THERR)//TX Error
SN_USART0->FIFOCTRL|= USART_TXFIFO_RESET; //TX FIFO Reset
}
}
/*****************************************************************************
* Function : USART0_Init
* Description : Initialization of USART0
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_Init (void)
{
SN_SYS1->AHBCLKEN |= USART0_CLK_EN; //Enables clock for USART0
SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV1; //USART0 PCLK = HCLK/1 = 12MHz
//SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV2; //USART0 PCLK = HCLK/2 = 6MHz
//SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV4; //USART0 PCLK = HCLK/4 = 3MHz
//SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV8; //USART0 PCLK = HCLK/8 = 1.5MHz
//SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV16; //USART0 PCLK = HCLK/16= 0.75MHz
//===Line Control===
//setting character Word length(5/6/7/8 bit)
SN_USART0->LC = (USART_CHARACTER_LEN8BIT //8bit character length.
| USART_STOPBIT_1BIT //stop bit of 1 bit
| USART_PARITY_BIT_DISEN //parity bit is disable
| USART_PARITY_SELECTODD //parity bit is odd
| USART_BREAK_DISEN //Break Transmission control disable
| USART_DIVISOR_EN); //Divisor Latch Access enable
//===Baud Rate Calculation===
//USART PCLK = 12MHz, Baud rate = 115200
SN_USART0->FD = (USART_OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5);
SN_USART0->DLM = 0;
SN_USART0->DLL = 4;
/*
//USART PCLK = 12MHz, Baud rate = 57600
SN_USART0->FD = (OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5);
SN_USART0->DLM = 0;
SN_USART0->DLL = 8;
*/
SN_USART0->LC &= ~(USART_DIVISOR_EN); //Disable divisor latch
//===Auto Baud Rate===
//USART0_Autobaudrate_Init(); //Auto buad rate initial
//===FIFO Control===
SN_USART0->FIFOCTRL =(USART_FIFO_ENABLE //Enable USART FIFOs
| USART_RXFIFO_RESET //RX FIFO Reset
| USART_TXFIFO_RESET //TX FIFO Reset
| USART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters)
//===Modem Control===
//USART0_Modem_Init(); //Initialization of USART0 Modem.
//===Smart Card Control===
//SN_USART0->SCICTRL_b.NACKDIS = 1; //NACK response disable, T=0 only (0:NACK response is enabled, 1:NACK response is inhibited)
//SN_USART0->SCICTRL_b.PROTSEL = 1; //Protocol selection (0:T=0, 1:T=1)
//SN_USART0->SCICTRL_b.SCLKEN = 1; //SCLK out enable (0:Disable, 1:Enable)
//SN_USART0->SCICTRL_b.TXRETRY = 0; //T=0 only, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signal NACK.
//SN_USART0->SCICTRL_b.XTRAGUARD = 0; //T=0 only, this field indicates the Guard time value in terms of number of bit times
//SN_USART0->SCICTRL_b.TC = 0; //TC[7:0] (Count for SCLK clock cycle when SCLKEN=1. SCLK will toggle every (TC[7:0]+1)*USARTn_PCLK cycle)
//===Synchronous Mode Control===
//USART0_SyncMode_Init(); //USART0_SyncMode_Init
//===RS485 Control===
//USART0_RS485_Init(); //USART0_RS485_Init
//===Scratch Pad===
//SN_USART0->SP = 0; //A readable, writable byte
//===Oversampling===
//SN_USART0->FD |= USART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16
//===Half-duplex===
//SN_USART0->HDEN = 1; //Half-duplex mode enable
//===Interrupt Enable===
USART0_InterruptEnable();
//===USART Control===
SN_USART0->CTRL =(USART_EN //Enable USART0
| USART_MODE_UART //USART Mode = USAT
| USART_RX_EN //Enable RX
| USART_TX_EN); //Enable TX
//===NVIC===
NVIC_EnableIRQ(USART0_IRQn); //Enable USART0 INT
}
/*****************************************************************************
* Function : USART0_SendByte
* Description : USART0 Send data
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_SendByte(void)
{
uint32_t i;
for (i=0; i<8; i++)
{
SN_USART0->TH= ('a'+i);
while ((SN_USART0->LS & 0x40) == 0);
}
}
/*****************************************************************************
* Function : USART0_AutoBaudrateInit
* Description : Initialization of USART0 Auto baud rate.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_AutoBaudrateInit(void)
{
SN_USART0->ABCTRL =(USART_ABTO_EN //Clear Auto Baud Time-out interrupt
| USART_ABEO_EN //Clear Auto Baud interrupt
| USART_ABCCTRL_RESTART //Restart in case of time-out
| USART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1
| USART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running)
}
/*****************************************************************************
* Function : USART0_Modem_Init
* Description : Initialization of USART0 Modem.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_Modem_Init(void)
{
SN_USART0->MC =(USART_MC_RTSCTRL //Source for modem output pin RTS
| USART_MCCTS_EN //CTS enable
| USART_MCRTS_EN); //RTS enable
}
/*****************************************************************************
* Function : USART0_RS485_Init
* Description : Initialization of USART0 RS-485.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_RS485_Init(void)
{
SN_USART0->RS485CTRL=(USART_NMM_EN //RS-485 Normal Multidrop Mode enable
| USART_485RX_EN //RS-485 Receiver enable, NMMEN=1 only
| USART_AAD_EN //Auto Address Detect enable
| USART_ADC_EN //Direction control enable
| USART_OINV_SEL1); //Polarity control
SN_USART0->RS485ADRMATCH = RS485_ADDRESS; //the address match value for RS-485mode
SN_USART0->RS485DLYV = RS485_DELAY_TIME; //The direction control (RTS or DTR) delay value,this time is in periods of the baud clock
}
/*****************************************************************************
* Function : USART0_SyncMode_Init
* Description : Initialization of USART0 Synchronous Mode.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_SyncMode_Init(void)
{
SN_USART0->SYNCCTRL=(USART_SCLK_HIGH //SCLK idle high
|USART_POLAR_FALLING); //sample on Falling edge
}
/*****************************************************************************
* Function : USART0_Smartcard_Init
* Description : Initialization of USART0 Smart Card.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_Smartcard_Init(void)
{
}
/*****************************************************************************
* Function : USART0_Enable
* Description : Enable USART0
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_Enable(void)
{
//Enable HCLK for USART0
SN_SYS1->AHBCLKEN |= USART0_CLK_EN; //Enables clock for USART0
SN_USART0->CTRL_b.USARTEN = USART_CTRL_EN; //USART enable bit
__USART0_RXFIFO_RESET;
__USART0_TXFIFO_RESET;
}
/*****************************************************************************
* Function : USART0_Disable
* Description : Disable USART0
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_Disable(void)
{
SN_USART0->CTRL_b.USARTEN = USART_CTRL_DIS; //USART disable
//Disable HCLK for USART0
SN_SYS1->AHBCLKEN &= ~(USART0_CLK_EN); //Disable clock for USART0
}
/*****************************************************************************
* Function : USART0_InterruptEnable
* Description : Interrupt Enable
* Input : wTxhfie- TX half empty interrupt enable. 0: Disable, 1: Enable.
wRxhfie- RX half empty interrupt enable. 0: Disable, 1: Enable.
wRxtoie- RX Time-out interrupt enable. 0: Disable, 1: Enable.
wRxovfie- RXOverflow interrupt enable. 0: Disable, 1: Enable.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_InterruptEnable(void)
{
SN_USART0->IE =(USART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt
| USART_THREIE_EN //Enable THRE interrupt
| USART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt
| USART_TEMTIE_EN //Enable TEMT interrupt
| USART_ABEOIE_EN //Enable Auto Baud interrupt
| USART_ABTOIE_EN //Enable Auto Baud time-out interrupt
| USART_TXERRIE_EN);//Enable TXERR interrupt
}

284
os/hal/ports/SN32/LLD/SN32F24xB/USART/USART1.c
View File

@ -1,284 +0,0 @@
/******************** (C) COPYRIGHT 2015 SONiX *******************************
* COMPANY: SONiX
* DATE: 2015/05
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: USART1 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
* 1.1 2014/01/20 SA1 1. Modify USART0_SendByte sub function
* 1.2 2014/02/27 SA1 1. Fix typing errors.
* 1.22 2014/05/23 SA1 1. Fix USART1_Init for BR=115200
* 2.0 2015/05/29 SA1 1. Fix USART1_Init for BR=115200 & 57600 @ PCLK=12MHz
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include "USART.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint8_t bUSART1_RecvNew;
uint32_t GulNum1;
uint8_t bUSART1_RecvFIFO[16];
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : UART1_IRQHandler
* Description : USART1 interrupt service routine
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void USART1_IRQHandler (void)
{
uint32_t II_Buf, LS_Buf;
volatile uint32_t Null_Buf;
II_Buf = SN_USART1->II;
while ((II_Buf & mskUSART_II_STATUS) == USART_II_STATUS) //check interrupt status, the INT can be determined by USARTn_II[3:1]
{
switch ((II_Buf>>1) & mskUSART_INTID_STATUS)
{
case USART_RLS: //Receive Line Status
LS_Buf = SN_USART1->LS;
if((LS_Buf & mskUSART_LS_OE) == USART_LS_OE) //Overrun Error
{ }
if((LS_Buf & mskUSART_LS_RXFE) == USART_LS_RXFE)//RX FIFO Error
{
if((LS_Buf & mskUSART_LS_PE) == USART_LS_PE)//Parity Error
Null_Buf = SN_USART1->RB; //Clear interrupt
if((LS_Buf & mskUSART_LS_FE) == USART_LS_FE) //Framing Error
Null_Buf = SN_USART1->RB; //Clear interrupt
if((LS_Buf & mskUSART_LS_BI) == USART_LS_BI) //Break Interrupt
Null_Buf = SN_USART1->RB; //Clear interrupt
}
break;
case USART_RDA: //Receive Data Available
case USART_CTI: //Character Time-out Indicator
LS_Buf = SN_USART1->LS;
bUSART1_RecvNew = 1;
if((LS_Buf & mskUSART_LS_RDR) == USART_LS_RDR)//Receiver Data Ready
{
bUSART1_RecvFIFO[GulNum1] = SN_USART1->RB;
GulNum1++;
}
if(GulNum1 == 16)
GulNum1 = 0;
break;
case USART_THRE: //THRE interrupt
LS_Buf = SN_USART1->LS;
if((LS_Buf & mskUSART_LS_THRE) == USART_LS_THRE)//THRE empty
{ //SN_USART1->TH = Null_Buf; //Clear interrupt
}
break;
case USART_TEMT: //TEMT interrupt
LS_Buf = SN_USART1->LS;
if((LS_Buf & mskUSART_LS_TEMT) == USART_LS_TEMT)
{ //SN_USART1->TH = Null_Buf; //Clear interrupt
}
break;
default:
break;
} //end switch ((II_Buf>>1) & mskUSART_INTID_STATUS)
II_Buf = SN_USART1->II;
} //end while ((II_Buf&0x01) == mskUSART_II_STATUS)
if ((II_Buf & mskUSART_II_ABEOIF) == USART_II_ABEOIF) //Auto Baud interrupt
SN_USART1->ABCTRL |= USART_ABEO_EN;
else if((II_Buf & mskUSART_II_ABTOIF) == USART_II_ABTOIF) //Auto Baud time-out interrupt
SN_USART1->ABCTRL |= USART_ABTO_EN;
if((II_Buf & mskUSART_II_TXERRIF) == USART_II_TXERRIF)//TXERR interrupt
{
LS_Buf = SN_USART1->LS;
if ((LS_Buf & mskUSART_LS_TXERR) == USART_LS_THERR)//TX Error
SN_USART1->FIFOCTRL|= USART_TXFIFO_RESET; //TX FIFO Reset
}
}
/*****************************************************************************
* Function : USART1_Init
* Description : Initialization of USART1
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART1_Init (void)
{
SN_SYS1->AHBCLKEN |= USART1_CLK_EN; //Enables clock for USART0
SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV1; //USART0 PCLK = HCLK/1 = 12MHz
//SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV2; //USART0 PCLK = HCLK/2 = 6MHz
//SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV4; //USART0 PCLK = HCLK/4 = 3MHz
//SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV8; //USART0 PCLK = HCLK/8 = 1.5MHz
//SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV16; //USART0 PCLK = HCLK/16= 0.75MHz
//===Line Control===
//setting character Word length(5/6/7/8 bit)
SN_USART1->LC = (USART_CHARACTER_LEN8BIT //8bit character length.
| USART_STOPBIT_1BIT //stop bit of 1 bit
| USART_PARITY_BIT_DISEN //parity bit is disable
| USART_PARITY_SELECTODD //parity bit is odd
| USART_BREAK_DISEN //Break Transmission control disable
| USART_DIVISOR_EN); //Divisor Latch Access enable
//===Baud Rate Calculation===
//USART PCLK = 12MHz, Baud rate = 115200
SN_USART1->FD = (USART_OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5);
SN_USART1->DLM = 0;
SN_USART1->DLL = 4;
/*
//USART PCLK = 12MHz, Baud rate = 57600
SN_USART1->FD = (OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5);
SN_USART1->DLM = 0;
SN_USART1->DLL = 8;
*/
SN_USART1->LC &= ~(USART_DIVISOR_EN); //Disable divisor latch
//===Auto Baud Rate===
//USART0_Autobaudrate_Init(); //Auto buad rate initial
//===FIFO Control===
SN_USART1->FIFOCTRL =(USART_FIFO_ENABLE //Enable USART FIFOs
| USART_RXFIFO_RESET //RX FIFO Reset
| USART_TXFIFO_RESET //TX FIFO Reset
| USART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters)
//===Scratch Pad===
//SN_USART1->SP = 0; //A readable, writable byte
//===Oversampling===
//SN_USART1->FD |= USART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16
//===Half-duplex===
//SN_USART1->HDEN = 1; //Half-duplex mode enable
//===Interrupt Enable===
USART1_InterruptEnable();
//===USART Control===
SN_USART1->CTRL =(USART_EN //Enable USART0
| USART_MODE_UART //USART Mode = USAT
| USART_RX_EN //Enable RX
| USART_TX_EN); //Enable TX
//===NVIC===
NVIC_EnableIRQ(USART1_IRQn); //Enable USART1 INT
}
/*****************************************************************************
* Function : USART1_SendByte
* Description : USART1 Send data
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART1_SendByte(void)
{
uint32_t i;
for (i=0; i<8; i++)
{
SN_USART1->TH= ('a'+i);
while ((SN_USART1->LS & 0x40) == 0);
}
}
/*****************************************************************************
* Function : USART1_AutoBaudrateInit
* Description : Initialization of USART1 Auto baud rate.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART1_AutoBaudrateInit(void)
{
SN_USART1->ABCTRL =(USART_ABTO_EN //Clear Auto Baud Time-out interrupt
| USART_ABEO_EN //Clear Auto Baud interrupt
| USART_ABCCTRL_RESTART //Restart in case of time-out
| USART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1
| USART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running)
}
/*****************************************************************************
* Function : USART1_Enable
* Description : Enable USART1
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART1_Enable(void)
{
//Enable HCLK for USART1
SN_SYS1->AHBCLKEN |= USART1_CLK_EN; //Enables clock for USART0
SN_USART1->CTRL_b.USARTEN = USART_CTRL_EN; //USART enable bit
__USART1_RXFIFO_RESET;
__USART1_TXFIFO_RESET;
}
/*****************************************************************************
* Function : USART1_Disable
* Description : Disable USART1
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART1_Disable(void)
{
SN_USART1->CTRL_b.USARTEN = USART_CTRL_DIS; //USART disable
//Disable HCLK for USART1
SN_SYS1->AHBCLKEN &= ~(USART1_CLK_EN); //Disable clock for USART0
}
/*****************************************************************************
* Function : USART1_InterruptEnable
* Description : Interrupt Enable
* Input : wTxhfie- TX half empty interrupt enable. 0: Disable, 1: Enable.
wRxhfie- RX half empty interrupt enable. 0: Disable, 1: Enable.
wRxtoie- RX Time-out interrupt enable. 0: Disable, 1: Enable.
wRxovfie- RXOverflow interrupt enable. 0: Disable, 1: Enable.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART1_InterruptEnable(void)
{
SN_USART1->IE =(USART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt
| USART_THREIE_EN //Enable THRE interrupt
| USART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt
| USART_TEMTIE_EN //Enable TEMT interrupt
| USART_ABEOIE_EN //Enable Auto Baud interrupt
| USART_ABTOIE_EN //Enable Auto Baud time-out interrupt
| USART_TXERRIE_EN);//Enable TXERR interrupt
}

289
os/hal/ports/SN32/LLD/SN32F24xB/WDT/WDT.c
View File

@ -1,155 +1,134 @@
/******************** (C) COPYRIGHT 2014 SONiX *******************************
* COMPANY: SONiX
* DATE: 2014/01
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: WDT related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
* 1.1 2014/01/20 SA1 1. Modify WDT_ReloadValue function
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F200_Def.h>
#include "WDT.h"
#include "..\..\System\SYS_con_drive.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : WDT_IRQHandler
* Description : ISR of WDT interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void WDT_IRQHandler(void)
{
SN_GPIO2->DATA_b.DATA0 = ~SN_GPIO2->DATA_b.DATA0; //P2.0 toggle
__WDT_FEED_VALUE;
__WDT_CLRINSTS; //Clear WDT interrupt flag
}
/*****************************************************************************
* Function : WDT_Init
* Description : WDT initial
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void WDT_Init(void)
{
uint32_t wRegBuf;
WDT_SelectClockSource(WDT_CLKSEL_ILRC); //clock source select
#if WDT_MODE == INTERRUPT
wRegBuf = mskWDT_WDTIE_ENABLE; //WDT as interrupt mode
#endif
#if WDT_MODE == RESET
wRegBuf = mskWDT_WDTIE_DISABLE; //WDT as reset mode
#endif
wRegBuf = wRegBuf & (~mskWDT_WDTINT); //Clear WDT interrupt flag
wRegBuf = wRegBuf | mskWDT_WDKEY;
SN_WDT->CFG = wRegBuf;
WDT_ReloadValue(61); //Set overflow time = 250ms
WDT_NvicEnable(); //Enable WDT NVIC interrupt
__WDT_ENABLE; //Enable WDT
}
/*****************************************************************************
* Function : WDT_ReloadValue
* Description : set WDT reload value
* Input : time -
0~255: overflow time set
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void WDT_ReloadValue(uint32_t time)
{
uint32_t wRegBuf;
wRegBuf = time | mskWDT_WDKEY;
SN_WDT->TC = wRegBuf;
__WDT_FEED_VALUE;
}
/***********************************************************************************
* Function : WDT_SelectClockSource
* Description : Select WDT clcok source
* Input : WDT clock source -
WDT_CLKSEL_IHRC or WDT_CLKSEL_HCLK or WDT_CLKSEL_ILRC or WDT_CLKSEL_ELS
* Output : None
* Return : None
* Note : None
***********************************************************************************/
void WDT_SelectClockSource(uint32_t src)
{
if (src == WDT_CLKSEL_IHRC)
SYS0_EnableIHRC();
else if (src == WDT_CLKSEL_ELS)
SYS0_EnableELSXtal();
SN_WDT->CLKSOURCE = mskWDT_WDKEY | src; //clock source select
}
/*****************************************************************************
* Function : WDT_NvicEnable
* Description : Enable WDT interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void WDT_NvicEnable(void)
{
NVIC_ClearPendingIRQ(WDT_IRQn);
NVIC_EnableIRQ(WDT_IRQn);
NVIC_SetPriority(WDT_IRQn, 0); // Set interrupt priority (default)
}
/*****************************************************************************
* Function : WDT_NvicDisable
* Description : Disable WDT interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void WDT_NvicDisable(void)
{
NVIC_DisableIRQ(WDT_IRQn);
}
/******************** (C) COPYRIGHT 2015 SONiX *******************************
* COMPANY: SONiX
* DATE: 2017/7
* AUTHOR: SA1
* IC: SN32F240B
* DESCRIPTION: WDT related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2017/07/07 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F200_Def.h>
#include "WDT.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : WDT_IRQHandler
* Description : ISR of WDT interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void WDT_IRQHandler(void)
{
SN_GPIO2->DATA_b.DATA0 = ~SN_GPIO2->DATA_b.DATA0; //P2.0 toggle
__WDT_FEED_VALUE;
__WDT_CLRINSTS; //Clear WDT interrupt flag
}
/*****************************************************************************
* Function : WDT_Init
* Description : WDT initial
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void WDT_Init(void)
{
uint32_t wRegBuf;
SN_SYS1->APBCP1_b.WDTPRE = 2;
#if WDT_MODE == INTERRUPT
wRegBuf = mskWDT_WDTIE_ENABLE; //WDT as interrupt mode
#endif
#if WDT_MODE == RESET
wRegBuf = mskWDT_WDTIE_DISABLE; //WDT as reset mode
#endif
wRegBuf = wRegBuf & (~mskWDT_WDTINT); //Clear WDT interrupt flag
wRegBuf = wRegBuf | mskWDT_WDKEY;
SN_WDT->CFG = wRegBuf;
WDT_ReloadValue(13); //Set overflow time = 250ms
WDT_NvicEnable(); //Enable WDT NVIC interrupt
__WDT_ENABLE; //Enable WDT
}
/*****************************************************************************
* Function : WDT_ReloadValue
* Description : set WDT reload value
* Input : time -
0~255: overflow time set
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void WDT_ReloadValue(uint32_t time)
{
uint32_t wRegBuf;
wRegBuf = time | mskWDT_WDKEY;
SN_WDT->TC = wRegBuf;
__WDT_FEED_VALUE;
}
/*****************************************************************************
* Function : WDT_NvicEnable
* Description : Enable WDT interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void WDT_NvicEnable(void)
{
NVIC_ClearPendingIRQ(WDT_IRQn);
NVIC_EnableIRQ(WDT_IRQn);
NVIC_SetPriority(WDT_IRQn, 0); // Set interrupt priority (default)
}
/*****************************************************************************
* Function : WDT_NvicDisable
* Description : Disable WDT interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void WDT_NvicDisable(void)
{
NVIC_DisableIRQ(WDT_IRQn);
}

103
os/hal/ports/SN32/LLD/SN32F24xB/WDT/WDT.h
View File

@ -1,55 +1,48 @@
#ifndef __SN32F240_WDT_H
#define __SN32F240_WDT_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define RESET 0 //WDT as Reset mode
#define INTERRUPT 1 //WDT as Interrupt mode
#define WDT_MODE INTERRUPT
//RESET_MODE : WDT as Reset mode
//Watchdog register key
#define mskWDT_WDKEY (0x5AFA<<16)
//Watchdog interrupt flag
#define mskWDT_WDTINT (1<<2)
//Watchdog interrupt enable
#define WDT_WDTIE_DISABLE 0
#define WDT_WDTIE_ENABLE 1
#define mskWDT_WDTIE_DISABLE (WDT_WDTIE_DISABLE<<1)
#define mskWDT_WDTIE_ENABLE (WDT_WDTIE_ENABLE<<1)
//Watchdog enable
#define mskWDT_WDTEN_DISABLE 0
#define mskWDT_WDTEN_ENABLE 1
//Watchdog Clock source
#define WDT_CLKSEL_IHRC 0
#define WDT_CLKSEL_HCLK 1
#define WDT_CLKSEL_ILRC 2
#define WDT_CLKSEL_ELS 3
//Watchdog Feed value
#define mskWDT_FV 0x55AA
/*_____ M A C R O S ________________________________________________________*/
//Watchdog Feed Value
#define __WDT_FEED_VALUE (SN_WDT->FEED = (mskWDT_WDKEY | mskWDT_FV))
//WDT Enable/Disable
#define __WDT_ENABLE (SN_WDT->CFG |= (mskWDT_WDKEY | mskWDT_WDTEN_ENABLE))
#define __WDT_DISABLE (SN_WDT->CFG = (mskWDT_WDKEY | (SN_WDT->CFG & ~mskWDT_WDTEN_ENABLE)))
//WDT INT status register clear
#define __WDT_CLRINSTS (SN_WDT->CFG = (mskWDT_WDKEY | (SN_WDT->CFG & ~mskWDT_WDTINT)))
/*_____ D E C L A R A T I O N S ____________________________________________*/
void WDT_Init(void);
void WDT_ReloadValue(uint32_t time);
void WDT_SelectClockSource(uint32_t src);
void WDT_NvicEnable(void);
void WDT_NvicDisable(void);
#endif /*__SN32F240_WDT_H*/
#ifndef __SN32F240B_WDT_H
#define __SN32F240B_WDT_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define RESET 0 //WDT as Reset mode
#define INTERRUPT 1 //WDT as Interrupt mode
#define WDT_MODE INTERRUPT
//RESET_MODE : WDT as Reset mode
//Watchdog register key
#define mskWDT_WDKEY (0x5AFA<<16)
//Watchdog interrupt flag
#define mskWDT_WDTINT (1<<2)
//Watchdog interrupt enable
#define WDT_WDTIE_DISABLE 0
#define WDT_WDTIE_ENABLE 1
#define mskWDT_WDTIE_DISABLE (WDT_WDTIE_DISABLE<<1)
#define mskWDT_WDTIE_ENABLE (WDT_WDTIE_ENABLE<<1)
//Watchdog enable
#define mskWDT_WDTEN_DISABLE 0
#define mskWDT_WDTEN_ENABLE 1
//Watchdog Feed value
#define mskWDT_FV 0x55AA
/*_____ M A C R O S ________________________________________________________*/
//Watchdog Feed Value
#define __WDT_FEED_VALUE (SN_WDT->FEED = (mskWDT_WDKEY | mskWDT_FV))
//WDT Enable/Disable
#define __WDT_ENABLE (SN_WDT->CFG |= (mskWDT_WDKEY | mskWDT_WDTEN_ENABLE))
#define __WDT_DISABLE (SN_WDT->CFG = (mskWDT_WDKEY | (SN_WDT->CFG & ~mskWDT_WDTEN_ENABLE)))
//WDT INT status register clear
#define __WDT_CLRINSTS (SN_WDT->CFG = (mskWDT_WDKEY | (SN_WDT->CFG & ~mskWDT_WDTINT)))
/*_____ D E C L A R A T I O N S ____________________________________________*/
void WDT_Init(void);
void WDT_ReloadValue(uint32_t time);
void WDT_NvicEnable(void);
void WDT_NvicDisable(void);
#endif /*__SN32F240B_WDT_H*/

1
os/hal/ports/SN32/SN32F240B/platform.mk
View File

@ -28,6 +28,7 @@ include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/GPIO/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/USB/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/CT/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/FLASH/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/SysTick/driver.mk
# include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/TIM/driver.mk

2
os/hal/ports/SN32/SN32F260/platform.mk
View File

@ -27,6 +27,8 @@ endif
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/GPIO/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/USB/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/CT/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/FLASH/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/SysTick/driver.mk
# include $(CHIBIOS)/os/hal/ports/SN32/LLD/TIM/driver.mk