Merge pull request #302 from KarlK90/update-risc-v-eclic-for-chibios-21.6
[RISC-V] Update RISC-V ECLIC port for chibios-21.6.x
This commit is contained in:
commit
1ba09f4d62
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@ -1,5 +1,5 @@
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/*
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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you may not use this file except in compliance with the License.
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@ -60,7 +60,7 @@
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/**
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/**
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* @brief System time counter resolution.
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* @brief System time counter resolution.
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* @note Allowed values are 16 or 32 bits.
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* @note Allowed values are 16, 32 or 64 bits.
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*/
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*/
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#if !defined(CH_CFG_ST_RESOLUTION)
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#if !defined(CH_CFG_ST_RESOLUTION)
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#define CH_CFG_ST_RESOLUTION 16
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#define CH_CFG_ST_RESOLUTION 16
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@ -725,6 +725,8 @@
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*
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*
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* @note It is invoked from within @p _thread_init() and implicitly from all
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* @note It is invoked from within @p _thread_init() and implicitly from all
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* the threads creation APIs.
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* the threads creation APIs.
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*
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* @param[in] tp pointer to the @p thread_t structure
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*/
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*/
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#define CH_CFG_THREAD_INIT_HOOK(tp) { \
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#define CH_CFG_THREAD_INIT_HOOK(tp) { \
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/* Add threads initialization code here.*/ \
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/* Add threads initialization code here.*/ \
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@ -733,6 +735,8 @@
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/**
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/**
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* @brief Threads finalization hook.
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* @brief Threads finalization hook.
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* @details User finalization code added to the @p chThdExit() API.
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* @details User finalization code added to the @p chThdExit() API.
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*
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* @param[in] tp pointer to the @p thread_t structure
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*/
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*/
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#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
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#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
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/* Add threads finalization code here.*/ \
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/* Add threads finalization code here.*/ \
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@ -741,6 +745,9 @@
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/**
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/**
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* @brief Context switch hook.
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* @brief Context switch hook.
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* @details This hook is invoked just before switching between threads.
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* @details This hook is invoked just before switching between threads.
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*
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* @param[in] ntp thread being switched in
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* @param[in] otp thread being switched out
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*/
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*/
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#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
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#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
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/* Context switch code here.*/ \
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/* Context switch code here.*/ \
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@ -1,5 +1,5 @@
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/*
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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you may not use this file except in compliance with the License.
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@ -415,6 +415,26 @@
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#define SERIAL_BUFFERS_SIZE 16
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#define SERIAL_BUFFERS_SIZE 16
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#endif
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#endif
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/*===========================================================================*/
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/* SIO driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Default bit rate.
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* @details Configuration parameter, this is the baud rate selected for the
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* default configuration.
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*/
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#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__)
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#define SIO_DEFAULT_BITRATE 38400
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#endif
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/**
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* @brief Support for thread synchronization API.
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*/
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#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__)
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#define SIO_USE_SYNCHRONIZATION TRUE
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#endif
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/*===========================================================================*/
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/*===========================================================================*/
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/* SERIAL_USB driver related setting. */
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/* SERIAL_USB driver related setting. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -0,0 +1,180 @@
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/*
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ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef HALCONF_COMMUNITY_H
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#define HALCONF_COMMUNITY_H
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/**
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* @brief Enables the community overlay.
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*/
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#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
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#define HAL_USE_COMMUNITY FALSE
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#endif
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/**
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* @brief Enables the FSMC subsystem.
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*/
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#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__)
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#define HAL_USE_FSMC FALSE
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#endif
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/**
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* @brief Enables the NAND subsystem.
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*/
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#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)
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#define HAL_USE_NAND FALSE
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#endif
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/**
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* @brief Enables the 1-wire subsystem.
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*/
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#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)
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#define HAL_USE_ONEWIRE FALSE
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#endif
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/**
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* @brief Enables the EICU subsystem.
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*/
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#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
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#define HAL_USE_EICU FALSE
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#endif
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/**
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* @brief Enables the CRC subsystem.
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*/
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#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__)
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#define HAL_USE_CRC FALSE
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#endif
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/**
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* @brief Enables the RNG subsystem.
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*/
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#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__)
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#define HAL_USE_RNG FALSE
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#endif
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/**
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* @brief Enables the EEPROM subsystem.
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*/
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#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__)
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#define HAL_USE_EEPROM FALSE
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#endif
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/**
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* @brief Enables the TIMCAP subsystem.
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*/
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#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__)
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#define HAL_USE_TIMCAP FALSE
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#endif
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/**
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* @brief Enables the COMP subsystem.
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*/
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#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__)
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#define HAL_USE_COMP FALSE
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#endif
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/**
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* @brief Enables the OPAMP subsystem.
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*/
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#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__)
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#define HAL_USE_OPAMP FALSE
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#endif
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/**
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* @brief Enables the QEI subsystem.
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*/
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#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__)
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#define HAL_USE_QEI FALSE
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#endif
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/**
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* @brief Enables the USBH subsystem.
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*/
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#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__)
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#define HAL_USE_USBH FALSE
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#endif
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/**
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* @brief Enables the USB_MSD subsystem.
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*/
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#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__)
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#define HAL_USE_USB_MSD FALSE
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#endif
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/*===========================================================================*/
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/* FSMCNAND driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.
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* @note Disabling this option saves both code and data space.
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*/
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#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
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#define NAND_USE_MUTUAL_EXCLUSION TRUE
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#endif
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/*===========================================================================*/
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/* 1-wire driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables strong pull up feature.
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* @note Disabling this option saves both code and data space.
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*/
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#define ONEWIRE_USE_STRONG_PULLUP FALSE
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/**
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* @brief Enables search ROM feature.
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* @note Disabling this option saves both code and data space.
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*/
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#define ONEWIRE_USE_SEARCH_ROM TRUE
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/*===========================================================================*/
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/* QEI driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables discard of overlow
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*/
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#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__)
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#define QEI_USE_OVERFLOW_DISCARD FALSE
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#endif
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/**
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* @brief Enables min max of overlow
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*/
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#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__)
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#define QEI_USE_OVERFLOW_MINMAX FALSE
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#endif
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/*===========================================================================*/
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/* EEProm driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables 24xx series I2C eeprom device driver.
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* @note Disabling this option saves both code and data space.
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*/
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#define EEPROM_USE_EE24XX FALSE
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/**
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* @brief Enables 25xx series SPI eeprom device driver.
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* @note Disabling this option saves both code and data space.
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*/
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#define EEPROM_USE_EE25XX FALSE
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#endif /* HALCONF_COMMUNITY_H */
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/** @} */
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@ -38,28 +38,28 @@
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/*
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/*
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* HAL driver system settings.
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* HAL driver system settings.
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*/
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*/
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#define GD32_PLLMF_VALUE 24
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#define GD32_USBFSPSC GD32_USBFSPSC_DIV2
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#define GD32_NO_INIT FALSE
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#define GD32_NO_INIT FALSE
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#define GD32_IRC8M_ENABLED TRUE
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#define GD32_IRC8M_ENABLED TRUE
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#define GD32_IRC40K_ENABLED FALSE
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#define GD32_IRC40K_ENABLED FALSE
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#define GD32_HXTAL_ENABLED TRUE
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#define GD32_HXTAL_ENABLED TRUE
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#define GD32_LXTAL_ENABLED TRUE
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#define GD32_LXTAL_ENABLED FALSE
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#define GD32_SCS GD32_SCS_PLL
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#define GD32_SCS GD32_SCS_PLL
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#define GD32_PLLSEL GD32_PLLSEL_PREDV0
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#define GD32_PLLSEL GD32_PLLSEL_PREDV0
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#define GD32_PREDV0SEL GD32_PREDV0SEL_HXTAL
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#define GD32_PREDV0SEL GD32_PREDV0SEL_HXTAL
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#define GD32_PREDV0_VALUE 2
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#define GD32_PREDV0_VALUE 2
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#define GD32_PLLMF_VALUE 18
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#define GD32_PREDV1_VALUE 2
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#define GD32_PREDV1_VALUE 2
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#define GD32_PLL1MF_VALUE 14
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#define GD32_PLL1MF_VALUE 14
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#define GD32_PLL2MF_VALUE 13
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#define GD32_PLL2MF_VALUE 13
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#define GD32_AHBPSC GD32_AHBPSC_DIV1
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#define GD32_AHBPSC GD32_AHBPSC_DIV1
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#define GD32_APB1PSC GD32_APB1PSC_DIV2
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#define GD32_APB1PSC GD32_APB1PSC_DIV2
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#define GD32_APB2PSC GD32_APB2PSC_DIV1
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#define GD32_APB2PSC GD32_APB2PSC_DIV1
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#define GD32_ADCPSC GD32_ADCPSC_DIV6
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#define GD32_ADCPSC GD32_ADCPSC_DIV16
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#define GD32_USB_CLOCK_REQUIRED TRUE
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#define GD32_USB_CLOCK_REQUIRED TRUE
|
||||||
#define GD32_USBFSPSC GD32_USBFSPSC_DIV1P5
|
|
||||||
#define GD32_I2S_CLOCK_REQUIRED FALSE
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#define GD32_I2S_CLOCK_REQUIRED FALSE
|
||||||
#define GD32_CKOUT0SEL GD32_CKOUT0SEL_NOCLOCK
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#define GD32_CKOUT0SEL GD32_CKOUT0SEL_NOCLOCK
|
||||||
#define GD32_RTCSRC GD32_RTCSRC_LXTAL
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#define GD32_RTCSRC GD32_RTCSRC_NOCLOCK
|
||||||
#define GD32_PVD_ENABLE FALSE
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#define GD32_PVD_ENABLE FALSE
|
||||||
#define GD32_LVDT GD32_LVDT_LEV0
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#define GD32_LVDT GD32_LVDT_LEV0
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||||||
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@ -104,6 +104,19 @@
|
||||||
#define GD32_CAN_CAN0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_CAN_CAN0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
#define GD32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
|
|
||||||
|
/*
|
||||||
|
* CRC driver system settings.
|
||||||
|
*/
|
||||||
|
#define GD32_CRC_USE_CRC0 FALSE
|
||||||
|
#define GD32_CRC_CRC0_DMA_IRQ_PRIORITY 14
|
||||||
|
#define GD32_CRC_CRC0_DMA_PRIORITY 2
|
||||||
|
#define GD32_CRC_CRC0_DMA_STREAM GD32_DMA_STREAM_ID(0, 0)
|
||||||
|
#define CRC_USE_DMA FALSE
|
||||||
|
#define CRCSW_USE_CRC1 FALSE
|
||||||
|
#define CRCSW_CRC32_TABLE FALSE
|
||||||
|
#define CRCSW_CRC16_TABLE FALSE
|
||||||
|
#define CRCSW_PROGRAMMABLE FALSE
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* DAC driver system settings.
|
* DAC driver system settings.
|
||||||
*/
|
*/
|
||||||
|
@ -184,10 +197,11 @@
|
||||||
#define GD32_PWM_USE_TIM2 FALSE
|
#define GD32_PWM_USE_TIM2 FALSE
|
||||||
#define GD32_PWM_USE_TIM3 FALSE
|
#define GD32_PWM_USE_TIM3 FALSE
|
||||||
#define GD32_PWM_USE_TIM4 FALSE
|
#define GD32_PWM_USE_TIM4 FALSE
|
||||||
#define GD32_PWM_TIM1_IRQ_PRIORITY 7
|
#define GD32_PWM_TIM0_IRQ_PRIORITY 10
|
||||||
#define GD32_PWM_TIM2_IRQ_PRIORITY 7
|
#define GD32_PWM_TIM1_IRQ_PRIORITY 10
|
||||||
#define GD32_PWM_TIM3_IRQ_PRIORITY 7
|
#define GD32_PWM_TIM2_IRQ_PRIORITY 10
|
||||||
#define GD32_PWM_TIM4_IRQ_PRIORITY 7
|
#define GD32_PWM_TIM3_IRQ_PRIORITY 10
|
||||||
|
#define GD32_PWM_TIM4_IRQ_PRIORITY 10
|
||||||
#define GD32_PWM_TIM0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_PWM_TIM0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
#define GD32_PWM_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_PWM_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
#define GD32_PWM_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_PWM_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
|
@ -208,11 +222,11 @@
|
||||||
#define GD32_SERIAL_USE_USART2 FALSE
|
#define GD32_SERIAL_USE_USART2 FALSE
|
||||||
#define GD32_SERIAL_USE_UART3 FALSE
|
#define GD32_SERIAL_USE_UART3 FALSE
|
||||||
#define GD32_SERIAL_USE_UART4 FALSE
|
#define GD32_SERIAL_USE_UART4 FALSE
|
||||||
#define GD32_SERIAL_USART0_PRIORITY 12
|
#define GD32_SERIAL_USART0_PRIORITY 10
|
||||||
#define GD32_SERIAL_USART1_PRIORITY 12
|
#define GD32_SERIAL_USART1_PRIORITY 10
|
||||||
#define GD32_SERIAL_USART2_PRIORITY 12
|
#define GD32_SERIAL_USART2_PRIORITY 10
|
||||||
#define GD32_SERIAL_UART3_PRIORITY 12
|
#define GD32_SERIAL_UART3_PRIORITY 10
|
||||||
#define GD32_SERIAL_UART4_PRIORITY 12
|
#define GD32_SERIAL_UART4_PRIORITY 10
|
||||||
#define GD32_SERIAL_USART0_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_SERIAL_USART0_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
#define GD32_SERIAL_USART1_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_SERIAL_USART1_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
#define GD32_SERIAL_USART2_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_SERIAL_USART2_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
|
@ -236,7 +250,7 @@
|
||||||
/*
|
/*
|
||||||
* ST driver system settings.
|
* ST driver system settings.
|
||||||
*/
|
*/
|
||||||
#define GD32_ST_IRQ_PRIORITY 9
|
#define GD32_ST_IRQ_PRIORITY 10
|
||||||
#define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
#define GD32_ST_USE_TIMER 1
|
#define GD32_ST_USE_TIMER 1
|
||||||
|
|
||||||
|
@ -248,28 +262,28 @@
|
||||||
#define GD32_UART_USE_USART2 FALSE
|
#define GD32_UART_USE_USART2 FALSE
|
||||||
#define GD32_UART_USE_UART3 FALSE
|
#define GD32_UART_USE_UART3 FALSE
|
||||||
#define GD32_UART_USE_UART4 FALSE
|
#define GD32_UART_USE_UART4 FALSE
|
||||||
#define GD32_UART_USART0_IRQ_PRIORITY 13
|
#define GD32_UART_USART0_IRQ_PRIORITY 10
|
||||||
#define GD32_UART_USART1_IRQ_PRIORITY 13
|
#define GD32_UART_USART1_IRQ_PRIORITY 10
|
||||||
#define GD32_UART_USART2_IRQ_PRIORITY 13
|
#define GD32_UART_USART2_IRQ_PRIORITY 10
|
||||||
#define GD32_UART_UART3_IRQ_PRIORITY 13
|
#define GD32_UART_UART3_IRQ_PRIORITY 10
|
||||||
#define GD32_UART_UART4_IRQ_PRIORITY 13
|
#define GD32_UART_UART4_IRQ_PRIORITY 10
|
||||||
#define GD32_UART_USART0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_UART_USART0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
#define GD32_UART_USART1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_UART_USART1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
#define GD32_UART_USART2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_UART_USART2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
#define GD32_UART_UART3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_UART_UART3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
#define GD32_UART_UART4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_UART_UART4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
#define GD32_UART_USART0_DMA_PRIORITY 0
|
#define GD32_UART_USART0_DMA_PRIORITY 3
|
||||||
#define GD32_UART_USART1_DMA_PRIORITY 0
|
#define GD32_UART_USART1_DMA_PRIORITY 3
|
||||||
#define GD32_UART_USART2_DMA_PRIORITY 0
|
#define GD32_UART_USART2_DMA_PRIORITY 3
|
||||||
#define GD32_UART_UART3_DMA_PRIORITY 0
|
#define GD32_UART_UART3_DMA_PRIORITY 3
|
||||||
#define GD32_UART_UART4_DMA_PRIORITY 0
|
#define GD32_UART_UART4_DMA_PRIORITY 3
|
||||||
#define GD32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
#define GD32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* USB driver system settings.
|
* USB driver system settings.
|
||||||
*/
|
*/
|
||||||
#define GD32_USB_USE_USBFS TRUE
|
#define GD32_USB_USE_USBFS TRUE
|
||||||
#define GD32_USB_USBFS_IRQ_PRIORITY 5
|
#define GD32_USB_USBFS_IRQ_PRIORITY 10
|
||||||
#define GD32_USB_USBFS_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
#define GD32_USB_USBFS_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||||
#define GD32_USB_USBFS_RX_FIFO_SIZE 256
|
#define GD32_USB_USBFS_RX_FIFO_SIZE 256
|
||||||
|
|
||||||
|
|
|
@ -78,7 +78,12 @@
|
||||||
/**
|
/**
|
||||||
* @brief Name of the implemented architecture.
|
* @brief Name of the implemented architecture.
|
||||||
*/
|
*/
|
||||||
#define PORT_ARCHITECTURE_NAME "RISC-V RV32IMAC"
|
#define PORT_ARCHITECTURE_NAME "RISC-V"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Name of the architecture variant.
|
||||||
|
*/
|
||||||
|
#define PORT_CORE_VARIANT_NAME "RV32IMAC"
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Compiler name and version.
|
* @brief Compiler name and version.
|
||||||
|
@ -382,7 +387,7 @@ bool _port_irq_epilogue(void);
|
||||||
/**
|
/**
|
||||||
* @brief Port-related initialization code.
|
* @brief Port-related initialization code.
|
||||||
*/
|
*/
|
||||||
static inline void port_init(void) {}
|
static inline void port_init(os_instance_t *oip){}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Returns a word encoding the current interrupts status.
|
* @brief Returns a word encoding the current interrupts status.
|
||||||
|
|
|
@ -334,7 +334,7 @@ _port_switch_from_isr:
|
||||||
jal ra, _dbg_check_lock
|
jal ra, _dbg_check_lock
|
||||||
#endif
|
#endif
|
||||||
# Calls _port_switch at the end of the function
|
# Calls _port_switch at the end of the function
|
||||||
jal ra, chSchDoReschedule
|
jal ra, chSchDoPreemption
|
||||||
#if CH_DBG_SYSTEM_STATE_CHECK
|
#if CH_DBG_SYSTEM_STATE_CHECK
|
||||||
jal ra, _dbg_check_unlock
|
jal ra, _dbg_check_unlock
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in New Issue