From 1d3f664311844306e2a9111bdc5e417b6b0028cb Mon Sep 17 00:00:00 2001 From: Stefan Kerkmann Date: Sun, 21 Mar 2021 01:23:59 +0100 Subject: [PATCH] Add renumbered dma channel definitions --- os/hal/ports/GD/GD32VF103/DMA/gd32_dma.c | 24 +++++++------- os/hal/ports/GD/GD32VF103/stm32f105xc.h | 40 ++++++++++++------------ 2 files changed, 32 insertions(+), 32 deletions(-) diff --git a/os/hal/ports/GD/GD32VF103/DMA/gd32_dma.c b/os/hal/ports/GD/GD32VF103/DMA/gd32_dma.c index 4108cfcb..3501b254 100644 --- a/os/hal/ports/GD/GD32VF103/DMA/gd32_dma.c +++ b/os/hal/ports/GD/GD32VF103/DMA/gd32_dma.c @@ -126,18 +126,18 @@ * instead: @p GD32_DMA0_STREAM0, @p GD32_DMA0_STREAM1 etc. */ const gd32_dma_stream_t _gd32_dma_streams[GD32_DMA_STREAMS] = { - {DMA0, DMA0_Channel1, GD32_DMA0_CH0_CMASK, DMA0_CH0_VARIANT, 0, 0, GD32_DMA0_CH0_NUMBER}, - {DMA0, DMA0_Channel2, GD32_DMA0_CH1_CMASK, DMA0_CH1_VARIANT, 4, 1, GD32_DMA0_CH1_NUMBER}, - {DMA0, DMA0_Channel3, GD32_DMA0_CH2_CMASK, DMA0_CH2_VARIANT, 8, 2, GD32_DMA0_CH2_NUMBER}, - {DMA0, DMA0_Channel4, GD32_DMA0_CH3_CMASK, DMA0_CH3_VARIANT, 12, 3, GD32_DMA0_CH3_NUMBER}, - {DMA0, DMA0_Channel5, GD32_DMA0_CH4_CMASK, DMA0_CH4_VARIANT, 16, 4, GD32_DMA0_CH4_NUMBER}, - {DMA0, DMA0_Channel6, GD32_DMA0_CH5_CMASK, DMA0_CH5_VARIANT, 20, 5, GD32_DMA0_CH5_NUMBER}, - {DMA0, DMA0_Channel7, GD32_DMA0_CH6_CMASK, DMA0_CH6_VARIANT, 24, 6, GD32_DMA0_CH6_NUMBER}, - {DMA1, DMA1_Channel1, GD32_DMA1_CH0_CMASK, DMA1_CH0_VARIANT, 0, 0 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH0_NUMBER}, - {DMA1, DMA1_Channel2, GD32_DMA1_CH1_CMASK, DMA1_CH1_VARIANT, 4, 1 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH1_NUMBER}, - {DMA1, DMA1_Channel3, GD32_DMA1_CH2_CMASK, DMA1_CH2_VARIANT, 8, 2 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH2_NUMBER}, - {DMA1, DMA1_Channel4, GD32_DMA1_CH3_CMASK, DMA1_CH3_VARIANT, 12, 3 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH3_NUMBER}, - {DMA1, DMA1_Channel5, GD32_DMA1_CH4_CMASK, DMA1_CH4_VARIANT, 16, 4 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH4_NUMBER}, + {DMA0, DMA0_Channel0, GD32_DMA0_CH0_CMASK, DMA0_CH0_VARIANT, 0, 0, GD32_DMA0_CH0_NUMBER}, + {DMA0, DMA0_Channel1, GD32_DMA0_CH1_CMASK, DMA0_CH1_VARIANT, 4, 1, GD32_DMA0_CH1_NUMBER}, + {DMA0, DMA0_Channel2, GD32_DMA0_CH2_CMASK, DMA0_CH2_VARIANT, 8, 2, GD32_DMA0_CH2_NUMBER}, + {DMA0, DMA0_Channel3, GD32_DMA0_CH3_CMASK, DMA0_CH3_VARIANT, 12, 3, GD32_DMA0_CH3_NUMBER}, + {DMA0, DMA0_Channel4, GD32_DMA0_CH4_CMASK, DMA0_CH4_VARIANT, 16, 4, GD32_DMA0_CH4_NUMBER}, + {DMA0, DMA0_Channel5, GD32_DMA0_CH5_CMASK, DMA0_CH5_VARIANT, 20, 5, GD32_DMA0_CH5_NUMBER}, + {DMA0, DMA0_Channel6, GD32_DMA0_CH6_CMASK, DMA0_CH6_VARIANT, 24, 6, GD32_DMA0_CH6_NUMBER}, + {DMA1, DMA1_Channel0, GD32_DMA1_CH0_CMASK, DMA1_CH0_VARIANT, 0, 0 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH0_NUMBER}, + {DMA1, DMA1_Channel1, GD32_DMA1_CH1_CMASK, DMA1_CH1_VARIANT, 4, 1 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH1_NUMBER}, + {DMA1, DMA1_Channel2, GD32_DMA1_CH2_CMASK, DMA1_CH2_VARIANT, 8, 2 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH2_NUMBER}, + {DMA1, DMA1_Channel3, GD32_DMA1_CH3_CMASK, DMA1_CH3_VARIANT, 12, 3 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH3_NUMBER}, + {DMA1, DMA1_Channel4, GD32_DMA1_CH4_CMASK, DMA1_CH4_VARIANT, 16, 4 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH4_NUMBER}, }; /*===========================================================================*/ diff --git a/os/hal/ports/GD/GD32VF103/stm32f105xc.h b/os/hal/ports/GD/GD32VF103/stm32f105xc.h index 89f8d86e..425bfc77 100644 --- a/os/hal/ports/GD/GD32VF103/stm32f105xc.h +++ b/os/hal/ports/GD/GD32VF103/stm32f105xc.h @@ -735,19 +735,19 @@ typedef struct #define SDIO_BASE (PERIPH_BASE + 0x00018000U) #define DMA0_BASE (AHBPERIPH_BASE + 0x00000000U) -#define DMA0_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U) -#define DMA0_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU) -#define DMA0_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U) -#define DMA0_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U) -#define DMA0_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) -#define DMA0_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU) -#define DMA0_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U) +#define DMA0_Channel0_BASE (AHBPERIPH_BASE + 0x00000008U) +#define DMA0_Channel1_BASE (AHBPERIPH_BASE + 0x0000001CU) +#define DMA0_Channel2_BASE (AHBPERIPH_BASE + 0x00000030U) +#define DMA0_Channel3_BASE (AHBPERIPH_BASE + 0x00000044U) +#define DMA0_Channel4_BASE (AHBPERIPH_BASE + 0x00000058U) +#define DMA0_Channel5_BASE (AHBPERIPH_BASE + 0x0000006CU) +#define DMA0_Channel6_BASE (AHBPERIPH_BASE + 0x00000080U) #define DMA1_BASE (AHBPERIPH_BASE + 0x00000400U) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U) +#define DMA1_Channel0_BASE (AHBPERIPH_BASE + 0x00000408U) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0000041CU) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x00000430U) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000444U) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000458U) #define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) //#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) @@ -824,18 +824,18 @@ typedef struct #define SDIO ((SDIO_TypeDef *)SDIO_BASE) #define DMA0 ((DMA_TypeDef *)DMA0_BASE) #define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA0_Channel0 ((DMA_Channel_TypeDef *)DMA0_Channel0_BASE) #define DMA0_Channel1 ((DMA_Channel_TypeDef *)DMA0_Channel1_BASE) #define DMA0_Channel2 ((DMA_Channel_TypeDef *)DMA0_Channel2_BASE) #define DMA0_Channel3 ((DMA_Channel_TypeDef *)DMA0_Channel3_BASE) #define DMA0_Channel4 ((DMA_Channel_TypeDef *)DMA0_Channel4_BASE) #define DMA0_Channel5 ((DMA_Channel_TypeDef *)DMA0_Channel5_BASE) #define DMA0_Channel6 ((DMA_Channel_TypeDef *)DMA0_Channel6_BASE) -#define DMA0_Channel7 ((DMA_Channel_TypeDef *)DMA0_Channel7_BASE) +#define DMA1_Channel0 ((DMA_Channel_TypeDef *)DMA1_Channel0_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) #define RCC ((RCC_TypeDef *)RCC_BASE) #define CRC ((CRC_TypeDef *)CRC_BASE) #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) @@ -14268,18 +14268,18 @@ typedef struct #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) /****************************** DMA Instances *********************************/ -#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA0_Channel1) || \ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA0_Channel0) || \ + ((INSTANCE) == DMA0_Channel1) || \ ((INSTANCE) == DMA0_Channel2) || \ ((INSTANCE) == DMA0_Channel3) || \ ((INSTANCE) == DMA0_Channel4) || \ ((INSTANCE) == DMA0_Channel5) || \ ((INSTANCE) == DMA0_Channel6) || \ - ((INSTANCE) == DMA0_Channel7) || \ + ((INSTANCE) == DMA1_Channel0) || \ ((INSTANCE) == DMA1_Channel1) || \ ((INSTANCE) == DMA1_Channel2) || \ ((INSTANCE) == DMA1_Channel3) || \ - ((INSTANCE) == DMA1_Channel4) || \ - ((INSTANCE) == DMA1_Channel5)) + ((INSTANCE) == DMA1_Channel4)) /******************************* GPIO Instances *******************************/ #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ @@ -14608,7 +14608,7 @@ typedef struct #define USB_LP_IRQn CAN1_RX0_IRQn #define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn #define USB_HP_IRQn CAN1_TX_IRQn -#define DMA1_Channel4_5_IRQn DMA1_Channel4_IRQn +#define DMA1_Channel3_5_IRQn DMA1_Channel3_IRQn #define USBWakeUp_IRQn OTG_FS_WKUP_IRQn #define CEC_IRQn OTG_FS_WKUP_IRQn #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn @@ -14629,7 +14629,7 @@ typedef struct #define USB_LP_IRQHandler CAN1_RX0_IRQHandler #define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler #define USB_HP_IRQHandler CAN1_TX_IRQHandler -#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_IRQHandler +#define DMA1_Channel3_5_IRQHandler DMA1_Channel3_IRQHandler #define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler #define CEC_IRQHandler OTG_FS_WKUP_IRQHandler #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler