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Rename I2C2 -> I2C1

This commit is contained in:
Stefan Kerkmann 2021-03-25 18:57:46 +01:00
parent ff5541e6c7
commit 22b8934b7f
7 changed files with 100 additions and 100 deletions
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70
os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.c
View File

@ -42,13 +42,13 @@
GD32_DMA_GETCHANNEL(GD32_I2C_I2C0_TX_DMA_STREAM, \
GD32_I2C0_TX_DMA_CHN)
#define I2C2_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_I2C_I2C2_RX_DMA_STREAM, \
GD32_I2C2_RX_DMA_CHN)
#define I2C1_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_I2C_I2C1_RX_DMA_STREAM, \
GD32_I2C1_RX_DMA_CHN)
#define I2C2_TX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_I2C_I2C2_TX_DMA_STREAM, \
GD32_I2C2_TX_DMA_CHN)
#define I2C1_TX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_I2C_I2C1_TX_DMA_STREAM, \
GD32_I2C1_TX_DMA_CHN)
/*===========================================================================*/
/* Driver constants. */
@ -89,8 +89,8 @@
I2CDriver I2CD1;
#endif
/** @brief I2C2 driver identifier.*/
#if GD32_I2C_USE_I2C2 || defined(__DOXYGEN__)
/** @brief I2C1 driver identifier.*/
#if GD32_I2C_USE_I2C1 || defined(__DOXYGEN__)
I2CDriver I2CD2;
#endif
@ -439,13 +439,13 @@ OSAL_IRQ_HANDLER(GD32_I2C0_ERROR_HANDLER) {
}
#endif /* GD32_I2C_USE_I2C0 */
#if GD32_I2C_USE_I2C2 || defined(__DOXYGEN__)
#if GD32_I2C_USE_I2C1 || defined(__DOXYGEN__)
/**
* @brief I2C2 event interrupt handler.
* @brief I2C1 event interrupt handler.
*
* @notapi
*/
OSAL_IRQ_HANDLER(GD32_I2C2_EVENT_HANDLER) {
OSAL_IRQ_HANDLER(GD32_I2C1_EVENT_HANDLER) {
OSAL_IRQ_PROLOGUE();
@ -455,11 +455,11 @@ OSAL_IRQ_HANDLER(GD32_I2C2_EVENT_HANDLER) {
}
/**
* @brief I2C2 error interrupt handler.
* @brief I2C1 error interrupt handler.
*
* @notapi
*/
OSAL_IRQ_HANDLER(GD32_I2C2_ERROR_HANDLER) {
OSAL_IRQ_HANDLER(GD32_I2C1_ERROR_HANDLER) {
uint16_t sr = I2CD2.i2c->STAT0;
OSAL_IRQ_PROLOGUE();
@ -469,7 +469,7 @@ OSAL_IRQ_HANDLER(GD32_I2C2_ERROR_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* GD32_I2C_USE_I2C2 */
#endif /* GD32_I2C_USE_I2C1 */
/*===========================================================================*/
/* Driver exported functions. */
@ -490,13 +490,13 @@ void i2c_lld_init(void) {
I2CD1.dmatx = NULL;
#endif /* GD32_I2C_USE_I2C0 */
#if GD32_I2C_USE_I2C2
#if GD32_I2C_USE_I2C1
i2cObjectInit(&I2CD2);
I2CD2.thread = NULL;
I2CD2.i2c = I2C2;
I2CD2.i2c = I2C1;
I2CD2.dmarx = NULL;
I2CD2.dmatx = NULL;
#endif /* GD32_I2C_USE_I2C2 */
#endif /* GD32_I2C_USE_I2C1 */
}
/**
@ -547,31 +547,31 @@ void i2c_lld_start(I2CDriver *i2cp) {
}
#endif /* GD32_I2C_USE_I2C0 */
#if GD32_I2C_USE_I2C2
#if GD32_I2C_USE_I2C1
if (&I2CD2 == i2cp) {
rccResetI2C2();
rccResetI2C1();
i2cp->dmarx = dmaStreamAllocI(GD32_I2C_I2C2_RX_DMA_STREAM,
GD32_I2C_I2C2_IRQ_PRIORITY,
i2cp->dmarx = dmaStreamAllocI(GD32_I2C_I2C1_RX_DMA_STREAM,
GD32_I2C_I2C1_IRQ_PRIORITY,
(gd32_dmaisr_t)i2c_lld_serve_rx_end_irq,
(void *)i2cp);
osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream");
i2cp->dmatx = dmaStreamAllocI(GD32_I2C_I2C2_TX_DMA_STREAM,
GD32_I2C_I2C2_IRQ_PRIORITY,
i2cp->dmatx = dmaStreamAllocI(GD32_I2C_I2C1_TX_DMA_STREAM,
GD32_I2C_I2C1_IRQ_PRIORITY,
(gd32_dmaisr_t)i2c_lld_serve_tx_end_irq,
(void *)i2cp);
osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream");
rccEnableI2C2(true);
eclicEnableVector(I2C0_EV_IRQn, GD32_I2C_I2C2_IRQ_PRIORITY, GD32_I2C_I2C2_IRQ_TRIGGER);
eclicEnableVector(I2C0_ER_IRQn, GD32_I2C_I2C2_IRQ_PRIORITY, GD32_I2C_I2C2_IRQ_TRIGGER);
rccEnableI2C1(true);
eclicEnableVector(I2C0_EV_IRQn, GD32_I2C_I2C1_IRQ_PRIORITY, GD32_I2C_I2C1_IRQ_TRIGGER);
eclicEnableVector(I2C0_ER_IRQn, GD32_I2C_I2C1_IRQ_PRIORITY, GD32_I2C_I2C1_IRQ_TRIGGER);
i2cp->rxdmamode |= GD32_DMA_CTL_CHSEL(I2C2_RX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_I2C_I2C2_DMA_PRIORITY);
i2cp->txdmamode |= GD32_DMA_CTL_CHSEL(I2C2_TX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_I2C_I2C2_DMA_PRIORITY);
i2cp->rxdmamode |= GD32_DMA_CTL_CHSEL(I2C1_RX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_I2C_I2C1_DMA_PRIORITY);
i2cp->txdmamode |= GD32_DMA_CTL_CHSEL(I2C1_TX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_I2C_I2C1_DMA_PRIORITY);
}
#endif /* GD32_I2C_USE_I2C2 */
#endif /* GD32_I2C_USE_I2C1 */
}
/* I2C registers pointed by the DMA.*/
@ -619,11 +619,11 @@ void i2c_lld_stop(I2CDriver *i2cp) {
}
#endif
#if GD32_I2C_USE_I2C2
#if GD32_I2C_USE_I2C1
if (&I2CD2 == i2cp) {
eclicDisableVector(I2C2_EV_IRQn);
eclicDisableVector(I2C2_ER_IRQn);
rccDisableI2C2();
eclicDisableVector(I2C1_EV_IRQn);
eclicDisableVector(I2C1_ER_IRQn);
rccDisableI2C1();
}
#endif
}

44
os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.h
View File

@ -58,12 +58,12 @@
#endif
/**
* @brief I2C2 driver enable switch.
* @details If set to @p TRUE the support for I2C2 is included.
* @brief I2C1 driver enable switch.
* @details If set to @p TRUE the support for I2C1 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_I2C_USE_I2C2) || defined(__DOXYGEN__)
#define GD32_I2C_USE_I2C2 FALSE
#if !defined(GD32_I2C_USE_I2C1) || defined(__DOXYGEN__)
#define GD32_I2C_USE_I2C1 FALSE
#endif
/**
@ -81,10 +81,10 @@
#endif
/**
* @brief I2C2 interrupt priority level setting.
* @brief I2C1 interrupt priority level setting.
*/
#if !defined(GD32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2C_I2C2_IRQ_PRIORITY 10
#if !defined(GD32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2C_I2C1_IRQ_PRIORITY 10
#endif
/**
@ -98,13 +98,13 @@
#endif
/**
* @brief I2C2 DMA priority (0..3|lowest..highest).
* @brief I2C1 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA streams but
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(GD32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2C_I2C2_DMA_PRIORITY 1
#if !defined(GD32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2C_I2C1_DMA_PRIORITY 1
#endif
/**
@ -118,8 +118,8 @@
#define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 6)
#define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 5)
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
#define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
/** @} */
@ -132,11 +132,11 @@
#error "I2C0 not present in the selected device"
#endif
#if GD32_I2C_USE_I2C2 && !GD32_HAS_I2C2
#error "I2C2 not present in the selected device"
#if GD32_I2C_USE_I2C1 && !GD32_HAS_I2C1
#error "I2C1 not present in the selected device"
#endif
#if !GD32_I2C_USE_I2C0 && !GD32_I2C_USE_I2C2
#if !GD32_I2C_USE_I2C0 && !GD32_I2C_USE_I2C1
#error "I2C driver activated but no I2C peripheral assigned"
#endif
@ -145,9 +145,9 @@
#error "Invalid IRQ priority assigned to I2C0"
#endif
#if GD32_I2C_USE_I2C2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_I2C_I2C2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to I2C2"
#if GD32_I2C_USE_I2C1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_I2C_I2C1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to I2C1"
#endif
#if GD32_I2C_USE_I2C0 && \
@ -155,9 +155,9 @@
#error "Invalid DMA priority assigned to I2C0"
#endif
#if GD32_I2C_USE_I2C2 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_I2C_I2C2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to I2C2"
#if GD32_I2C_USE_I2C1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_I2C_I2C1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to I2C1"
#endif
#if !defined(GD32_DMA_REQUIRED)
@ -301,7 +301,7 @@ struct I2CDriver {
extern I2CDriver I2CD1;
#endif
#if GD32_I2C_USE_I2C2
#if GD32_I2C_USE_I2C1
extern I2CDriver I2CD2;
#endif
#endif /* !defined(__DOXYGEN__) */

10
os/hal/ports/GD/GD32VF103/gd32_isr.h
View File

@ -62,10 +62,10 @@
#define GD32_I2C0_EVENT_NUMBER 50
#define GD32_I2C0_ERROR_NUMBER 51
#define GD32_I2C2_EVENT_HANDLER vector52
#define GD32_I2C2_ERROR_HANDLER vector53
#define GD32_I2C2_EVENT_NUMBER 52
#define GD32_I2C2_ERROR_NUMBER 53
#define GD32_I2C1_EVENT_HANDLER vector52
#define GD32_I2C1_ERROR_HANDLER vector53
#define GD32_I2C1_EVENT_NUMBER 52
#define GD32_I2C1_ERROR_NUMBER 53
/*
* TIM units.
@ -229,7 +229,7 @@
#define GD32_GPT_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM9_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT

12
os/hal/ports/GD/GD32VF103/gd32_rcc.h
View File

@ -466,28 +466,28 @@
#define rccResetI2C0() rccResetAPB1(RCC_APB1RSTR_I2C0RST)
/**
* @brief Enables the I2C2 peripheral clock.
* @brief Enables the I2C1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
/**
* @brief Disables the I2C2 peripheral clock.
* @brief Disables the I2C1 peripheral clock.
*
* @api
*/
#define rccDisableI2C2() rccDisableAPB1(RCC_APB1ENR_I2C2EN)
#define rccDisableI2C1() rccDisableAPB1(RCC_APB1ENR_I2C1EN)
/**
* @brief Resets the I2C2 peripheral.
* @brief Resets the I2C1 peripheral.
*
* @api
*/
#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
/** @} */
/**

8
os/hal/ports/GD/GD32VF103/gd32_registry.h
View File

@ -190,11 +190,11 @@
#endif
#if GD32_HAS_I2C_01
#define GD32_HAS_I2C2 TRUE
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
#define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
#define GD32_HAS_I2C1 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
#else
#define GD32_HAS_I2C2 FALSE
#define GD32_HAS_I2C1 FALSE
#endif
/* RTC attributes.*/

32
os/hal/ports/GD/GD32VF103/stm32_registry.h
View File

@ -140,9 +140,9 @@
#define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_HAS_I2C2 TRUE
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_I2C1 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_I2C3 FALSE
#define GD32_HAS_I2C4 FALSE
@ -353,7 +353,7 @@
#define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_HAS_I2C2 FALSE
#define GD32_HAS_I2C1 FALSE
#define GD32_HAS_I2C3 FALSE
#define GD32_HAS_I2C4 FALSE
@ -538,9 +538,9 @@
#define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_HAS_I2C2 TRUE
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_I2C1 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_I2C3 FALSE
#define GD32_HAS_I2C4 FALSE
@ -756,9 +756,9 @@
#define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_HAS_I2C2 TRUE
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_I2C1 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_I2C3 FALSE
#define GD32_HAS_I2C4 FALSE
@ -996,9 +996,9 @@
#define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_HAS_I2C2 TRUE
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_I2C1 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_I2C3 FALSE
#define GD32_HAS_I2C4 FALSE
@ -1256,9 +1256,9 @@
#define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_HAS_I2C2 TRUE
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_I2C1 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_I2C3 FALSE
#define GD32_HAS_I2C4 FALSE

24
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -715,7 +715,7 @@ typedef struct
#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
#define I2C0_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5800)
#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
#define CAN2_BASE (APB1PERIPH_BASE + 0x00006800U)
//#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
@ -803,7 +803,7 @@ typedef struct
#define UART4 ((USART_TypeDef *)UART4_BASE)
#define UART5 ((USART_TypeDef *)UART5_BASE)
#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
#define CAN2 ((CAN_TypeDef *)CAN2_BASE)
#define BKP ((BKP_TypeDef *)BKP_BASE)
@ -1583,9 +1583,9 @@ typedef struct
#define RCC_APB1RSTR_USART3RST_Pos (18U)
#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
#define RCC_APB1RSTR_I2C2RST_Pos (22U)
#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
#define RCC_APB1RSTR_I2C1RST_Pos (22U)
#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00400000 */
#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 2 reset */
#define RCC_APB1RSTR_TIM5RST_Pos (3U)
@ -1719,9 +1719,9 @@ typedef struct
#define RCC_APB1ENR_USART3EN_Pos (18U)
#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
#define RCC_APB1ENR_I2C2EN_Pos (22U)
#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
#define RCC_APB1ENR_I2C1EN_Pos (22U)
#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00400000 */
#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 2 clock enable */
#define RCC_APB1ENR_TIM5EN_Pos (3U)
@ -12350,9 +12350,9 @@ typedef struct
#define DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT_Pos (15U)
#define DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
#define DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (16U)
#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
#define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */
#define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
@ -12631,7 +12631,7 @@ typedef struct
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C0) || \
((INSTANCE) == I2C2))
((INSTANCE) == I2C1))
/******************************* SMBUS Instances ******************************/
#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE