diff --git a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/debug/OpenOCD on ICDI (prompts for .cfg target configuration) - kopie.launch b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch similarity index 100% rename from demos/TIVA/RT-TM4C123G-LAUNCHPAD/debug/OpenOCD on ICDI (prompts for .cfg target configuration) - kopie.launch rename to demos/TIVA/RT-TM4C123G-LAUNCHPAD/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch diff --git a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/debug/RT-TM4C123G-LAUNCHPAD (OpenOCD, Flash and Run) - kopie.launch b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/debug/RT-TM4C123G-LAUNCHPAD (OpenOCD, Flash and Run).launch similarity index 100% rename from demos/TIVA/RT-TM4C123G-LAUNCHPAD/debug/RT-TM4C123G-LAUNCHPAD (OpenOCD, Flash and Run) - kopie.launch rename to demos/TIVA/RT-TM4C123G-LAUNCHPAD/debug/RT-TM4C123G-LAUNCHPAD (OpenOCD, Flash and Run).launch diff --git a/os/hal/ports/TIVA/LLD/gpt_lld.c b/os/hal/ports/TIVA/LLD/gpt_lld.c index 0a619140..c1606878 100644 --- a/os/hal/ports/TIVA/LLD/gpt_lld.c +++ b/os/hal/ports/TIVA/LLD/gpt_lld.c @@ -461,84 +461,84 @@ void gpt_lld_start(GPTDriver *gptp) /* Clock activation.*/ #if TIVA_GPT_USE_GPT0 if (&GPTD1 == gptp) { - SYSCTL->RCGC.TIMER |= (1 << 0); + SYSCTL->RCGCTIMER |= (1 << 0); nvicEnableVector(TIVA_GPT0A_NUMBER, TIVA_GPT_GPT0A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_GPT1 if (&GPTD2 == gptp) { - SYSCTL->RCGC.TIMER |= (1 << 1); + SYSCTL->RCGCTIMER |= (1 << 1); nvicEnableVector(TIVA_GPT1A_NUMBER, TIVA_GPT_GPT1A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_GPT2 if (&GPTD3 == gptp) { - SYSCTL->RCGC.TIMER |= (1 << 2); + SYSCTL->RCGCTIMER |= (1 << 2); nvicEnableVector(TIVA_GPT2A_NUMBER, TIVA_GPT_GPT2A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_GPT3 if (&GPTD4 == gptp) { - SYSCTL->RCGC.TIMER |= (1 << 3); + SYSCTL->RCGCTIMER |= (1 << 3); nvicEnableVector(TIVA_GPT3A_NUMBER, TIVA_GPT_GPT3A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_GPT4 if (&GPTD5 == gptp) { - SYSCTL->RCGC.TIMER |= (1 << 4); + SYSCTL->RCGCTIMER |= (1 << 4); nvicEnableVector(TIVA_GPT4A_NUMBER, TIVA_GPT_GPT4A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_GPT5 if (&GPTD6 == gptp) { - SYSCTL->RCGC.TIMER |= (1 << 5); + SYSCTL->RCGCTIMER |= (1 << 5); nvicEnableVector(TIVA_GPT5A_NUMBER, TIVA_GPT_GPT5A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_WGPT0 if (&GPTD7 == gptp) { - SYSCTL->RCGC.WTIMER |= (1 << 0); + SYSCTL->RCGCWTIMER |= (1 << 0); nvicEnableVector(TIVA_WGPT0A_NUMBER, TIVA_GPT_WGPT0A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_WGPT1 if (&GPTD8 == gptp) { - SYSCTL->RCGC.WTIMER |= (1 << 1); + SYSCTL->RCGCWTIMER |= (1 << 1); nvicEnableVector(TIVA_WGPT1A_NUMBER, TIVA_GPT_WGPT1A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_WGPT2 if (&GPTD9 == gptp) { - SYSCTL->RCGC.WTIMER |= (1 << 2); + SYSCTL->RCGCWTIMER |= (1 << 2); nvicEnableVector(TIVA_WGPT2A_NUMBER, TIVA_GPT_WGPT2A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_WGPT3 if (&GPTD10 == gptp) { - SYSCTL->RCGC.WTIMER |= (1 << 3); + SYSCTL->RCGCWTIMER |= (1 << 3); nvicEnableVector(TIVA_WGPT3A_NUMBER, TIVA_GPT_WGPT3A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_WGPT4 if (&GPTD11 == gptp) { - SYSCTL->RCGC.WTIMER |= (1 << 4); + SYSCTL->RCGCWTIMER |= (1 << 4); nvicEnableVector(TIVA_WGPT4A_NUMBER, TIVA_GPT_WGPT4A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_WGPT5 if (&GPTD12 == gptp) { - SYSCTL->RCGC.WTIMER |= (1 << 5); + SYSCTL->RCGCWTIMER |= (1 << 5); nvicEnableVector(TIVA_WGPT5A_NUMBER, TIVA_GPT_WGPT5A_IRQ_PRIORITY); } #endif @@ -567,84 +567,84 @@ void gpt_lld_stop(GPTDriver *gptp) #if TIVA_GPT_USE_GPT0 if (&GPTD1 == gptp) { nvicDisableVector(TIVA_GPT0A_NUMBER); - SYSCTL->RCGC.TIMER &= ~(1 << 0); + SYSCTL->RCGCTIMER &= ~(1 << 0); } #endif #if TIVA_GPT_USE_GPT1 if (&GPTD2 == gptp) { nvicDisableVector(TIVA_GPT1A_NUMBER); - SYSCTL->RCGC.TIMER &= ~(1 << 1); + SYSCTL->RCGCTIMER &= ~(1 << 1); } #endif #if TIVA_GPT_USE_GPT2 if (&GPTD3 == gptp) { nvicDisableVector(TIVA_GPT2A_NUMBER); - SYSCTL->RCGC.TIMER &= ~(1 << 2); + SYSCTL->RCGCTIMER &= ~(1 << 2); } #endif #if TIVA_GPT_USE_GPT3 if (&GPTD4 == gptp) { nvicDisableVector(TIVA_GPT3A_NUMBER); - SYSCTL->RCGC.TIMER &= ~(1 << 3); + SYSCTL->RCGCTIMER &= ~(1 << 3); } #endif #if TIVA_GPT_USE_GPT4 if (&GPTD5 == gptp) { nvicDisableVector(TIVA_GPT4A_NUMBER); - SYSCTL->RCGC.TIMER &= ~(1 << 4); + SYSCTL->RCGCTIMER &= ~(1 << 4); } #endif #if TIVA_GPT_USE_GPT5 if (&GPTD6 == gptp) { nvicDisableVector(TIVA_GPT5A_NUMBER); - SYSCTL->RCGC.TIMER &= ~(1 << 5); + SYSCTL->RCGCTIMER &= ~(1 << 5); } #endif #if TIVA_GPT_USE_WGPT0 if (&GPTD7 == gptp) { nvicDisableVector(TIVA_WGPT0A_NUMBER); - SYSCTL->RCGC.WTIMER &= ~(1 << 0); + SYSCTL->RCGCWTIMER &= ~(1 << 0); } #endif #if TIVA_GPT_USE_WGPT1 if (&GPTD8 == gptp) { nvicDisableVector(TIVA_WGPT1A_NUMBER); - SYSCTL->RCGC.WTIMER &= ~(1 << 1); + SYSCTL->RCGCWTIMER &= ~(1 << 1); } #endif #if TIVA_GPT_USE_WGPT2 if (&GPTD9 == gptp) { nvicDisableVector(TIVA_WGPT2A_NUMBER); - SYSCTL->RCGC.WTIMER &= ~(1 << 2); + SYSCTL->RCGCWTIMER &= ~(1 << 2); } #endif #if TIVA_GPT_USE_WGPT3 if (&GPTD10 == gptp) { nvicDisableVector(TIVA_WGPT3A_NUMBER); - SYSCTL->RCGC.WTIMER &= ~(1 << 3); + SYSCTL->RCGCWTIMER &= ~(1 << 3); } #endif #if TIVA_GPT_USE_WGPT4 if (&GPTD11 == gptp) { nvicDisableVector(TIVA_WGPT4A_NUMBER); - SYSCTL->RCGC.WTIMER &= ~(1 << 4); + SYSCTL->RCGCWTIMER &= ~(1 << 4); } #endif #if TIVA_GPT_USE_WGPT5 if (&GPTD12 == gptp) { nvicDisableVector(TIVA_WGPT5A_NUMBER); - SYSCTL->RCGC.WTIMER &= ~(1 << 5); + SYSCTL->RCGCWTIMER &= ~(1 << 5); } #endif } diff --git a/os/hal/ports/TIVA/LLD/i2c_lld.c b/os/hal/ports/TIVA/LLD/i2c_lld.c index ecd2a470..4019a3bd 100644 --- a/os/hal/ports/TIVA/LLD/i2c_lld.c +++ b/os/hal/ports/TIVA/LLD/i2c_lld.c @@ -503,70 +503,70 @@ void i2c_lld_start(I2CDriver *i2cp) if (i2cp->state == I2C_STOP) { #if TIVA_I2C_USE_I2C0 if (&I2CD1 == i2cp) { - SYSCTL->RCGC.I2C |= (1 << 0); + SYSCTL->RCGCI2C |= (1 << 0); nvicEnableVector(TIVA_I2C0_NUMBER, TIVA_I2C_I2C0_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C0 */ #if TIVA_I2C_USE_I2C1 if (&I2CD2 == i2cp) { - SYSCTL->RCGC.I2C |= (1 << 1); + SYSCTL->RCGCI2C |= (1 << 1); nvicEnableVector(TIVA_I2C1_NUMBER, TIVA_I2C_I2C1_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C1 */ #if TIVA_I2C_USE_I2C2 if (&I2CD3 == i2cp) { - SYSCTL->RCGC.I2C |= (1 << 2); + SYSCTL->RCGCI2C |= (1 << 2); nvicEnableVector(TIVA_I2C2_NUMBER, TIVA_I2C_I2C2_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C2 */ #if TIVA_I2C_USE_I2C3 if (&I2CD4 == i2cp) { - SYSCTL->RCGC.I2C |= (1 << 3); + SYSCTL->RCGCI2C |= (1 << 3); nvicEnableVector(TIVA_I2C3_NUMBER, TIVA_I2C_I2C3_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C3 */ #if TIVA_I2C_USE_I2C4 if (&I2CD5 == i2cp) { - SYSCTL->RCGC.I2C |= (1 << 4); + SYSCTL->RCGCI2C |= (1 << 4); nvicEnableVector(TIVA_I2C4_NUMBER, TIVA_I2C_I2C4_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C4 */ #if TIVA_I2C_USE_I2C5 if (&I2CD6 == i2cp) { - SYSCTL->RCGC.I2C |= (1 << 5); + SYSCTL->RCGCI2C |= (1 << 5); nvicEnableVector(TIVA_I2C5_NUMBER, TIVA_I2C_I2C5_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C5 */ #if TIVA_I2C_USE_I2C6 if (&I2CD7 == i2cp) { - SYSCTL->RCGC.I2C |= (1 << 6); + SYSCTL->RCGCI2C |= (1 << 6); nvicEnableVector(TIVA_I2C6_NUMBER, TIVA_I2C_I2C6_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C6 */ #if TIVA_I2C_USE_I2C7 if (&I2CD8 == i2cp) { - SYSCTL->RCGC.I2C |= (1 << 7); + SYSCTL->RCGCI2C |= (1 << 7); nvicEnableVector(TIVA_I2C7_NUMBER, TIVA_I2C_I2C7_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C7 */ #if TIVA_I2C_USE_I2C8 if (&I2CD9 == i2cp) { - SYSCTL->RCGC.I2C |= (1 << 8); + SYSCTL->RCGCI2C |= (1 << 8); nvicEnableVector(TIVA_I2C8_NUMBER, TIVA_I2C_I2C8_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C7 */ #if TIVA_I2C_USE_I2C9 if (&I2CD10 == i2cp) { - SYSCTL->RCGC.I2C |= (1 << 9); + SYSCTL->RCGCI2C |= (1 << 9); nvicEnableVector(TIVA_I2C9_NUMBER, TIVA_I2C_I2C9_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C7 */ @@ -595,70 +595,70 @@ void i2c_lld_stop(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C0 if (&I2CD1 == i2cp) { - SYSCTL->RCGC.I2C &= ~(1 << 0); + SYSCTL->RCGCI2C &= ~(1 << 0); nvicDisableVector(TIVA_I2C0_NUMBER); } #endif /* TIVA_I2C_USE_I2C0 */ #if TIVA_I2C_USE_I2C1 if (&I2CD2 == i2cp) { - SYSCTL->RCGC.I2C &= ~(1 << 1); + SYSCTL->RCGCI2C &= ~(1 << 1); nvicDisableVector(TIVA_I2C1_NUMBER); } #endif /* TIVA_I2C_USE_I2C1 */ #if TIVA_I2C_USE_I2C2 if (&I2CD3 == i2cp) { - SYSCTL->RCGC.I2C &= ~(1 << 2); + SYSCTL->RCGCI2C &= ~(1 << 2); nvicDisableVector(TIVA_I2C2_NUMBER); } #endif /* TIVA_I2C_USE_I2C2 */ #if TIVA_I2C_USE_I2C3 if (&I2CD4 == i2cp) { - SYSCTL->RCGC.I2C &= ~(1 << 3); + SYSCTL->RCGCI2C &= ~(1 << 3); nvicDisableVector(TIVA_I2C3_NUMBER); } #endif /* TIVA_I2C_USE_I2C3 */ #if TIVA_I2C_USE_I2C4 if (&I2CD5 == i2cp) { - SYSCTL->RCGC.I2C &= ~(1 << 4); + SYSCTL->RCGCI2C &= ~(1 << 4); nvicDisableVector(TIVA_I2C4_NUMBER); } #endif /* TIVA_I2C_USE_I2C4 */ #if TIVA_I2C_USE_I2C5 if (&I2CD6 == i2cp) { - SYSCTL->RCGC.I2C &= ~(1 << 5); + SYSCTL->RCGCI2C &= ~(1 << 5); nvicDisableVector(TIVA_I2C5_NUMBER); } #endif /* TIVA_I2C_USE_I2C5 */ #if TIVA_I2C_USE_I2C6 if (&I2CD7 == i2cp) { - SYSCTL->RCGC.I2C &= ~(1 << 6); + SYSCTL->RCGCI2C &= ~(1 << 6); nvicDisableVector(TIVA_I2C6_NUMBER); } #endif /* TIVA_I2C_USE_I2C6 */ #if TIVA_I2C_USE_I2C7 if (&I2CD8 == i2cp) { - SYSCTL->RCGC.I2C &= ~(1 << 7); + SYSCTL->RCGCI2C &= ~(1 << 7); nvicDisableVector(TIVA_I2C7_NUMBER); } #endif /* TIVA_I2C_USE_I2C7 */ #if TIVA_I2C_USE_I2C8 if (&I2CD9 == i2cp) { - SYSCTL->RCGC.I2C &= ~(1 << 8); + SYSCTL->RCGCI2C &= ~(1 << 8); nvicDisableVector(TIVA_I2C8_NUMBER); } #endif /* TIVA_I2C_USE_I2C8 */ #if TIVA_I2C_USE_I2C9 if (&I2CD10 == i2cp) { - SYSCTL->RCGC.I2C &= ~(1 << 9); + SYSCTL->RCGCI2C &= ~(1 << 9); nvicDisableVector(TIVA_I2C9_NUMBER); } #endif /* TIVA_I2C_USE_I2C9 */ diff --git a/os/hal/ports/TIVA/LLD/pwm_lld.c b/os/hal/ports/TIVA/LLD/pwm_lld.c index f4635abe..fdde9f8b 100644 --- a/os/hal/ports/TIVA/LLD/pwm_lld.c +++ b/os/hal/ports/TIVA/LLD/pwm_lld.c @@ -340,7 +340,7 @@ void pwm_lld_start(PWMDriver *pwmp) /* Clock activation.*/ #if TIVA_PWM_USE_PWM0 if (&PWMD1 == pwmp) { - SYSCTL->RCGC.PWM |= (1 << 0); + SYSCTL->RCGCPWM |= (1 << 0); nvicEnableVector(TIVA_PWM0FAULT_NUMBER, TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY); nvicEnableVector(TIVA_PWM0GEN0_NUMBER, TIVA_PWM_PWM0_0_IRQ_PRIORITY); @@ -352,7 +352,7 @@ void pwm_lld_start(PWMDriver *pwmp) #if TIVA_PWM_USE_PWM1 if (&PWMD2 == pwmp) { - SYSCTL->RCGC.PWM |= (1 << 1); + SYSCTL->RCGCPWM |= (1 << 1); nvicEnableVector(TIVA_PWM1FAULT_NUMBER, TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY); nvicEnableVector(TIVA_PWM1GEN0_NUMBER, TIVA_PWM_PWM1_0_IRQ_PRIORITY); @@ -427,7 +427,7 @@ void pwm_lld_stop(PWMDriver *pwmp) nvicDisableVector(TIVA_PWM0GEN1_NUMBER); nvicDisableVector(TIVA_PWM0GEN2_NUMBER); nvicDisableVector(TIVA_PWM0GEN3_NUMBER); - SYSCTL->RCGC.PWM &= ~(1 << 0); + SYSCTL->RCGCPWM &= ~(1 << 0); } #endif @@ -438,7 +438,7 @@ void pwm_lld_stop(PWMDriver *pwmp) nvicDisableVector(TIVA_PWM1GEN1_NUMBER); nvicDisableVector(TIVA_PWM1GEN2_NUMBER); nvicDisableVector(TIVA_PWM1GEN3_NUMBER); - SYSCTL->RCGC.PWM &= ~(1 << 1); + SYSCTL->RCGCPWM &= ~(1 << 1); } #endif } diff --git a/os/hal/ports/TIVA/TM4C123x/tm4c123x.h b/os/hal/ports/TIVA/TM4C123x/tm4c123x.h index 539bb668..925c1de7 100644 --- a/os/hal/ports/TIVA/TM4C123x/tm4c123x.h +++ b/os/hal/ports/TIVA/TM4C123x/tm4c123x.h @@ -523,74 +523,173 @@ typedef struct */ typedef struct { - uint32_t WD; /**< Watchdog Timer */ - uint32_t TIMER; /**< General-Purpose Timer */ - uint32_t GPIO; /**< General-Purpose Input/Output */ - uint32_t DMA; /**< Micro Direct Memory Access */ - uint32_t _RESERVED0[1]; /**< Reserved */ - uint32_t HIB; /**< Hibernation */ - uint32_t UART; /**< Universal Asynchronous - Receiver/Transmitter */ - uint32_t SSI; /**< Synchronous Serial Interface */ - uint32_t I2C; /**< Inter-Integrated Circuit */ - uint32_t _RESERVED1[1]; /**< Reserved */ - uint32_t USB; /**< Universal Serial Bus */ - uint32_t _RESERVED2[2]; /**< Reserved */ - uint32_t CAN; /**< Controller Area Network */ - uint32_t ADC; /**< Analog-to-Digital Converter */ - uint32_t ACMP; /**< Analog Comparator */ - uint32_t PWM; /**< Pulse Width Modulator */ - uint32_t QEI; /**< Quadrature Encoder Interface */ - uint32_t _RESERVED3[4]; /**< Reserved */ - uint32_t EEPROM; /**< EEPROM */ - uint32_t WTIMER; /**< Wide General-Purpose Timer */ - uint32_t _RESERVED4[40]; /**< Reserved */ -} SYSCTL_PERIPH_t; - -typedef struct -{ - __I uint32_t DID[2]; /**< Device Identification 0 and 1 */ - __I uint32_t _RESERVED0[10]; /**< Reserved */ + __I uint32_t DID0; /**< Device Identification 0 */ + __I uint32_t DID1; /**< Device Identification 1 */ + __I uint32_t RESERVED0[10]; /**< Reserved */ __IO uint32_t PBORCTL; /**< Brown-Out Reset Control */ - __I uint32_t _RESERVED1[7]; /**< Reserved */ + __I uint32_t RESERVED1[7]; /**< Reserved */ __I uint32_t RIS; /**< Raw Interrupt Status */ __IO uint32_t IMC; /**< Interrupt Mask Control */ __IO uint32_t MISC; /**< Interrupt Status and Clear */ __IO uint32_t RESC; /**< Reset Cause */ __IO uint32_t RCC; /**< Run-Mode Clock Configuration */ - __I uint32_t _RESERVED2[2]; /**< Reserved */ + __I uint32_t RESERVED2[2]; /**< Reserved */ __IO uint32_t GPIOHBCTL; /**< GPIO High-Performance Bus Control */ __IO uint32_t RCC2; /**< Run-Mode Clock Configuration 2 */ - __I uint32_t _RESERVED3[2]; /**< Reserved */ + __I uint32_t RESERVED3[2]; /**< Reserved */ __IO uint32_t MOSCCTL; /**< Main Oscillator Control */ - __I uint32_t _RESERVED4[49]; /**< Reserved */ + __I uint32_t RESERVED4[49]; /**< Reserved */ __IO uint32_t DSLPCLKCFG; /**< Deep Sleep Clock Configuration */ - __I uint32_t _RESERVED5[1]; /**< Reserved */ + __I uint32_t RESERVED5[1]; /**< Reserved */ __I uint32_t SYSPROP; /**< System Properties */ __IO uint32_t PIOSCCAL; /**< PIOSC Calibration */ __I uint32_t PIOSCSTAT; /**< PIOSC Statistics */ - __I uint32_t _RESERVED6[2]; /**< Reserved */ - __I uint32_t PLLFREQ[2]; /**< PLL Frequency 0 and 1 */ + __I uint32_t RESERVED6[2]; /**< Reserved */ + __I uint32_t PLLFREQ0; /**< PLL Frequency 0 */ + __I uint32_t PLLFREQ1; /**< PLL Frequency 1 */ __I uint32_t PLLSTAT; /**< PLL Frequency Status */ - __I uint32_t _RESERVED7[7]; /**< Reserved */ + __I uint32_t RESERVED7[7]; /**< Reserved */ __IO uint32_t SLPPWRCFG; /**< Sleep Power Configuration */ __IO uint32_t DSLPPWRCFG; /**< Deep-Sleep Power Configuration */ - __I uint32_t _RESERVED8[9]; /**< Reserved */ + __I uint32_t RESERVED8[9]; /**< Reserved */ __IO uint32_t LDOSPCTL; /**< LDO Sleep Power Control */ __I uint32_t LDOSPCAL; /**< LDO Sleep Power Calibration */ __IO uint32_t LDODPCTL; /**< LDO Deep-Sleep Power Control */ __I uint32_t LDODPCAL; /**< LDO Deep-Sleep Power Calibration */ - __I uint32_t _RESERVED9[2]; /**< Reserved */ + __I uint32_t RESERVED9[2]; /**< Reserved */ __I uint32_t SDPMST; /**< Sleep/Deep-Sleep Power Mode Status */ - __I uint32_t _RESERVED10[76];/**< Reserved */ - __I SYSCTL_PERIPH_t PP; /**< Peripheral Present */ - __I uint32_t _RESERVED11[64];/**< Reserved */ - __IO SYSCTL_PERIPH_t SR; /**< Software Reset */ - __IO SYSCTL_PERIPH_t RCGC; /**< Run Mode Clock Gating Control */ - __IO SYSCTL_PERIPH_t SCGC; /**< Sleep Mode Clock Gating Control */ - __IO SYSCTL_PERIPH_t DCGC; /**< Deep-Sleep Mode Clock Gating Control */ - __I uint32_t _RESERVED12[64];/**< Reserved */ - __IO SYSCTL_PERIPH_t PR; /**< Peripheral Ready */ + __I uint32_t RESERVED10[76]; /**< Reserved */ + __I uint32_t PPWD; /**< WDT Peripheral Present */ + __I uint32_t PPTIMER; /**< GPT Peripheral Present */ + __I uint32_t PPGPIO; /**< GPIO Peripheral Present */ + __I uint32_t PPDMA; /**< UDMA Peripheral Present */ + __I uint32_t RESERVED11[1]; /**< Reserved */ + __I uint32_t PPHIB; /**< HIB Peripheral Present */ + __I uint32_t PPUART; /**< UART Peripheral Present */ + __I uint32_t PPSSI; /**< SSI Peripheral Present */ + __I uint32_t PPI2C; /**< I2C Peripheral Present */ + __I uint32_t RESERVED12[1]; /**< Reserved */ + __I uint32_t PPUSB; /**< USB Peripheral Present */ + __I uint32_t RESERVED13[2]; /**< Reserved */ + __I uint32_t PPCAN; /**< CAN Peripheral Present */ + __I uint32_t PPADC; /**< ADC Peripheral Present */ + __I uint32_t PPACMP; /**< ACMP Peripheral Present */ + __I uint32_t PPPWM; /**< PWM Peripheral Present */ + __I uint32_t PPQEI; /**< QEI Peripheral Present */ + __I uint32_t RESERVED14[4]; /**< Reserved */ + __I uint32_t PPEEPROM; /**< EEPROM Peripheral Present */ + __I uint32_t PPWTIMER; /**< Wide GPT Peripheral Present */ + __I uint32_t RESERVED15[104];/**< Reserved */ + __IO uint32_t SRWD; /**< WDT Software Reset */ + __IO uint32_t SRTIMER; /**< GPT Software Reset */ + __IO uint32_t SRGPIO; /**< GPIO Software Reset */ + __IO uint32_t SRDMA; /**< UDMA Software Reset */ + __I uint32_t RESERVED16[1]; /**< Reserved */ + __IO uint32_t SRHIB; /**< HIB Software Reset */ + __IO uint32_t SRUART; /**< UART Software Reset */ + __IO uint32_t SRSSI; /**< SSI Software Reset */ + __IO uint32_t SRI2C; /**< I2C Software Reset */ + __I uint32_t RESERVED17[1]; /**< Reserved */ + __IO uint32_t SRUSB; /**< USB Software Reset */ + __I uint32_t RESERVED18[2]; /**< Reserved */ + __IO uint32_t SRCAN; /**< CAN Software Reset */ + __IO uint32_t SRADC; /**< ADC Software Reset */ + __IO uint32_t SRACMP; /**< ACMP Software Reset */ + __IO uint32_t SRPWM; /**< PWM Software Reset */ + __IO uint32_t SRQEI; /**< QEI Software Reset */ + __I uint32_t RESERVED19[4]; /**< Reserved */ + __IO uint32_t SREEPROM; /**< EEPROM Software Reset */ + __IO uint32_t SRWTIMER; /**< Wide GPT Software Reset */ + __I uint32_t RESERVED20[40]; /**< Reserved */ + __IO uint32_t RCGCWD; /**< WDT Run Mode Clock Gating Control */ + __IO uint32_t RCGCTIMER; /**< GPT Run Mode Clock Gating Control */ + __IO uint32_t RCGCGPIO; /**< GPIO Run Mode Clock Gating Control */ + __IO uint32_t RCGCDMA; /**< UDMA Run Mode Clock Gating Control */ + __I uint32_t RESERVED21[1]; /**< Reserved */ + __IO uint32_t RCGCHIB; /**< HIB Run Mode Clock Gating Control */ + __IO uint32_t RCGCUART; /**< UART Run Mode Control */ + __IO uint32_t RCGCSSI; /**< SSI Run Mode Clock Gating Control */ + __IO uint32_t RCGCI2C; /**< I2C Run Mode Clock Gating Control */ + __I uint32_t RESERVED22[1]; /**< Reserved */ + __IO uint32_t RCGCUSB; /**< USB Run Mode Clock Gating Control */ + __I uint32_t RESERVED23[2]; /**< Reserved */ + __IO uint32_t RCGCCAN; /**< CAN Run Mode Clock Gating Control */ + __IO uint32_t RCGCADC; /**< ADC Run Mode Clock Gating Control */ + __IO uint32_t RCGCACMP; /**< ACMP Run Mode Clock Gating Control */ + __IO uint32_t RCGCPWM; /**< PWM Run Mode Clock Gating Control */ + __IO uint32_t RCGCQEI; /**< QEI Run Mode Clock Gating Control */ + __I uint32_t RESERVED24[4]; /**< Reserved */ + __IO uint32_t RCGCEEPROM; /**< EEPROM Run Mode Clock Gating Control */ + __IO uint32_t RCGCWTIMER; /**< Wide GPT Run Mode Clock Gating Control */ + __I uint32_t RESERVED25[40]; /**< Reserved */ + __IO uint32_t SCGCWD; /**< WDT Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCTIMER; /**< GPT Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCGPIO; /**< GPIO Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCDMA; /**< UDMA Sleep Mode Clock Gating Control */ + __I uint32_t RESERVED26[1]; /**< Reserved */ + __IO uint32_t SCGCHIB; /**< HIB Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCUART; /**< UART Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCSSI; /**< SSI Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCI2C; /**< I2C Sleep Mode Clock Gating Control */ + __I uint32_t RESERVED27[1]; /**< Reserved */ + __IO uint32_t SCGCUSB; /**< USB Sleep Mode Clock Gating Control */ + __I uint32_t RESERVED28[2]; /**< Reserved */ + __IO uint32_t SCGCCAN; /**< CAN Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCADC; /**< ADC Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCACMP; /**< ACMP Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCPWM; /**< PWM Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCQEI; /**< QEI Sleep Mode Clock Gating Control */ + __I uint32_t RESERVED29[4]; /**< Reserved */ + __IO uint32_t SCGCEEPROM; /**< EEPROM Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCWTIMER; /**< Wide GPT Sleep Mode Clock Gating Control*/ + __I uint32_t RESERVED30[40]; /**< Reserved */ + __IO uint32_t DCGCWD; /**< WDT Deep-Sleep Mode Clock Gating Control*/ + __IO uint32_t DCGCTIMER; /**< GPT Deep-Sleep Mode Clock Gating Control*/ + __IO uint32_t DCGCGPIO; /**< GPIO Deep-Sleep Mode Clock Gating + Control */ + __IO uint32_t DCGCDMA; /**< UDMA Deep-Sleep Mode Clock Gating + Control */ + __I uint32_t RESERVED31[1]; /**< Reserved */ + __IO uint32_t DCGCHIB; /**< HIB Deep-Sleep Mode Clock Gating Control*/ + __IO uint32_t DCGCUART; /**< UART Deep-Sleep Mode Clock Gating + Control */ + __IO uint32_t DCGCSSI; /**< SSI Deep-Sleep Mode Clock Gating Control*/ + __IO uint32_t DCGCI2C; /**< I2C Deep-Sleep Mode Clock Gating Control*/ + __I uint32_t RESERVED32[1]; /**< Reserved */ + __IO uint32_t DCGCUSB; /**< USB Deep-Sleep Mode Clock Gating Control*/ + __I uint32_t RESERVED33[2]; /**< Reserved */ + __IO uint32_t DCGCCAN; /**< CAN Deep-Sleep Mode Clock Gating Control*/ + __IO uint32_t DCGCADC; /**< ADC Deep-Sleep Mode Clock Gating Control*/ + __IO uint32_t DCGCACMP; /**< ACMP Deep-Sleep Mode Clock Gating + Control */ + __IO uint32_t DCGCPWM; /**< PWM Deep-Sleep Mode Clock Gating Control*/ + __IO uint32_t DCGCQEI; /**< QEI Deep-Sleep Mode Clock Gating Control*/ + __I uint32_t RESERVED34[4]; /**< Reserved */ + __IO uint32_t DCGCEEPROM; /**< EEPROM Deep-Sleep Mode Clock Gating + Control */ + __IO uint32_t DCGCWTIMER; /**< Wide GPT Deep-Sleep Mode Clock Gating + Control */ + __I uint32_t RESERVED35[104];/**< Reserved */ + __IO uint32_t PRWD; /**< WDT Peripheral Ready */ + __IO uint32_t PRTIMER; /**< GPT Peripheral Ready */ + __IO uint32_t PRGPIO; /**< GPIO Peripheral Ready */ + __IO uint32_t PRDMA; /**< UDMA Peripheral Ready */ + __I uint32_t RESERVED36[1]; /**< Reserved */ + __IO uint32_t PRHIB; /**< HIB Peripheral Ready */ + __IO uint32_t PRUART; /**< UART Peripheral Ready */ + __IO uint32_t PRSSI; /**< SSI Peripheral Ready */ + __IO uint32_t PRI2C; /**< I2C Peripheral Ready */ + __I uint32_t RESERVED37[1]; /**< Reserved */ + __IO uint32_t PRUSB; /**< USB Peripheral Ready */ + __I uint32_t RESERVED38[2]; /**< Reserved */ + __IO uint32_t PRCAN; /**< CAN Peripheral Ready */ + __IO uint32_t PRADC; /**< ADC Peripheral Ready */ + __IO uint32_t PRACMP; /**< ACMP Peripheral Ready */ + __IO uint32_t PRPWM; /**< PWM Peripheral Ready */ + __IO uint32_t PRQEI; /**< QEI Peripheral Ready */ + __I uint32_t RESERVED39[4]; /**< Reserved */ + __IO uint32_t PREEPROM; /**< EEPROM Peripheral Ready */ + __IO uint32_t PRWTIMER; /**< Wide GPT Peripheral Ready */ } SYSCTL_TypeDef; /** diff --git a/testhal/TIVA/TM4C123x/GPT/debug/OpenOCD on ICDI (prompts for .cfg target configuration) - kopie.launch b/testhal/TIVA/TM4C123x/GPT/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch similarity index 100% rename from testhal/TIVA/TM4C123x/GPT/debug/OpenOCD on ICDI (prompts for .cfg target configuration) - kopie.launch rename to testhal/TIVA/TM4C123x/GPT/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch diff --git a/testhal/TIVA/TM4C123x/GPT/debug/TM4C123x-GPT (OpenOCD, Flash and Run) - kopie.launch b/testhal/TIVA/TM4C123x/GPT/debug/TM4C123x-GPT (OpenOCD, Flash and Run).launch similarity index 100% rename from testhal/TIVA/TM4C123x/GPT/debug/TM4C123x-GPT (OpenOCD, Flash and Run) - kopie.launch rename to testhal/TIVA/TM4C123x/GPT/debug/TM4C123x-GPT (OpenOCD, Flash and Run).launch diff --git a/testhal/TIVA/TM4C123x/I2C/debug/OpenOCD on ICDI (prompts for .cfg target configuration) - kopie.launch b/testhal/TIVA/TM4C123x/I2C/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch similarity index 100% rename from testhal/TIVA/TM4C123x/I2C/debug/OpenOCD on ICDI (prompts for .cfg target configuration) - kopie.launch rename to testhal/TIVA/TM4C123x/I2C/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch diff --git a/testhal/TIVA/TM4C123x/I2C/debug/TM4C123x-I2C (OpenOCD, Flash and Run) - kopie.launch b/testhal/TIVA/TM4C123x/I2C/debug/TM4C123x-I2C (OpenOCD, Flash and Run).launch similarity index 100% rename from testhal/TIVA/TM4C123x/I2C/debug/TM4C123x-I2C (OpenOCD, Flash and Run) - kopie.launch rename to testhal/TIVA/TM4C123x/I2C/debug/TM4C123x-I2C (OpenOCD, Flash and Run).launch diff --git a/testhal/TIVA/TM4C123x/PWM/debug/OpenOCD on ICDI (prompts for .cfg target configuration) - kopie.launch b/testhal/TIVA/TM4C123x/PWM/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch similarity index 100% rename from testhal/TIVA/TM4C123x/PWM/debug/OpenOCD on ICDI (prompts for .cfg target configuration) - kopie.launch rename to testhal/TIVA/TM4C123x/PWM/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch diff --git a/testhal/TIVA/TM4C123x/PWM/debug/TM4C123x-PWM (OpenOCD, Flash and Run) - kopie.launch b/testhal/TIVA/TM4C123x/PWM/debug/TM4C123x-PWM (OpenOCD, Flash and Run).launch similarity index 100% rename from testhal/TIVA/TM4C123x/PWM/debug/TM4C123x-PWM (OpenOCD, Flash and Run) - kopie.launch rename to testhal/TIVA/TM4C123x/PWM/debug/TM4C123x-PWM (OpenOCD, Flash and Run).launch