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Rename OTG device registers

This commit is contained in:
Stefan Kerkmann 2021-03-24 19:21:53 +01:00
parent 3839d682cf
commit 27551a2282
4 changed files with 220 additions and 236 deletions
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257
os/hal/ports/GD/GD32VF103/OTG/gd32_otg.h
View File

@ -54,13 +54,13 @@ typedef struct {
volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint
control register. */
volatile uint32_t resvd4;
volatile uint32_t DIEPINT; /**< @brief Device IN endpoint interrupt
volatile uint32_t DIEPINTF; /**< @brief Device IN endpoint interrupt
register. */
volatile uint32_t resvdC;
volatile uint32_t DIEPTSIZ; /**< @brief Device IN endpoint transfer size
volatile uint32_t DIEPLEN; /**< @brief Device IN endpoint transfer size
register. */
volatile uint32_t resvd14;
volatile uint32_t DTXFSTS; /**< @brief Device IN endpoint transmit FIFO
volatile uint32_t DIEPTFSTAT; /**< @brief Device IN endpoint transmit FIFO
status register. */
volatile uint32_t resvd1C;
} gd32_usbfs_in_ep_t;
@ -72,10 +72,10 @@ typedef struct {
volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint
control register. */
volatile uint32_t resvd4;
volatile uint32_t DOEPINT; /**< @brief Device OUT endpoint interrupt
volatile uint32_t DOEPINTF; /**< @brief Device OUT endpoint interrupt
register. */
volatile uint32_t resvdC;
volatile uint32_t DOEPTSIZ; /**< @brief Device OUT endpoint transfer
volatile uint32_t DOEPLEN; /**< @brief Device OUT endpoint transfer
size register. */
volatile uint32_t resvd14;
volatile uint32_t resvd18;
@ -131,24 +131,24 @@ typedef struct {
volatile uint32_t resvd700[64];
volatile uint32_t DCFG; /**< @brief Device configuration register. */
volatile uint32_t DCTL; /**< @brief Device control register. */
volatile uint32_t DSTS; /**< @brief Device status register. */
volatile uint32_t DSTAT; /**< @brief Device status register. */
volatile uint32_t resvd80C;
volatile uint32_t DIEPMSK; /**< @brief Device IN endpoint common
volatile uint32_t DIEPINTFEN; /**< @brief Device IN endpoint common
interrupt mask register. */
volatile uint32_t DOEPMSK; /**< @brief Device OUT endpoint common
volatile uint32_t DOEPINTFEN; /**< @brief Device OUT endpoint common
interrupt mask register. */
volatile uint32_t DAINT; /**< @brief Device all endpoints interrupt
volatile uint32_t DAEPINT; /**< @brief Device all endpoints interrupt
register. */
volatile uint32_t DAINTMSK; /**< @brief Device all endpoints interrupt
volatile uint32_t DAEPINTEN; /**< @brief Device all endpoints interrupt
mask register. */
volatile uint32_t resvd820;
volatile uint32_t resvd824;
volatile uint32_t DVBUSDIS; /**< @brief Device VBUS discharge time
volatile uint32_t DVBUSDT; /**< @brief Device VBUS discharge time
register. */
volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS pulsing time
volatile uint32_t DVBUSPT; /**< @brief Device VBUS pulsing time
register. */
volatile uint32_t resvd830;
volatile uint32_t DIEPEMPMSK; /**< @brief Device IN endpoint FIFO empty
volatile uint32_t DIEPFEINTEN; /**< @brief Device IN endpoint FIFO empty
interrupt mask register. */
volatile uint32_t resvd838;
volatile uint32_t resvd83C;
@ -158,7 +158,7 @@ typedef struct {
gd32_usbfs_in_ep_t ie[16]; /**< @brief Input endpoints. */
gd32_usbfs_out_ep_t oe[16]; /**< @brief Output endpoints. */
volatile uint32_t resvdD00[64];
volatile uint32_t PCGCCTL; /**< @brief Power and clock gating control
volatile uint32_t PWRCLKCTL; /**< @brief Power and clock gating control
register. */
volatile uint32_t resvdE04[127];
volatile uint32_t FIFO[16][1024];
@ -591,19 +591,16 @@ typedef struct {
* @name DCFG register bit definitions
* @{
*/
#define DCFG_PFIVL_MASK (3U<<11) /**< Periodic frame interval
#define DCFG_EOPFT_MASK (3U<<11) /**< Periodic frame interval
mask. */
#define DCFG_PFIVL(n) ((n)<<11) /**< Periodic frame interval
#define DCFG_EOPFT(n) ((n)<<11) /**< Periodic frame interval
value. */
#define DCFG_DAD_MASK (0x7FU<<4) /**< Device address mask. */
#define DCFG_DAD(n) ((n)<<4) /**< Device address value. */
#define DCFG_NZLSOHSK (1U<<2) /**< Non-Zero-Length status
#define DCFG_DAR_MASK (0x7FU<<4) /**< Device address mask. */
#define DCFG_DAR(n) ((n)<<4) /**< Device address value. */
#define DCFG_NZLSOH (1U<<2) /**< Non-Zero-Length status
OUT handshake. */
#define DCFG_DSPD_MASK (3U<<0) /**< Device speed mask. */
#define DCFG_DSPD_HS (0U<<0) /**< High speed (USB 2.0). */
#define DCFG_DSPD_HS_FS (1U<<0) /**< High speed (USB 2.0) in FS
mode. */
#define DCFG_DSPD_FS11 (3U<<0) /**< Full speed (USB 1.1
#define DCFG_DS_MASK (3U<<0) /**< Device speed mask. */
#define DCFG_DS_FS11 (3U<<0) /**< Full speed (USB 1.1
transceiver clock is 48
MHz). */
/** @} */
@ -612,122 +609,118 @@ typedef struct {
* @name DCTL register bit definitions
* @{
*/
#define DCTL_POPRGDNE (1U<<11) /**< Power-on programming done. */
#define DCTL_POIF (1U<<11) /**< Power-on programming done. */
#define DCTL_CGONAK (1U<<10) /**< Clear global OUT NAK. */
#define DCTL_SGONAK (1U<<9) /**< Set global OUT NAK. */
#define DCTL_CGINAK (1U<<8) /**< Clear global non-periodic
IN NAK. */
#define DCTL_SGINAK (1U<<7) /**< Set global non-periodic
IN NAK. */
#define DCTL_TCTL_MASK (7U<<4) /**< Test control mask. */
#define DCTL_TCTL(n) ((n)<<4 /**< Test control value. */
#define DCTL_GONSTS (1U<<3) /**< Global OUT NAK status. */
#define DCTL_GINSTS (1U<<2) /**< Global non-periodic IN
#define DCTL_GONS (1U<<3) /**< Global OUT NAK status. */
#define DCTL_GINS (1U<<2) /**< Global non-periodic IN
NAK status. */
#define DCTL_SDIS (1U<<1) /**< Soft disconnect. */
#define DCTL_RWUSIG (1U<<0) /**< Remote wakeup signaling. */
#define DCTL_SD (1U<<1) /**< Soft disconnect. */
#define DCTL_RWKUP (1U<<0) /**< Remote wakeup signaling. */
/** @} */
/**
* @name DSTS register bit definitions
* @name DSTAT register bit definitions
* @{
*/
#define DSTS_FNSOF_MASK (0x3FFU<<8) /**< Frame number of the received
#define DSTAT_FNRSOF_MASK (0x3FFU<<8) /**< Frame number of the received
SOF mask. */
#define DSTS_FNSOF(n) ((n)<<8) /**< Frame number of the received
#define DSTAT_FNRSOF(n) ((n)<<8) /**< Frame number of the received
SOF value. */
#define DSTS_FNSOF_ODD (1U<<8) /**< Frame parity of the received
#define DSTAT_FNRSOF_ODD (1U<<8) /**< Frame parity of the received
SOF value. */
#define DSTS_EERR (1U<<3) /**< Erratic error. */
#define DSTS_ENUMSPD_MASK (3U<<1) /**< Enumerated speed mask. */
#define DSTS_ENUMSPD_FS_48 (3U<<1) /**< Full speed (PHY clock is
#define DSTAT_ES_MASK (3U<<1) /**< Enumerated speed mask. */
#define DSTAT_ES_FS_48 (3U<<1) /**< Full speed (PHY clock is
running at 48 MHz). */
#define DSTS_ENUMSPD_HS_480 (0U<<1) /**< High speed. */
#define DSTS_SUSPSTS (1U<<0) /**< Suspend status. */
#define DSTAT_SPST (1U<<0) /**< Suspend status. */
/** @} */
/**
* @name DIEPMSK register bit definitions
* @name DIEPINTFEN register bit definitions
* @{
*/
#define DIEPMSK_TXFEM (1U<<6) /**< Transmit FIFO empty mask. */
#define DIEPMSK_INEPNEM (1U<<6) /**< IN endpoint NAK effective
mask. */
#define DIEPMSK_ITTXFEMSK (1U<<4) /**< IN token received when
#define DIEPINTFEN_IEPNEEN (1U<<6) /**< Transmit FIFO empty mask. */
#define DIEPINTFEN_EPTXFUDEN (1U<<4) /**< IN token received when
TxFIFO empty mask. */
#define DIEPMSK_TOCM (1U<<3) /**< Timeout condition mask. */
#define DIEPMSK_EPDM (1U<<1) /**< Endpoint disabled
#define DIEPINTFEN_CITOEN (1U<<3) /**< Timeout condition mask. */
#define DIEPINTFEN_EPDISEN (1U<<1) /**< Endpoint disabled
interrupt mask. */
#define DIEPMSK_XFRCM (1U<<0) /**< Transfer completed
#define DIEPINTFEN_TFEN (1U<<0) /**< Transfer completed
interrupt mask. */
/** @} */
/**
* @name DOEPMSK register bit definitions
* @name DOEPINTFEN register bit definitions
* @{
*/
#define DOEPMSK_OTEPDM (1U<<4) /**< OUT token received when
#define DOEPINTFEN_BTBSTPEN (1U<<6) /**< Back-to-back Setup packets
interrupt enable bit */
#define DOEPINTFEN_EPRXFOVREN (1U<<4) /**< OUT token received when
endpoint disabled mask. */
#define DOEPMSK_STUPM (1U<<3) /**< SETUP phase done mask. */
#define DOEPMSK_EPDM (1U<<1) /**< Endpoint disabled
#define DOEPINTFEN_STPFEN (1U<<3) /**< SETUP phase done mask. */
#define DOEPINTFEN_EPDISEN (1U<<1) /**< Endpoint disabled
interrupt mask. */
#define DOEPMSK_XFRCM (1U<<0) /**< Transfer completed
#define DOEPINTFEN_TFEN (1U<<0) /**< Transfer completed
interrupt mask. */
/** @} */
/**
* @name DAINT register bit definitions
* @name DAEPINT register bit definitions
* @{
*/
#define DAINT_OEPINT_MASK (0xFFFFU<<16)/**< OUT endpoint interrupt
#define DAEPINT_OEPITB_MASK (0xFFFFU<<16)/**< OUT endpoint interrupt
bits mask. */
#define DAINT_OEPINT(n) ((n)<<16) /**< OUT endpoint interrupt
#define DAEPINT_OEPITB(n) ((n)<<16) /**< OUT endpoint interrupt
bits value. */
#define DAINT_IEPINT_MASK (0xFFFFU<<0)/**< IN endpoint interrupt
#define DAEPINT_IEPITB_MASK (0xFFFFU<<0)/**< IN endpoint interrupt
bits mask. */
#define DAINT_IEPINT(n) ((n)<<0) /**< IN endpoint interrupt
#define DAEPINT_IEPITB(n) ((n)<<0) /**< IN endpoint interrupt
bits value. */
/** @} */
/**
* @name DAINTMSK register bit definitions
* @name DAEPINTEN register bit definitions
* @{
*/
#define DAINTMSK_OEPM_MASK (0xFFFFU<<16)/**< OUT EP interrupt mask
#define DAEPINTEN_OEPIE_MASK (0xFFFFU<<16)/**< OUT EP interrupt mask
bits mask. */
#define DAINTMSK_OEPM(n) (1U<<(16+(n)))/**< OUT EP interrupt mask
#define DAEPINTEN_OEPIE(n) (1U<<(16+(n)))/**< OUT EP interrupt mask
bits value. */
#define DAINTMSK_IEPM_MASK (0xFFFFU<<0)/**< IN EP interrupt mask
#define DAEPINTEN_IEPIE_MASK (0xFFFFU<<0)/**< IN EP interrupt mask
bits mask. */
#define DAINTMSK_IEPM(n) (1U<<(n)) /**< IN EP interrupt mask
#define DAEPINTEN_IEPIE(n) (1U<<(n)) /**< IN EP interrupt mask
bits value. */
/** @} */
/**
* @name DVBUSDIS register bit definitions
* @name DVBUSDT register bit definitions
* @{
*/
#define DVBUSDIS_VBUSDT_MASK (0xFFFFU<<0)/**< Device VBUS discharge
#define DVBUSDT_DVBUSDT_MASK (0xFFFFU<<0)/**< Device VBUS discharge
time mask. */
#define DVBUSDIS_VBUSDT(n) ((n)<<0) /**< Device VBUS discharge
#define DVBUSDT_DVBUSDT(n) ((n)<<0) /**< Device VBUS discharge
time value. */
/** @} */
/**
* @name DVBUSPULSE register bit definitions
* @name DVBUSPT register bit definitions
* @{
*/
#define DVBUSPULSE_DVBUSP_MASK (0xFFFU<<0) /**< Device VBUSpulsing time
#define DVBUSPT_DVBUSPT_MASK (0xFFFU<<0) /**< Device VBUSpulsing time
mask. */
#define DVBUSPULSE_DVBUSP(n) ((n)<<0) /**< Device VBUS pulsing time
#define DVBUSPT_DVBUSPT(n) ((n)<<0) /**< Device VBUS pulsing time
value. */
/** @} */
/**
* @name DIEPEMPMSK register bit definitions
* @name DIEPFEINTEN register bit definitions
* @{
*/
#define DIEPEMPMSK_INEPTXFEM(n) (1U<<(n)) /**< IN EP Tx FIFO empty
#define DIEPFEINTEN_IEPTXFEIE(n) (1U<<(n)) /**< IN EP Tx FIFO empty
interrupt mask bit. */
/** @} */
@ -735,62 +728,62 @@ typedef struct {
* @name DIEPCTL register bit definitions
* @{
*/
#define DIEPCTL_EPENA (1U<<31) /**< Endpoint enable. */
#define DIEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */
#define DIEPCTL_EPEN (1U<<31) /**< Endpoint enable. */
#define DIEPCTL_EPD (1U<<30) /**< Endpoint disable. */
#define DIEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */
#define DIEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */
#define DIEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */
#define DIEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */
#define DIEPCTL_SEVENFRM (1U<<28) /**< Set even frame. */
#define DIEPCTL_SNAK (1U<<27) /**< Set NAK. */
#define DIEPCTL_CNAK (1U<<26) /**< Clear NAK. */
#define DIEPCTL_TXFNUM_MASK (15U<<22) /**< TxFIFO number mask. */
#define DIEPCTL_TXFNUM(n) ((n)<<22) /**< TxFIFO number value. */
#define DIEPCTL_STALL (1U<<21) /**< STALL handshake. */
#define DIEPCTL_SNPM (1U<<20) /**< Snoop mode. */
#define DIEPCTL_EPTYP_MASK (3<<18) /**< Endpoint type mask. */
#define DIEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */
#define DIEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */
#define DIEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */
#define DIEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */
#define DIEPCTL_NAKSTS (1U<<17) /**< NAK status. */
#define DIEPCTL_EPTYPE_MASK (3<<18) /**< Endpoint type mask. */
#define DIEPCTL_EPTYPE_CTRL (0U<<18) /**< Control. */
#define DIEPCTL_EPTYPE_ISO (1U<<18) /**< Isochronous. */
#define DIEPCTL_EPTYPE_BULK (2U<<18) /**< Bulk. */
#define DIEPCTL_EPTYPE_INTR (3U<<18) /**< Interrupt. */
#define DIEPCTL_NAKS (1U<<17) /**< NAK status. */
#define DIEPCTL_EONUM (1U<<16) /**< Even/odd frame. */
#define DIEPCTL_DPID (1U<<16) /**< Endpoint data PID. */
#define DIEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */
#define DIEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */
#define DIEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */
#define DIEPCTL_EPACT (1U<<15) /**< USB active endpoint. */
#define DIEPCTL_MPL_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */
#define DIEPCTL_MPL(n) ((n)<<0) /**< Maximum Packet size value. */
/** @} */
/**
* @name DIEPINT register bit definitions
* @name DIEPINTF register bit definitions
* @{
*/
#define DIEPINT_TXFE (1U<<7) /**< Transmit FIFO empty. */
#define DIEPINT_INEPNE (1U<<6) /**< IN endpoint NAK effective. */
#define DIEPINT_ITTXFE (1U<<4) /**< IN Token received when
#define DIEPINTFF_TXFE (1U<<7) /**< Transmit FIFO empty. */
#define DIEPINTFF_IEPNE (1U<<6) /**< IN endpoint NAK effective. */
#define DIEPINTFF_EPTXFUD (1U<<4) /**< IN Token received when
TxFIFO is empty. */
#define DIEPINT_TOC (1U<<3) /**< Timeout condition. */
#define DIEPINT_EPDISD (1U<<1) /**< Endpoint disabled
#define DIEPINTFF_CITO (1U<<3) /**< Timeout condition. */
#define DIEPINTFF_EPDIS (1U<<1) /**< Endpoint disabled
interrupt. */
#define DIEPINT_XFRC (1U<<0) /**< Transfer completed. */
#define DIEPINTFF_TF (1U<<0) /**< Transfer completed. */
/** @} */
/**
* @name DIEPTSIZ register bit definitions
* @name DIEPLEN register bit definitions
* @{
*/
#define DIEPTSIZ_MCNT_MASK (3U<<29) /**< Multi count mask. */
#define DIEPTSIZ_MCNT(n) ((n)<<29) /**< Multi count value. */
#define DIEPTSIZ_PKTCNT_MASK (0x3FF<<19) /**< Packet count mask. */
#define DIEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */
#define DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */
#define DIEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */
#define DIEPLEN_MCPF_MASK (3U<<29) /**< Multi count mask. */
#define DIEPLEN_MCPF(n) ((n)<<29) /**< Multi count value. */
#define DIEPLEN_PCNT_MASK (0x3FF<<19) /**< Packet count mask. */
#define DIEPLEN_PCNT(n) ((n)<<19) /**< Packet count value. */
#define DIEPLEN_TLEN_MASK (0x7FFFFU<<0)/**< Transfer size mask. */
#define DIEPLEN_TLEN(n) ((n)<<0) /**< Transfer size value. */
/** @} */
/**
* @name DTXFSTS register bit definitions.
* @name DIEPTFSTAT register bit definitions.
* @{
*/
#define DTXFSTS_INEPTFSAV_MASK (0xFFFF<<0) /**< IN endpoint TxFIFO space
#define DIEPTFSTAT_IEPTFS_MASK (0xFFFF<<0) /**< IN endpoint TxFIFO space
available. */
/** @} */
@ -798,66 +791,64 @@ typedef struct {
* @name DOEPCTL register bit definitions.
* @{
*/
#define DOEPCTL_EPENA (1U<<31) /**< Endpoint enable. */
#define DOEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */
#define DOEPCTL_EPEN (1U<<31) /**< Endpoint enable. */
#define DOEPCTL_EPD (1U<<30) /**< Endpoint disable. */
#define DOEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */
#define DOEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */
#define DOEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */
#define DOEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */
#define DOEPCTL_SEVENFRM (1U<<28) /**< Set even frame. */
#define DOEPCTL_SNAK (1U<<27) /**< Set NAK. */
#define DOEPCTL_CNAK (1U<<26) /**< Clear NAK. */
#define DOEPCTL_STALL (1U<<21) /**< STALL handshake. */
#define DOEPCTL_SNPM (1U<<20) /**< Snoop mode. */
#define DOEPCTL_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */
#define DOEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */
#define DOEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */
#define DOEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */
#define DOEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */
#define DOEPCTL_NAKSTS (1U<<17) /**< NAK status. */
#define DOEPCTL_EONUM (1U<<16) /**< Even/odd frame. */
#define DOEPCTL_SNOOP (1U<<20) /**< Snoop mode. */
#define DOEPCTL_EPTYPE_MASK (3U<<18) /**< Endpoint type mask. */
#define DOEPCTL_EPTYPE_CTRL (0U<<18) /**< Control. */
#define DOEPCTL_EPTYPE_ISO (1U<<18) /**< Isochronous. */
#define DOEPCTL_EPTYPE_BULK (2U<<18) /**< Bulk. */
#define DOEPCTL_EPTYPE_INTR (3U<<18) /**< Interrupt. */
#define DOEPCTL_NAKS (1U<<17) /**< NAK status. */
#define DOEPCTL_EOFRM (1U<<16) /**< Even/odd frame. */
#define DOEPCTL_DPID (1U<<16) /**< Endpoint data PID. */
#define DOEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */
#define DOEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */
#define DOEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */
#define DOEPCTL_EPACT (1U<<15) /**< USB active endpoint. */
#define DOEPCTL_MPL_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */
#define DOEPCTL_MPL(n) ((n)<<0) /**< Maximum Packet size value. */
/** @} */
/**
* @name DOEPINT register bit definitions
* @name DOEPINTF register bit definitions
* @{
*/
#define DOEPINT_SETUP_RCVD (1U<<15) /**< SETUP packet received. */
#define DOEPINT_B2BSTUP (1U<<6) /**< Back-to-back SETUP packets
#define DOEPINTF_BTBSTP (1U<<6) /**< Back-to-back SETUP packets
received. */
#define DOEPINT_OTEPDIS (1U<<4) /**< OUT token received when
#define DOEPINTF_EPRXFOVR (1U<<4) /**< OUT token received when
endpoint disabled. */
#define DOEPINT_STUP (1U<<3) /**< SETUP phase done. */
#define DOEPINT_EPDISD (1U<<1) /**< Endpoint disabled
#define DOEPINTF_STPF (1U<<3) /**< SETUP phase done. */
#define DOEPINTF_EPDIS (1U<<1) /**< Endpoint disabled
interrupt. */
#define DOEPINT_XFRC (1U<<0) /**< Transfer completed
#define DOEPINTF_TF (1U<<0) /**< Transfer completed
interrupt. */
/** @} */
/**
* @name DOEPTSIZ register bit definitions
* @name DOEPLEN register bit definitions
* @{
*/
#define DOEPTSIZ_RXDPID_MASK (3U<<29) /**< Received data PID mask. */
#define DOEPTSIZ_RXDPID(n) ((n)<<29) /**< Received data PID value. */
#define DOEPTSIZ_STUPCNT_MASK (3U<<29) /**< SETUP packet count mask. */
#define DOEPTSIZ_STUPCNT(n) ((n)<<29) /**< SETUP packet count value. */
#define DOEPTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */
#define DOEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */
#define DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */
#define DOEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */
#define DOEPLEN_RXDPID_MASK (3U<<29) /**< Received data PID mask. */
#define DOEPLEN_RXDPID(n) ((n)<<29) /**< Received data PID value. */
#define DOEPLEN_STPCNT_MASK (3U<<29) /**< SETUP packet count mask. */
#define DOEPLEN_STPCNT(n) ((n)<<29) /**< SETUP packet count value. */
#define DOEPLEN_PCNT_MASK (0x3FFU<<19)/**< Packet count mask. */
#define DOEPLEN_PCNT(n) ((n)<<19) /**< Packet count value. */
#define DOEPLEN_TLEN_MASK (0x7FFFFU<<0)/**< Transfer size mask. */
#define DOEPLEN_TLEN(n) ((n)<<0) /**< Transfer size value. */
/** @} */
/**
* @name PCGCCTL register bit definitions
* @name PWRCLKCTL register bit definitions
* @{
*/
#define PCGCCTL_PHYSUSP (1U<<4) /**< PHY Suspended. */
#define PCGCCTL_GATEHCLK (1U<<1) /**< Gate HCLK. */
#define PCGCCTL_STPPCLK (1U<<0) /**< Stop PCLK. */
#define PWRCLKCTL_SHCLK (1U<<1) /**< Gate HCLK. */
#define PWRCLKCTL_SUCLK (1U<<0) /**< Stop PCLK. */
/** @} */
#define USBFS_ADDR 0x50000000

167
os/hal/ports/GD/GD32VF103/OTG/hal_usb_lld.c
View File

@ -125,18 +125,18 @@ static void otg_disable_ep(USBDriver *usbp) {
for (i = 0; i <= usbp->otgparams->num_endpoints; i++) {
if ((otgp->ie[i].DIEPCTL & DIEPCTL_EPENA) != 0U) {
otgp->ie[i].DIEPCTL |= DIEPCTL_EPDIS;
if ((otgp->ie[i].DIEPCTL & DIEPCTL_EPEN) != 0U) {
otgp->ie[i].DIEPCTL |= DIEPCTL_EPD;
}
if ((otgp->oe[i].DOEPCTL & DIEPCTL_EPENA) != 0U) {
otgp->oe[i].DOEPCTL |= DIEPCTL_EPDIS;
if ((otgp->oe[i].DOEPCTL & DIEPCTL_EPEN) != 0U) {
otgp->oe[i].DOEPCTL |= DIEPCTL_EPD;
}
otgp->ie[i].DIEPINT = 0xFFFFFFFF;
otgp->oe[i].DOEPINT = 0xFFFFFFFF;
otgp->ie[i].DIEPINTF = 0xFFFFFFFF;
otgp->oe[i].DOEPINTF = 0xFFFFFFFF;
}
otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0);
otgp->DAEPINTEN = DAEPINTEN_OEPIE(0) | DAEPINTEN_IEPIE(0);
}
static void otg_rxfifo_flush(USBDriver *usbp) {
@ -302,7 +302,7 @@ static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
/* Transaction end condition.*/
if (usbp->epc[ep]->in_state->txcnt >= usbp->epc[ep]->in_state->txsize) {
#if 1
usbp->otg->DIEPEMPMSK &= ~DIEPEMPMSK_INEPTXFEM(ep);
usbp->otg->DIEPFEINTEN &= ~DIEPFEINTEN_IEPTXFEIE(ep);
#endif
return true;
}
@ -314,7 +314,7 @@ static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
/* Checks if in the TXFIFO there is enough space to accommodate the
next packet.*/
if (((usbp->otg->ie[ep].DTXFSTS & DTXFSTS_INEPTFSAV_MASK) * 4) < n)
if (((usbp->otg->ie[ep].DIEPTFSTAT & DIEPTFSTAT_IEPTFS_MASK) * 4) < n)
return false;
// TODO Enable again or keep brute force?
@ -345,14 +345,14 @@ static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
*/
static void otg_epin_handler(USBDriver *usbp, usbep_t ep) {
gd32_usbfs_t *otgp = usbp->otg;
uint32_t epint = otgp->ie[ep].DIEPINT;
uint32_t epint = otgp->ie[ep].DIEPINTF;
otgp->ie[ep].DIEPINT = epint;
otgp->ie[ep].DIEPINTF = epint;
if (epint & DIEPINT_TOC) {
if (epint & DIEPINTFF_CITO) {
/* Timeouts not handled yet, not sure how to handle.*/
}
if ((epint & DIEPINT_XFRC) && (otgp->DIEPMSK & DIEPMSK_XFRCM)) {
if ((epint & DIEPINTFF_TF) && (otgp->DIEPINTFEN & DIEPINTFEN_TFEN)) {
/* Transmit transfer complete.*/
USBInEndpointState *isp = usbp->epc[ep]->in_state;
@ -371,8 +371,8 @@ static void otg_epin_handler(USBDriver *usbp, usbep_t ep) {
_usb_isr_invoke_in_cb(usbp, ep);
}
}
if ((epint & DIEPINT_TXFE) &&
(otgp->DIEPEMPMSK & DIEPEMPMSK_INEPTXFEM(ep))) {
if ((epint & DIEPINTFF_TXFE) &&
(otgp->DIEPFEINTEN & DIEPFEINTEN_IEPTXFEIE(ep))) {
/* TX FIFO empty or emptying.*/
otg_txfifo_handler(usbp, ep);
}
@ -388,18 +388,18 @@ static void otg_epin_handler(USBDriver *usbp, usbep_t ep) {
*/
static void otg_epout_handler(USBDriver *usbp, usbep_t ep) {
gd32_usbfs_t *otgp = usbp->otg;
uint32_t epint = otgp->oe[ep].DOEPINT;
uint32_t epint = otgp->oe[ep].DOEPINTF;
/* Resets all EP IRQ sources.*/
otgp->oe[ep].DOEPINT = epint;
otgp->oe[ep].DOEPINTF = epint;
if ((epint & DOEPINT_STUP) && (otgp->DOEPMSK & DOEPMSK_STUPM)) {
if ((epint & DOEPINTF_STPF) && (otgp->DOEPINTFEN & DOEPINTFEN_STPFEN)) {
/* Setup packets handling, setup packets are handled using a
specific callback.*/
_usb_isr_invoke_setup_cb(usbp, ep);
}
if ((epint & DOEPINT_XFRC) && (otgp->DOEPMSK & DOEPMSK_XFRCM)) {
if ((epint & DOEPINTF_TF) && (otgp->DOEPINTFEN & DOEPINTFEN_TFEN)) {
USBOutEndpointState *osp;
/* OUT state structure pointer for this endpoint.*/
@ -448,12 +448,12 @@ static void otg_isoc_in_failed_handler(USBDriver *usbp) {
gd32_usbfs_t *otgp = usbp->otg;
for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
if (((otgp->ie[ep].DIEPCTL & DIEPCTL_EPTYP_MASK) == DIEPCTL_EPTYP_ISO) &&
((otgp->ie[ep].DIEPCTL & DIEPCTL_EPENA) != 0)) {
if (((otgp->ie[ep].DIEPCTL & DIEPCTL_EPTYPE_MASK) == DIEPCTL_EPTYPE_ISO) &&
((otgp->ie[ep].DIEPCTL & DIEPCTL_EPEN) != 0)) {
/* Endpoint enabled -> ISOC IN transfer failed */
/* Disable endpoint */
otgp->ie[ep].DIEPCTL |= (DIEPCTL_EPDIS | DIEPCTL_SNAK);
while (otgp->ie[ep].DIEPCTL & DIEPCTL_EPENA)
otgp->ie[ep].DIEPCTL |= (DIEPCTL_EPD | DIEPCTL_SNAK);
while (otgp->ie[ep].DIEPCTL & DIEPCTL_EPEN)
;
/* Flush FIFO */
@ -480,13 +480,13 @@ static void otg_isoc_out_failed_handler(USBDriver *usbp) {
gd32_usbfs_t *otgp = usbp->otg;
for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
if (((otgp->oe[ep].DOEPCTL & DOEPCTL_EPTYP_MASK) == DOEPCTL_EPTYP_ISO) &&
((otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA) != 0)) {
if (((otgp->oe[ep].DOEPCTL & DOEPCTL_EPTYPE_MASK) == DOEPCTL_EPTYPE_ISO) &&
((otgp->oe[ep].DOEPCTL & DOEPCTL_EPEN) != 0)) {
/* Endpoint enabled -> ISOC OUT transfer failed */
/* Disable endpoint */
/* CHTODO:: Core stucks here */
/*otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPDIS | DOEPCTL_SNAK);
while (otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA)
/*otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPD | DOEPCTL_SNAK);
while (otgp->oe[ep].DOEPCTL & DOEPCTL_EPEN)
;*/
/* Prepare transfer for next frame.*/
_usb_isr_invoke_out_cb(usbp, ep);
@ -522,13 +522,13 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) {
if (sts & GINTF_WKUPIF) {
/* If clocks are gated off, turn them back on (may be the case if
coming out of suspend mode).*/
if (otgp->PCGCCTL & (PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK)) {
if (otgp->PWRCLKCTL & (PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK)) {
/* Set to zero to un-gate the USB core clocks.*/
otgp->PCGCCTL &= ~(PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK);
otgp->PWRCLKCTL &= ~(PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK);
}
/* Clear the Remote Wake-up Signaling.*/
otgp->DCTL &= ~DCTL_RWUSIG;
otgp->DCTL &= ~DCTL_RWKUP;
_usb_wakeup(usbp);
}
@ -544,15 +544,8 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) {
/* Enumeration done.*/
if (sts & GINTF_ENUMF) {
/* Full or High speed timing selection.*/
if ((otgp->DSTS & DSTS_ENUMSPD_MASK) == DSTS_ENUMSPD_HS_480) {
otgp->GUSBCS = (otgp->GUSBCS & ~(GUSBCS_UTT_MASK)) |
GUSBCS_UTT(TRDT_VALUE_HS);
}
else {
otgp->GUSBCS = (otgp->GUSBCS & ~(GUSBCS_UTT_MASK)) |
GUSBCS_UTT(TRDT_VALUE_FS);
}
}
/* SOF interrupt handling.*/
@ -577,7 +570,7 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) {
}
/* IN/OUT endpoints event handling.*/
src = otgp->DAINT;
src = otgp->DAEPINT;
if (sts & GINTF_OEPIF) {
if (src & (1 << 16))
otg_epout_handler(usbp, 0);
@ -667,11 +660,11 @@ void usb_lld_start(USBDriver *usbp) {
otgp->GUSBCS = GUSBCS_FDM | GUSBCS_UTT(TRDT_VALUE_FS);
/* 48MHz 1.1 PHY.*/
otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11;
otgp->DCFG = 0x02200000 | DCFG_DS_FS11;
}
/* PHY enabled.*/
otgp->PCGCCTL = 0;
otgp->PWRCLKCTL = 0;
/* VBUS sensing and transceiver enabled.*/
otgp->GCCFG = GCCFG_INIT_VALUE;
@ -687,9 +680,9 @@ void usb_lld_start(USBDriver *usbp) {
/* Clear all pending Device Interrupts, only the USB Reset interrupt
is required initially.*/
otgp->DIEPMSK = 0;
otgp->DOEPMSK = 0;
otgp->DAINTMSK = 0;
otgp->DIEPINTFEN = 0;
otgp->DOEPINTFEN = 0;
otgp->DAEPINTEN = 0;
if (usbp->config->sof_cb == NULL)
otgp->GINTEN = GINTEN_ENUMFIE | GINTEN_RSTIE | GINTEN_SPIE |
GINTEN_ESPIE | GINTEN_SESIE | GINTEN_WKUPIE |
@ -725,7 +718,7 @@ void usb_lld_stop(USBDriver *usbp) {
active.*/
otg_disable_ep(usbp);
otgp->DAINTMSK = 0;
otgp->DAEPINTEN = 0;
otgp->GAHBCS = 0;
otgp->GCCFG = 0;
@ -751,15 +744,15 @@ void usb_lld_reset(USBDriver *usbp) {
otg_txfifo_flush(usbp, 0);
/* Endpoint interrupts all disabled and cleared.*/
otgp->DIEPEMPMSK = 0;
otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0);
otgp->DIEPFEINTEN = 0;
otgp->DAEPINTEN = DAEPINTEN_OEPIE(0) | DAEPINTEN_IEPIE(0);
/* All endpoints in NAK mode, interrupts cleared.*/
for (i = 0; i <= usbp->otgparams->num_endpoints; i++) {
otgp->ie[i].DIEPCTL = DIEPCTL_SNAK;
otgp->oe[i].DOEPCTL = DOEPCTL_SNAK;
otgp->ie[i].DIEPINT = 0xFFFFFFFF;
otgp->oe[i].DOEPINT = 0xFFFFFFFF;
otgp->ie[i].DIEPINTF = 0xFFFFFFFF;
otgp->oe[i].DOEPINTF = 0xFFFFFFFF;
}
/* Resets the FIFO memory allocator.*/
@ -770,21 +763,21 @@ void usb_lld_reset(USBDriver *usbp) {
otg_rxfifo_flush(usbp);
/* Resets the device address to zero.*/
otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(0);
otgp->DCFG = (otgp->DCFG & ~DCFG_DAR_MASK) | DCFG_DAR(0);
/* Enables also EP-related interrupt sources.*/
otgp->GINTEN |= GINTEN_RXFNEIE | GINTEN_OEPIE | GINTEN_IEPIE;
otgp->DIEPMSK = DIEPMSK_TOCM | DIEPMSK_XFRCM;
otgp->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM;
otgp->DIEPINTFEN = DIEPINTFEN_CITOEN | DIEPINTFEN_TFEN;
otgp->DOEPINTFEN = DOEPINTFEN_STPFEN | DOEPINTFEN_TFEN;
/* EP0 initialization, it is a special case.*/
usbp->epc[0] = &ep0config;
otgp->oe[0].DOEPTSIZ = DOEPTSIZ_STUPCNT(3);
otgp->oe[0].DOEPCTL = DOEPCTL_SD0PID | DOEPCTL_USBAEP | DOEPCTL_EPTYP_CTRL |
DOEPCTL_MPSIZ(ep0config.out_maxsize);
otgp->ie[0].DIEPTSIZ = 0;
otgp->ie[0].DIEPCTL = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL |
DIEPCTL_TXFNUM(0) | DIEPCTL_MPSIZ(ep0config.in_maxsize);
otgp->oe[0].DOEPLEN = DOEPLEN_STPCNT(3);
otgp->oe[0].DOEPCTL = DOEPCTL_SD0PID | DOEPCTL_EPACT | DOEPCTL_EPTYPE_CTRL |
DOEPCTL_MPL(ep0config.out_maxsize);
otgp->ie[0].DIEPLEN = 0;
otgp->ie[0].DIEPCTL = DIEPCTL_SD0PID | DIEPCTL_EPACT | DIEPCTL_EPTYPE_CTRL |
DIEPCTL_TXFNUM(0) | DIEPCTL_MPL(ep0config.in_maxsize);
otgp->DIEPTFLEN0 = DIEPTFLEN_IEPTXFD(ep0config.in_maxsize / 4) |
DIEPTFLEN_IEPTXRSAR(otg_ram_alloc(usbp,
ep0config.in_maxsize / 4));
@ -800,7 +793,7 @@ void usb_lld_reset(USBDriver *usbp) {
void usb_lld_set_address(USBDriver *usbp) {
gd32_usbfs_t *otgp = usbp->otg;
otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(usbp->address);
otgp->DCFG = (otgp->DCFG & ~DCFG_DAR_MASK) | DCFG_DAR(usbp->address);
}
/**
@ -818,34 +811,34 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
/* IN and OUT common parameters.*/
switch (usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) {
case USB_EP_MODE_TYPE_CTRL:
ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL;
ctl = DIEPCTL_SD0PID | DIEPCTL_EPACT | DIEPCTL_EPTYPE_CTRL;
break;
case USB_EP_MODE_TYPE_ISOC:
ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_ISO;
ctl = DIEPCTL_SD0PID | DIEPCTL_EPACT | DIEPCTL_EPTYPE_ISO;
break;
case USB_EP_MODE_TYPE_BULK:
ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_BULK;
ctl = DIEPCTL_SD0PID | DIEPCTL_EPACT | DIEPCTL_EPTYPE_BULK;
break;
case USB_EP_MODE_TYPE_INTR:
ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_INTR;
ctl = DIEPCTL_SD0PID | DIEPCTL_EPACT | DIEPCTL_EPTYPE_INTR;
break;
default:
return;
}
/* OUT endpoint activation or deactivation.*/
otgp->oe[ep].DOEPTSIZ = 0;
otgp->oe[ep].DOEPLEN = 0;
if (usbp->epc[ep]->out_state != NULL) {
otgp->oe[ep].DOEPCTL = ctl | DOEPCTL_MPSIZ(usbp->epc[ep]->out_maxsize);
otgp->DAINTMSK |= DAINTMSK_OEPM(ep);
otgp->oe[ep].DOEPCTL = ctl | DOEPCTL_MPL(usbp->epc[ep]->out_maxsize);
otgp->DAEPINTEN |= DAEPINTEN_OEPIE(ep);
}
else {
otgp->oe[ep].DOEPCTL &= ~DOEPCTL_USBAEP;
otgp->DAINTMSK &= ~DAINTMSK_OEPM(ep);
otgp->oe[ep].DOEPCTL &= ~DOEPCTL_EPACT;
otgp->DAEPINTEN &= ~DAEPINTEN_OEPIE(ep);
}
/* IN endpoint activation or deactivation.*/
otgp->ie[ep].DIEPTSIZ = 0;
otgp->ie[ep].DIEPLEN = 0;
if (usbp->epc[ep]->in_state != NULL) {
/* FIFO allocation for the IN endpoint.*/
fsize = usbp->epc[ep]->in_maxsize / 4;
@ -857,14 +850,14 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
otgp->ie[ep].DIEPCTL = ctl |
DIEPCTL_TXFNUM(ep) |
DIEPCTL_MPSIZ(usbp->epc[ep]->in_maxsize);
otgp->DAINTMSK |= DAINTMSK_IEPM(ep);
DIEPCTL_MPL(usbp->epc[ep]->in_maxsize);
otgp->DAEPINTEN |= DAEPINTEN_IEPIE(ep);
}
else {
otgp->DIEPTFLEN[ep - 1] = 0x02000400; /* Reset value.*/
otg_txfifo_flush(usbp, ep);
otgp->ie[ep].DIEPCTL &= ~DIEPCTL_USBAEP;
otgp->DAINTMSK &= ~DAINTMSK_IEPM(ep);
otgp->ie[ep].DIEPCTL &= ~DIEPCTL_EPACT;
otgp->DAEPINTEN &= ~DAEPINTEN_IEPIE(ep);
}
}
@ -902,7 +895,7 @@ usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
(void)usbp;
ctl = usbp->otg->oe[ep].DOEPCTL;
if (!(ctl & DOEPCTL_USBAEP))
if (!(ctl & DOEPCTL_EPACT))
return EP_STATUS_DISABLED;
if (ctl & DOEPCTL_STALL)
return EP_STATUS_STALLED;
@ -927,7 +920,7 @@ usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
(void)usbp;
ctl = usbp->otg->ie[ep].DIEPCTL;
if (!(ctl & DIEPCTL_USBAEP))
if (!(ctl & DIEPCTL_EPACT))
return EP_STATUS_DISABLED;
if (ctl & DIEPCTL_STALL)
return EP_STATUS_STALLED;
@ -979,21 +972,21 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
usbp->epc[ep]->out_maxsize;
rxsize = (pcnt * usbp->epc[ep]->out_maxsize + 3U) & 0xFFFFFFFCU;
/*Setting up transaction parameters in DOEPTSIZ.*/
usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_STUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) |
DOEPTSIZ_XFRSIZ(rxsize);
/*Setting up transaction parameters in DOEPLEN.*/
usbp->otg->oe[ep].DOEPLEN = DOEPLEN_STPCNT(3) | DOEPLEN_PCNT(pcnt) |
DOEPLEN_TLEN(rxsize);
/* Special case of isochronous endpoint.*/
if ((usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) == USB_EP_MODE_TYPE_ISOC) {
/* Odd/even bit toggling for isochronous endpoint.*/
if (usbp->otg->DSTS & DSTS_FNSOF_ODD)
usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_SEVNFRM;
if (usbp->otg->DSTAT & DSTAT_FNRSOF_ODD)
usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_SEVENFRM;
else
usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_SODDFRM;
}
/* Starting operation.*/
usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_EPENA | DOEPCTL_CNAK;
usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_EPEN | DOEPCTL_CNAK;
}
/**
@ -1011,7 +1004,7 @@ void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
isp->totsize = isp->txsize;
if (isp->txsize == 0) {
/* Special case, sending zero size packet.*/
usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(1) | DIEPTSIZ_XFRSIZ(0);
usbp->otg->ie[ep].DIEPLEN = DIEPLEN_PCNT(1) | DIEPLEN_TLEN(0);
}
else {
if ((ep == 0) && (isp->txsize > EP0_MAX_INSIZE))
@ -1021,22 +1014,22 @@ void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
uint32_t pcnt = (isp->txsize + usbp->epc[ep]->in_maxsize - 1) /
usbp->epc[ep]->in_maxsize;
/* CHTODO: Support more than one packet per frame for isochronous transfers.*/
usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_MCNT(1) | DIEPTSIZ_PKTCNT(pcnt) |
DIEPTSIZ_XFRSIZ(isp->txsize);
usbp->otg->ie[ep].DIEPLEN = DIEPLEN_MCPF(1) | DIEPLEN_PCNT(pcnt) |
DIEPLEN_TLEN(isp->txsize);
}
/* Special case of isochronous endpoint.*/
if ((usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) == USB_EP_MODE_TYPE_ISOC) {
/* Odd/even bit toggling.*/
if (usbp->otg->DSTS & DSTS_FNSOF_ODD)
usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_SEVNFRM;
if (usbp->otg->DSTAT & DSTAT_FNRSOF_ODD)
usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_SEVENFRM;
else
usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_SODDFRM;
}
/* Starting operation.*/
usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK;
usbp->otg->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEM(ep);
usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_EPEN | DIEPCTL_CNAK;
usbp->otg->DIEPFEINTEN |= DIEPFEINTEN_IEPTXFEIE(ep);
}
/**

4
os/hal/ports/GD/GD32VF103/OTG/hal_usb_lld.h
View File

@ -455,9 +455,9 @@ struct USBDriver {
*/
#define usb_lld_wakeup_host(usbp) \
do { \
(usbp)->otg->DCTL |= DCTL_RWUSIG; \
(usbp)->otg->DCTL |= DCTL_RWKUP; \
osalThreadSleepMilliseconds(GD32_USB_HOST_WAKEUP_DURATION); \
(usbp)->otg->DCTL &= ~DCTL_RWUSIG; \
(usbp)->otg->DCTL &= ~DCTL_RWKUP; \
} while (false)
/*===========================================================================*/

28
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -582,18 +582,18 @@ typedef struct
{
__IO uint32_t DCFG; /*!< dev Configuration Register Address offset: 800h*/
__IO uint32_t DCTL; /*!< dev Control Register Address offset: 804h*/
__IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset: 808h*/
__IO uint32_t DSTAT; /*!< dev Status Register (RO) Address offset: 808h*/
uint32_t Reserved0C; /*!< Reserved 80Ch*/
__IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask Address offset: 810h*/
__IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset: 814h*/
__IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset: 818h*/
__IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/
__IO uint32_t DIEPINTFEN; /*!< dev IN Endpoint Mask Address offset: 810h*/
__IO uint32_t DOEPINTFEN; /*!< dev OUT Endpoint Mask Address offset: 814h*/
__IO uint32_t DAEPINT; /*!< dev All Endpoints Itr Reg Address offset: 818h*/
__IO uint32_t DAEPINTEN; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/
uint32_t Reserved20; /*!< Reserved 820h*/
uint32_t Reserved9; /*!< Reserved 824h*/
__IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset: 828h*/
__IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset: 82Ch*/
__IO uint32_t DVBUSDT; /*!< dev VBUS discharge Register Address offset: 828h*/
__IO uint32_t DVBUSPT; /*!< dev VBUS Pulse Register Address offset: 82Ch*/
__IO uint32_t DTHRCTL; /*!< dev thr Address offset: 830h*/
__IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset: 834h*/
__IO uint32_t DIEPFEINTEN; /*!< dev empty msk Address offset: 834h*/
__IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset: 838h*/
__IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/
uint32_t Reserved40; /*!< dedicated EP mask Address offset: 840h*/
@ -610,11 +610,11 @@ typedef struct
{
__IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h*/
__IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
__IO uint32_t DIEPINTF; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
__IO uint32_t DIEPLEN; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
__IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
__IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
__IO uint32_t DIEPTFSTAT; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
} USB_OTG_INEndpointTypeDef;
@ -626,9 +626,9 @@ typedef struct
{
__IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h*/
__IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
__IO uint32_t DOEPINTF; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
__IO uint32_t DOEPLEN; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
__IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
} USB_OTG_OUTEndpointTypeDef;
@ -773,7 +773,7 @@ typedef struct
#define USB_OTG_HOST_PORT_BASE 0x00000440U
#define USB_OTG_HOST_CHANNEL_BASE 0x00000500U
#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U
#define USB_OTG_PCGCCTL_BASE 0x00000E00U
#define USB_OTG_PWRCLKCTL_BASE 0x00000E00U
#define USB_OTG_FIFO_BASE 0x00001000U
#define USB_OTG_FIFO_SIZE 0x00001000U