diff --git a/os/common/ext/CMSIS/KINETIS/k64f.h b/os/common/ext/CMSIS/KINETIS/k64f.h index 648d8da3..76285dec 100644 --- a/os/common/ext/CMSIS/KINETIS/k64f.h +++ b/os/common/ext/CMSIS/KINETIS/k64f.h @@ -278,13 +278,12 @@ typedef enum IRQn { * @{ */ -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ -/* #include "system_MK64F12.h" /+ Device specific configuration file */ /*! * @} @@ -5108,15 +5107,15 @@ typedef struct { /* ---------------------------------------------------------------------------- - -- MPU Peripheral Access Layer + -- SYSMPU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! - * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer + * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer * @{ */ -/** MPU - Register Layout Typedef */ +/** SYSMPU - Register Layout Typedef */ typedef struct { __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */ uint8_t RESERVED_0[12]; @@ -5128,170 +5127,170 @@ typedef struct { __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */ uint8_t RESERVED_2[832]; __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */ -} MPU_TypeDef; +} SYSMPU_TypeDef; /* ---------------------------------------------------------------------------- - -- MPU Register Masks + -- SYSMPU Register Masks ---------------------------------------------------------------------------- */ /*! - * @addtogroup MPU_Register_Masks MPU Register Masks + * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks * @{ */ /*! @name CESR - Control/Error Status Register */ -#define MPU_CESR_VLD (0x1U) -#define MPU_CESR_NRGD_MASK (0xF00U) -#define MPU_CESR_NRGD_SHIFT (8U) -#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK) -#define MPU_CESR_NSP_MASK (0xF000U) -#define MPU_CESR_NSP_SHIFT (12U) -#define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK) -#define MPU_CESR_HRL_MASK (0xF0000U) -#define MPU_CESR_HRL_SHIFT (16U) -#define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK) -#define MPU_CESR_SPERR_MASK (0xF8000000U) -#define MPU_CESR_SPERR_SHIFT (27U) -#define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK) +#define SYSMPU_CESR_VLD (0x1U) +#define SYSMPU_CESR_NRGD_MASK (0xF00U) +#define SYSMPU_CESR_NRGD_SHIFT (8U) +#define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK) +#define SYSMPU_CESR_NSP_MASK (0xF000U) +#define SYSMPU_CESR_NSP_SHIFT (12U) +#define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK) +#define SYSMPU_CESR_HRL_MASK (0xF0000U) +#define SYSMPU_CESR_HRL_SHIFT (16U) +#define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK) +#define SYSMPU_CESR_SPERR_MASK (0xF8000000U) +#define SYSMPU_CESR_SPERR_SHIFT (27U) +#define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK) -/* The count of MPU_EAR */ -#define MPU_EAR_COUNT (5U) +/* The count of SYSMPU_EAR */ +#define SYSMPU_EAR_COUNT (5U) /*! @name EDR - Error Detail Register, slave port n */ -#define MPU_EDR_ERW (0x1U) -#define MPU_EDR_EATTR_MASK (0xEU) -#define MPU_EDR_EATTR_SHIFT (1U) -#define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK) -#define MPU_EDR_EMN_MASK (0xF0U) -#define MPU_EDR_EMN_SHIFT (4U) -#define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK) -#define MPU_EDR_EPID_MASK (0xFF00U) -#define MPU_EDR_EPID_SHIFT (8U) -#define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK) -#define MPU_EDR_EACD_MASK (0xFFFF0000U) -#define MPU_EDR_EACD_SHIFT (16U) -#define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK) +#define SYSMPU_EDR_ERW (0x1U) +#define SYSMPU_EDR_EATTR_MASK (0xEU) +#define SYSMPU_EDR_EATTR_SHIFT (1U) +#define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK) +#define SYSMPU_EDR_EMN_MASK (0xF0U) +#define SYSMPU_EDR_EMN_SHIFT (4U) +#define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK) +#define SYSMPU_EDR_EPID_MASK (0xFF00U) +#define SYSMPU_EDR_EPID_SHIFT (8U) +#define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK) +#define SYSMPU_EDR_EACD_MASK (0xFFFF0000U) +#define SYSMPU_EDR_EACD_SHIFT (16U) +#define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK) -/* The count of MPU_EDR */ -#define MPU_EDR_COUNT (5U) +/* The count of SYSMPU_EDR */ +#define SYSMPU_EDR_COUNT (5U) /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */ -#define MPU_WORD_VLD (0x1U) -#define MPU_WORD_M0UM_MASK (0x7U) -#define MPU_WORD_M0UM_SHIFT (0U) -#define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK) -#define MPU_WORD_M0SM_MASK (0x18U) -#define MPU_WORD_M0SM_SHIFT (3U) -#define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK) -#define MPU_WORD_M0PE (0x20U) -#define MPU_WORD_ENDADDR_MASK (0xFFFFFFE0U) -#define MPU_WORD_ENDADDR_SHIFT (5U) -#define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK) -#define MPU_WORD_SRTADDR_MASK (0xFFFFFFE0U) -#define MPU_WORD_SRTADDR_SHIFT (5U) -#define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK) -#define MPU_WORD_M1UM_MASK (0x1C0U) -#define MPU_WORD_M1UM_SHIFT (6U) -#define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK) -#define MPU_WORD_M1SM_MASK (0x600U) -#define MPU_WORD_M1SM_SHIFT (9U) -#define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK) -#define MPU_WORD_M1PE (0x800U) -#define MPU_WORD_M2UM_MASK (0x7000U) -#define MPU_WORD_M2UM_SHIFT (12U) -#define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK) -#define MPU_WORD_M2SM_MASK (0x18000U) -#define MPU_WORD_M2SM_SHIFT (15U) -#define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK) -#define MPU_WORD_PIDMASK_MASK (0xFF0000U) -#define MPU_WORD_PIDMASK_SHIFT (16U) -#define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK) -#define MPU_WORD_M2PE (0x20000U) -#define MPU_WORD_M3UM_MASK (0x1C0000U) -#define MPU_WORD_M3UM_SHIFT (18U) -#define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK) -#define MPU_WORD_M3SM_MASK (0x600000U) -#define MPU_WORD_M3SM_SHIFT (21U) -#define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK) -#define MPU_WORD_M3PE (0x800000U) -#define MPU_WORD_PID_MASK (0xFF000000U) -#define MPU_WORD_PID_SHIFT (24U) -#define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK) -#define MPU_WORD_M4WE (0x1000000U) -#define MPU_WORD_M4RE (0x2000000U) -#define MPU_WORD_M5WE (0x4000000U) -#define MPU_WORD_M5RE (0x8000000U) -#define MPU_WORD_M6WE (0x10000000U) -#define MPU_WORD_M6RE (0x20000000U) -#define MPU_WORD_M7WE (0x40000000U) -#define MPU_WORD_M7RE (0x80000000U) +#define SYSMPU_WORD_VLD (0x1U) +#define SYSMPU_WORD_M0UM_MASK (0x7U) +#define SYSMPU_WORD_M0UM_SHIFT (0U) +#define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK) +#define SYSMPU_WORD_M0SM_MASK (0x18U) +#define SYSMPU_WORD_M0SM_SHIFT (3U) +#define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK) +#define SYSMPU_WORD_M0PE (0x20U) +#define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U) +#define SYSMPU_WORD_ENDADDR_SHIFT (5U) +#define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK) +#define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U) +#define SYSMPU_WORD_SRTADDR_SHIFT (5U) +#define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK) +#define SYSMPU_WORD_M1UM_MASK (0x1C0U) +#define SYSMPU_WORD_M1UM_SHIFT (6U) +#define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK) +#define SYSMPU_WORD_M1SM_MASK (0x600U) +#define SYSMPU_WORD_M1SM_SHIFT (9U) +#define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK) +#define SYSMPU_WORD_M1PE (0x800U) +#define SYSMPU_WORD_M2UM_MASK (0x7000U) +#define SYSMPU_WORD_M2UM_SHIFT (12U) +#define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK) +#define SYSMPU_WORD_M2SM_MASK (0x18000U) +#define SYSMPU_WORD_M2SM_SHIFT (15U) +#define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK) +#define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U) +#define SYSMPU_WORD_PIDMASK_SHIFT (16U) +#define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK) +#define SYSMPU_WORD_M2PE (0x20000U) +#define SYSMPU_WORD_M3UM_MASK (0x1C0000U) +#define SYSMPU_WORD_M3UM_SHIFT (18U) +#define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK) +#define SYSMPU_WORD_M3SM_MASK (0x600000U) +#define SYSMPU_WORD_M3SM_SHIFT (21U) +#define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK) +#define SYSMPU_WORD_M3PE (0x800000U) +#define SYSMPU_WORD_PID_MASK (0xFF000000U) +#define SYSMPU_WORD_PID_SHIFT (24U) +#define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK) +#define SYSMPU_WORD_M4WE (0x1000000U) +#define SYSMPU_WORD_M4RE (0x2000000U) +#define SYSMPU_WORD_M5WE (0x4000000U) +#define SYSMPU_WORD_M5RE (0x8000000U) +#define SYSMPU_WORD_M6WE (0x10000000U) +#define SYSMPU_WORD_M6RE (0x20000000U) +#define SYSMPU_WORD_M7WE (0x40000000U) +#define SYSMPU_WORD_M7RE (0x80000000U) -/* The count of MPU_WORD */ -#define MPU_WORD_COUNT (12U) +/* The count of SYSMPU_WORD */ +#define SYSMPU_WORD_COUNT (12U) -/* The count of MPU_WORD */ -#define MPU_WORD_COUNT2 (4U) +/* The count of SYSMPU_WORD */ +#define SYSMPU_WORD_COUNT2 (4U) /*! @name RGDAAC - Region Descriptor Alternate Access Control n */ -#define MPU_RGDAAC_M0UM_MASK (0x7U) -#define MPU_RGDAAC_M0UM_SHIFT (0U) -#define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK) -#define MPU_RGDAAC_M0SM_MASK (0x18U) -#define MPU_RGDAAC_M0SM_SHIFT (3U) -#define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK) -#define MPU_RGDAAC_M0PE (0x20U) -#define MPU_RGDAAC_M1UM_MASK (0x1C0U) -#define MPU_RGDAAC_M1UM_SHIFT (6U) -#define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK) -#define MPU_RGDAAC_M1SM_MASK (0x600U) -#define MPU_RGDAAC_M1SM_SHIFT (9U) -#define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK) -#define MPU_RGDAAC_M1PE (0x800U) -#define MPU_RGDAAC_M2UM_MASK (0x7000U) -#define MPU_RGDAAC_M2UM_SHIFT (12U) -#define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK) -#define MPU_RGDAAC_M2SM_MASK (0x18000U) -#define MPU_RGDAAC_M2SM_SHIFT (15U) -#define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK) -#define MPU_RGDAAC_M2PE (0x20000U) -#define MPU_RGDAAC_M3UM_MASK (0x1C0000U) -#define MPU_RGDAAC_M3UM_SHIFT (18U) -#define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK) -#define MPU_RGDAAC_M3SM_MASK (0x600000U) -#define MPU_RGDAAC_M3SM_SHIFT (21U) -#define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK) -#define MPU_RGDAAC_M3PE (0x800000U) -#define MPU_RGDAAC_M4WE (0x1000000U) -#define MPU_RGDAAC_M4RE (0x2000000U) -#define MPU_RGDAAC_M5WE (0x4000000U) -#define MPU_RGDAAC_M5RE (0x8000000U) -#define MPU_RGDAAC_M6WE (0x10000000U) -#define MPU_RGDAAC_M6RE (0x20000000U) -#define MPU_RGDAAC_M7WE (0x40000000U) -#define MPU_RGDAAC_M7RE (0x80000000U) +#define SYSMPU_RGDAAC_M0UM_MASK (0x7U) +#define SYSMPU_RGDAAC_M0UM_SHIFT (0U) +#define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK) +#define SYSMPU_RGDAAC_M0SM_MASK (0x18U) +#define SYSMPU_RGDAAC_M0SM_SHIFT (3U) +#define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK) +#define SYSMPU_RGDAAC_M0PE (0x20U) +#define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U) +#define SYSMPU_RGDAAC_M1UM_SHIFT (6U) +#define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK) +#define SYSMPU_RGDAAC_M1SM_MASK (0x600U) +#define SYSMPU_RGDAAC_M1SM_SHIFT (9U) +#define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK) +#define SYSMPU_RGDAAC_M1PE (0x800U) +#define SYSMPU_RGDAAC_M2UM_MASK (0x7000U) +#define SYSMPU_RGDAAC_M2UM_SHIFT (12U) +#define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK) +#define SYSMPU_RGDAAC_M2SM_MASK (0x18000U) +#define SYSMPU_RGDAAC_M2SM_SHIFT (15U) +#define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK) +#define SYSMPU_RGDAAC_M2PE (0x20000U) +#define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U) +#define SYSMPU_RGDAAC_M3UM_SHIFT (18U) +#define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK) +#define SYSMPU_RGDAAC_M3SM_MASK (0x600000U) +#define SYSMPU_RGDAAC_M3SM_SHIFT (21U) +#define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK) +#define SYSMPU_RGDAAC_M3PE (0x800000U) +#define SYSMPU_RGDAAC_M4WE (0x1000000U) +#define SYSMPU_RGDAAC_M4RE (0x2000000U) +#define SYSMPU_RGDAAC_M5WE (0x4000000U) +#define SYSMPU_RGDAAC_M5RE (0x8000000U) +#define SYSMPU_RGDAAC_M6WE (0x10000000U) +#define SYSMPU_RGDAAC_M6RE (0x20000000U) +#define SYSMPU_RGDAAC_M7WE (0x40000000U) +#define SYSMPU_RGDAAC_M7RE (0x80000000U) -/* The count of MPU_RGDAAC */ -#define MPU_RGDAAC_COUNT (12U) +/* The count of SYSMPU_RGDAAC */ +#define SYSMPU_RGDAAC_COUNT (12U) /*! * @} - */ /* end of group MPU_Register_Masks */ + */ /* end of group SYSMPU_Register_Masks */ -/* MPU - Peripheral instance base addresses */ -/** Peripheral MPU base address */ -#define MPU_BASE (0x4000D000u) -/** Peripheral MPU base pointer */ -#define MPU ((MPU_TypeDef *)MPU_BASE) -/** Array initializer of MPU peripheral base addresses */ -#define MPU_BASE_ADDRS { MPU_BASE } -/** Array initializer of MPU peripheral base pointers */ -#define MPU_BASE_PTRS { MPU } +/* SYSMPU - Peripheral instance base addresses */ +/** Peripheral SYSMPU base address */ +#define SYSMPU_BASE (0x4000D000u) +/** Peripheral SYSMPU base pointer */ +#define SYSMPU ((SYSMPU_TypeDef *)SYSMPU_BASE) +/** Array initializer of SYSMPU peripheral base addresses */ +#define SYSMPU_BASE_ADDRS { SYSMPU_BASE } +/** Array initializer of SYSMPU peripheral base pointers */ +#define SYSMPU_BASE_PTRS { SYSMPU } /*! * @} - */ /* end of group MPU_Peripheral_Access_Layer */ + */ /* end of group SYSMPU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- diff --git a/os/hal/boards/PJRC_TEENSY_3_5/board.h b/os/hal/boards/PJRC_TEENSY_3_5/board.h index efa0a563..b363167c 100644 --- a/os/hal/boards/PJRC_TEENSY_3_5/board.h +++ b/os/hal/boards/PJRC_TEENSY_3_5/board.h @@ -31,7 +31,7 @@ #define KINETIS_XTAL_FREQUENCY 16000000UL /* Use internal capacitors for the crystal */ -#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P +#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P|OSC_CR_ERCLKEN /* * MCU type @@ -52,16 +52,16 @@ #define TEENSY_PIN40 28 #define TEENSY_PIN41 29 -#define TEENSY_PIN25_IOPORT IOPORT1 +#define TEENSY_PIN40_IOPORT IOPORT1 +#define TEENSY_PIN41_IOPORT IOPORT1 +#define TEENSY_PIN42_IOPORT IOPORT1 #define TEENSY_PIN3_IOPORT IOPORT1 #define TEENSY_PIN4_IOPORT IOPORT1 +#define TEENSY_PIN25_IOPORT IOPORT1 #define TEENSY_PIN26_IOPORT IOPORT1 #define TEENSY_PIN27_IOPORT IOPORT1 #define TEENSY_PIN28_IOPORT IOPORT1 #define TEENSY_PIN39_IOPORT IOPORT1 -#define TEENSY_PIN42_IOPORT IOPORT1 -#define TEENSY_PIN40_IOPORT IOPORT1 -#define TEENSY_PIN41_IOPORT IOPORT1 #define TEENSY_PIN16 0 #define TEENSY_PIN17 1 @@ -80,22 +80,22 @@ #define TEENSY_PIN44 22 #define TEENSY_PIN45 23 -#define TEENSY_PIN16_IOPORT IOPORT2 -#define TEENSY_PIN17_IOPORT IOPORT2 -#define TEENSY_PIN19_IOPORT IOPORT2 -#define TEENSY_PIN18_IOPORT IOPORT2 #define TEENSY_PIN49_IOPORT IOPORT2 #define TEENSY_PIN50_IOPORT IOPORT2 -#define TEENSY_PIN31_IOPORT IOPORT2 -#define TEENSY_PIN32_IOPORT IOPORT2 +#define TEENSY_PIN43_IOPORT IOPORT2 +#define TEENSY_PIN44_IOPORT IOPORT2 +#define TEENSY_PIN45_IOPORT IOPORT2 +#define TEENSY_PIN46_IOPORT IOPORT2 #define TEENSY_PIN0_IOPORT IOPORT2 #define TEENSY_PIN1_IOPORT IOPORT2 #define TEENSY_PIN29_IOPORT IOPORT2 #define TEENSY_PIN30_IOPORT IOPORT2 -#define TEENSY_PIN43_IOPORT IOPORT2 -#define TEENSY_PIN46_IOPORT IOPORT2 -#define TEENSY_PIN44_IOPORT IOPORT2 -#define TEENSY_PIN45_IOPORT IOPORT2 +#define TEENSY_PIN31_IOPORT IOPORT2 +#define TEENSY_PIN32_IOPORT IOPORT2 +#define TEENSY_PIN16_IOPORT IOPORT2 +#define TEENSY_PIN17_IOPORT IOPORT2 +#define TEENSY_PIN19_IOPORT IOPORT2 +#define TEENSY_PIN18_IOPORT IOPORT2 #define TEENSY_PIN15 0 #define TEENSY_PIN22 1 @@ -110,18 +110,18 @@ #define TEENSY_PIN37 10 #define TEENSY_PIN38 11 -#define TEENSY_PIN15_IOPORT IOPORT3 -#define TEENSY_PIN22_IOPORT IOPORT3 -#define TEENSY_PIN23_IOPORT IOPORT3 #define TEENSY_PIN9_IOPORT IOPORT3 #define TEENSY_PIN10_IOPORT IOPORT3 -#define TEENSY_PIN13_IOPORT IOPORT3 #define TEENSY_PIN11_IOPORT IOPORT3 #define TEENSY_PIN12_IOPORT IOPORT3 #define TEENSY_PIN35_IOPORT IOPORT3 #define TEENSY_PIN36_IOPORT IOPORT3 #define TEENSY_PIN37_IOPORT IOPORT3 #define TEENSY_PIN38_IOPORT IOPORT3 +#define TEENSY_PIN13_IOPORT IOPORT3 +#define TEENSY_PIN15_IOPORT IOPORT3 +#define TEENSY_PIN22_IOPORT IOPORT3 +#define TEENSY_PIN23_IOPORT IOPORT3 #define TEENSY_PIN2 0 #define TEENSY_PIN14 1 @@ -139,21 +139,21 @@ #define TEENSY_PIN51 14 #define TEENSY_PIN54 15 -#define TEENSY_PIN2_IOPORT IOPORT4 -#define TEENSY_PIN14_IOPORT IOPORT4 -#define TEENSY_PIN7_IOPORT IOPORT4 -#define TEENSY_PIN8_IOPORT IOPORT4 -#define TEENSY_PIN6_IOPORT IOPORT4 -#define TEENSY_PIN20_IOPORT IOPORT4 -#define TEENSY_PIN21_IOPORT IOPORT4 -#define TEENSY_PIN5_IOPORT IOPORT4 +#define TEENSY_PIN51_IOPORT IOPORT4 +#define TEENSY_PIN52_IOPORT IOPORT4 +#define TEENSY_PIN53_IOPORT IOPORT4 +#define TEENSY_PIN54_IOPORT IOPORT4 +#define TEENSY_PIN55_IOPORT IOPORT4 #define TEENSY_PIN47_IOPORT IOPORT4 #define TEENSY_PIN48_IOPORT IOPORT4 -#define TEENSY_PIN55_IOPORT IOPORT4 -#define TEENSY_PIN53_IOPORT IOPORT4 -#define TEENSY_PIN52_IOPORT IOPORT4 -#define TEENSY_PIN51_IOPORT IOPORT4 -#define TEENSY_PIN54_IOPORT IOPORT4 +#define TEENSY_PIN2_IOPORT IOPORT4 +#define TEENSY_PIN5_IOPORT IOPORT4 +#define TEENSY_PIN6_IOPORT IOPORT4 +#define TEENSY_PIN7_IOPORT IOPORT4 +#define TEENSY_PIN8_IOPORT IOPORT4 +#define TEENSY_PIN14_IOPORT IOPORT4 +#define TEENSY_PIN20_IOPORT IOPORT4 +#define TEENSY_PIN21_IOPORT IOPORT4 #define TEENSY_PIN56 10 #define TEENSY_PIN57 11 @@ -163,9 +163,9 @@ #define TEENSY_PIN56_IOPORT IOPORT5 #define TEENSY_PIN57_IOPORT IOPORT5 +#define TEENSY_PIN24_IOPORT IOPORT5 #define TEENSY_PIN33_IOPORT IOPORT5 #define TEENSY_PIN34_IOPORT IOPORT5 -#define TEENSY_PIN24_IOPORT IOPORT5 #define LINE_PIN0 PAL_LINE(TEENSY_PIN0_IOPORT, TEENSY_PIN0) #define LINE_PIN1 PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1) diff --git a/os/hal/ports/KINETIS/K60x/hal_lld.c b/os/hal/ports/KINETIS/K60x/hal_lld.c index cfe633bd..1efa47aa 100644 --- a/os/hal/ports/KINETIS/K60x/hal_lld.c +++ b/os/hal/ports/KINETIS/K60x/hal_lld.c @@ -82,6 +82,11 @@ const uint8_t _cfm[0x10] = { */ void hal_lld_init(void) { +#if defined(K64F) + /* Disable the MPU by default */ + SYSMPU->CESR &= ~SYSMPU_CESR_VLD; +#endif + } /** @@ -181,9 +186,9 @@ void k60x_clock_init(void) { /* * Now in FBE mode */ - #define KINETIS_PLLIN_FREQUENCY 2000000UL + #define KINETIS_PLLIN_FREQUENCY 4000000UL /* - * Config PLL input for 2 MHz + * Config PLL input for 4 MHz * TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz */ MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1); @@ -215,8 +220,10 @@ void k60x_clock_init(void) { SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) | SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) | SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1); - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); - SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL_IRC48M; /* FIXME ? Why this? */ + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC; + + /* Configure peripherals to use MCGPLLCLK */ + SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL_MCGPLL; /* Switch to PLL as clock source */ MCG->C1 = MCG_C1_CLKS(0); diff --git a/os/hal/ports/KINETIS/K60x/hal_lld.h b/os/hal/ports/KINETIS/K60x/hal_lld.h index 8da89b30..ac1a083f 100644 --- a/os/hal/ports/KINETIS/K60x/hal_lld.h +++ b/os/hal/ports/KINETIS/K60x/hal_lld.h @@ -119,6 +119,21 @@ #endif #endif +/** + * @brief Clock divider for FlexBus clock (OUTDIV3). + * @note The allowed range is 1..16 + * @note The default value is calculated for a 48 MHz clock + * from a 96 MHz PLL output. + */ +#if !defined(KINETIS_CLKDIV1_OUTDIV3) || defined(__DOXYGEN__) + #if defined(KINETIS_FLEXBUSCLK_FREQUENCY) && KINETIS_FLEXBUSCLK_FREQUENCY > 0 + #define KINETIS_CLKDIV1_OUTDIV3 (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLEXBUSCLK_FREQUENCY) + #else + /* If no FlexBus frequency provided, use bus speed divider */ + #define KINETIS_CLKDIV1_OUTDIV3 KINETIS_CLKDIV1_OUTDIV2 + #endif +#endif + /** * @brief Clock divider for flash clock (OUTDIV4). * @note The allowed range is 1..16 @@ -228,6 +243,11 @@ #error KINETIS_CLKDIV1_OUTDIV2 must be 1 through 16 #endif +#if !(defined(KINETIS_CLKDIV1_OUTDIV3) && \ + KINETIS_CLKDIV1_OUTDIV3 >= 1 && KINETIS_CLKDIV1_OUTDIV3 <= 16) +#error KINETIS_CLKDIV1_OUTDIV3 must be 1 through 16 +#endif + #if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \ KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16) #error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16 diff --git a/os/hal/ports/KINETIS/K60x/platform.mk b/os/hal/ports/KINETIS/K60x/platform.mk index 978d8df7..de31fd4b 100644 --- a/os/hal/ports/KINETIS/K60x/platform.mk +++ b/os/hal/ports/KINETIS/K60x/platform.mk @@ -19,11 +19,11 @@ endif include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/GPIOv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/UARTv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/I2Cv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PORTv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ADCv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SDHCv1/driver.mk -include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/I2Cv1/driver.mk -include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ADCv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/USBHSv1/driver.mk # Shared variables diff --git a/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c index da75f0c5..e8838c16 100644 --- a/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c +++ b/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c @@ -407,7 +407,7 @@ void usb_lld_init(void) { #elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE -#if !defined(MK66F18) +#if !defined(MK66F18) && !defined(K64F) /* Note: We don't need this for MK66F18, we can use IRC48M clock for USB */ #define KINETIS_USBCLK_FREQUENCY 48000000UL uint32_t i,j; @@ -427,6 +427,12 @@ void usb_lld_init(void) { #error USB clock setting not implemented for this KINETIS_MCG_MODE #endif /* KINETIS_MCG_MODE == ... */ +#if defined(K64F) + /* Switch from default MCGPLLCLK to IRC48M for USB */ + //SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); + //SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_IRC48M; +#endif + #if defined(MK66F18) /* Switch from default MCGPLLCLK to IRC48M for USB */ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);