From 09d1e9756f7ad2015a786d47c0583a3687efbe4d Mon Sep 17 00:00:00 2001 From: fauxpark Date: Sat, 13 Nov 2021 01:28:43 +1100 Subject: [PATCH 1/4] [WIP] Further K64F modifications, attempting to get USB working --- os/common/ext/CMSIS/KINETIS/k64f.h | 280 +++++++++--------- os/common/ext/CMSIS/KINETIS/system_MK64F12.h | 168 +++++++++++ os/hal/boards/PJRC_TEENSY_3_5/board.h | 66 ++--- os/hal/ports/KINETIS/K60x/hal_lld.c | 9 +- os/hal/ports/KINETIS/K60x/hal_lld.h | 20 ++ os/hal/ports/KINETIS/K60x/platform.mk | 4 +- .../ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c | 8 +- 7 files changed, 378 insertions(+), 177 deletions(-) create mode 100644 os/common/ext/CMSIS/KINETIS/system_MK64F12.h diff --git a/os/common/ext/CMSIS/KINETIS/k64f.h b/os/common/ext/CMSIS/KINETIS/k64f.h index 648d8da3..0eb67acc 100644 --- a/os/common/ext/CMSIS/KINETIS/k64f.h +++ b/os/common/ext/CMSIS/KINETIS/k64f.h @@ -278,13 +278,13 @@ typedef enum IRQn { * @{ */ -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ -/* #include "system_MK64F12.h" /+ Device specific configuration file */ +#include "system_MK64F12.h" /* Device specific configuration file */ /*! * @} @@ -5108,15 +5108,15 @@ typedef struct { /* ---------------------------------------------------------------------------- - -- MPU Peripheral Access Layer + -- SYSMPU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! - * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer + * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer * @{ */ -/** MPU - Register Layout Typedef */ +/** SYSMPU - Register Layout Typedef */ typedef struct { __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */ uint8_t RESERVED_0[12]; @@ -5128,170 +5128,170 @@ typedef struct { __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */ uint8_t RESERVED_2[832]; __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */ -} MPU_TypeDef; +} SYSMPU_TypeDef; /* ---------------------------------------------------------------------------- - -- MPU Register Masks + -- SYSMPU Register Masks ---------------------------------------------------------------------------- */ /*! - * @addtogroup MPU_Register_Masks MPU Register Masks + * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks * @{ */ /*! @name CESR - Control/Error Status Register */ -#define MPU_CESR_VLD (0x1U) -#define MPU_CESR_NRGD_MASK (0xF00U) -#define MPU_CESR_NRGD_SHIFT (8U) -#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK) -#define MPU_CESR_NSP_MASK (0xF000U) -#define MPU_CESR_NSP_SHIFT (12U) -#define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK) -#define MPU_CESR_HRL_MASK (0xF0000U) -#define MPU_CESR_HRL_SHIFT (16U) -#define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK) -#define MPU_CESR_SPERR_MASK (0xF8000000U) -#define MPU_CESR_SPERR_SHIFT (27U) -#define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK) +#define SYSMPU_CESR_VLD (0x1U) +#define SYSMPU_CESR_NRGD_MASK (0xF00U) +#define SYSMPU_CESR_NRGD_SHIFT (8U) +#define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK) +#define SYSMPU_CESR_NSP_MASK (0xF000U) +#define SYSMPU_CESR_NSP_SHIFT (12U) +#define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK) +#define SYSMPU_CESR_HRL_MASK (0xF0000U) +#define SYSMPU_CESR_HRL_SHIFT (16U) +#define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK) +#define SYSMPU_CESR_SPERR_MASK (0xF8000000U) +#define SYSMPU_CESR_SPERR_SHIFT (27U) +#define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK) -/* The count of MPU_EAR */ -#define MPU_EAR_COUNT (5U) +/* The count of SYSMPU_EAR */ +#define SYSMPU_EAR_COUNT (5U) /*! @name EDR - Error Detail Register, slave port n */ -#define MPU_EDR_ERW (0x1U) -#define MPU_EDR_EATTR_MASK (0xEU) -#define MPU_EDR_EATTR_SHIFT (1U) -#define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK) -#define MPU_EDR_EMN_MASK (0xF0U) -#define MPU_EDR_EMN_SHIFT (4U) -#define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK) -#define MPU_EDR_EPID_MASK (0xFF00U) -#define MPU_EDR_EPID_SHIFT (8U) -#define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK) -#define MPU_EDR_EACD_MASK (0xFFFF0000U) -#define MPU_EDR_EACD_SHIFT (16U) -#define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK) +#define SYSMPU_EDR_ERW (0x1U) +#define SYSMPU_EDR_EATTR_MASK (0xEU) +#define SYSMPU_EDR_EATTR_SHIFT (1U) +#define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK) +#define SYSMPU_EDR_EMN_MASK (0xF0U) +#define SYSMPU_EDR_EMN_SHIFT (4U) +#define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK) +#define SYSMPU_EDR_EPID_MASK (0xFF00U) +#define SYSMPU_EDR_EPID_SHIFT (8U) +#define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK) +#define SYSMPU_EDR_EACD_MASK (0xFFFF0000U) +#define SYSMPU_EDR_EACD_SHIFT (16U) +#define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK) -/* The count of MPU_EDR */ -#define MPU_EDR_COUNT (5U) +/* The count of SYSMPU_EDR */ +#define SYSMPU_EDR_COUNT (5U) /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */ -#define MPU_WORD_VLD (0x1U) -#define MPU_WORD_M0UM_MASK (0x7U) -#define MPU_WORD_M0UM_SHIFT (0U) -#define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK) -#define MPU_WORD_M0SM_MASK (0x18U) -#define MPU_WORD_M0SM_SHIFT (3U) -#define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK) -#define MPU_WORD_M0PE (0x20U) -#define MPU_WORD_ENDADDR_MASK (0xFFFFFFE0U) -#define MPU_WORD_ENDADDR_SHIFT (5U) -#define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK) -#define MPU_WORD_SRTADDR_MASK (0xFFFFFFE0U) -#define MPU_WORD_SRTADDR_SHIFT (5U) -#define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK) -#define MPU_WORD_M1UM_MASK (0x1C0U) -#define MPU_WORD_M1UM_SHIFT (6U) -#define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK) -#define MPU_WORD_M1SM_MASK (0x600U) -#define MPU_WORD_M1SM_SHIFT (9U) -#define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK) -#define MPU_WORD_M1PE (0x800U) -#define MPU_WORD_M2UM_MASK (0x7000U) -#define MPU_WORD_M2UM_SHIFT (12U) -#define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK) -#define MPU_WORD_M2SM_MASK (0x18000U) -#define MPU_WORD_M2SM_SHIFT (15U) -#define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK) -#define MPU_WORD_PIDMASK_MASK (0xFF0000U) -#define MPU_WORD_PIDMASK_SHIFT (16U) -#define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK) -#define MPU_WORD_M2PE (0x20000U) -#define MPU_WORD_M3UM_MASK (0x1C0000U) -#define MPU_WORD_M3UM_SHIFT (18U) -#define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK) -#define MPU_WORD_M3SM_MASK (0x600000U) -#define MPU_WORD_M3SM_SHIFT (21U) -#define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK) -#define MPU_WORD_M3PE (0x800000U) -#define MPU_WORD_PID_MASK (0xFF000000U) -#define MPU_WORD_PID_SHIFT (24U) -#define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK) -#define MPU_WORD_M4WE (0x1000000U) -#define MPU_WORD_M4RE (0x2000000U) -#define MPU_WORD_M5WE (0x4000000U) -#define MPU_WORD_M5RE (0x8000000U) -#define MPU_WORD_M6WE (0x10000000U) -#define MPU_WORD_M6RE (0x20000000U) -#define MPU_WORD_M7WE (0x40000000U) -#define MPU_WORD_M7RE (0x80000000U) +#define SYSMPU_WORD_VLD (0x1U) +#define SYSMPU_WORD_M0UM_MASK (0x7U) +#define SYSMPU_WORD_M0UM_SHIFT (0U) +#define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK) +#define SYSMPU_WORD_M0SM_MASK (0x18U) +#define SYSMPU_WORD_M0SM_SHIFT (3U) +#define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK) +#define SYSMPU_WORD_M0PE (0x20U) +#define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U) +#define SYSMPU_WORD_ENDADDR_SHIFT (5U) +#define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK) +#define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U) +#define SYSMPU_WORD_SRTADDR_SHIFT (5U) +#define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK) +#define SYSMPU_WORD_M1UM_MASK (0x1C0U) +#define SYSMPU_WORD_M1UM_SHIFT (6U) +#define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK) +#define SYSMPU_WORD_M1SM_MASK (0x600U) +#define SYSMPU_WORD_M1SM_SHIFT (9U) +#define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK) +#define SYSMPU_WORD_M1PE (0x800U) +#define SYSMPU_WORD_M2UM_MASK (0x7000U) +#define SYSMPU_WORD_M2UM_SHIFT (12U) +#define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK) +#define SYSMPU_WORD_M2SM_MASK (0x18000U) +#define SYSMPU_WORD_M2SM_SHIFT (15U) +#define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK) +#define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U) +#define SYSMPU_WORD_PIDMASK_SHIFT (16U) +#define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK) +#define SYSMPU_WORD_M2PE (0x20000U) +#define SYSMPU_WORD_M3UM_MASK (0x1C0000U) +#define SYSMPU_WORD_M3UM_SHIFT (18U) +#define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK) +#define SYSMPU_WORD_M3SM_MASK (0x600000U) +#define SYSMPU_WORD_M3SM_SHIFT (21U) +#define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK) +#define SYSMPU_WORD_M3PE (0x800000U) +#define SYSMPU_WORD_PID_MASK (0xFF000000U) +#define SYSMPU_WORD_PID_SHIFT (24U) +#define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK) +#define SYSMPU_WORD_M4WE (0x1000000U) +#define SYSMPU_WORD_M4RE (0x2000000U) +#define SYSMPU_WORD_M5WE (0x4000000U) +#define SYSMPU_WORD_M5RE (0x8000000U) +#define SYSMPU_WORD_M6WE (0x10000000U) +#define SYSMPU_WORD_M6RE (0x20000000U) +#define SYSMPU_WORD_M7WE (0x40000000U) +#define SYSMPU_WORD_M7RE (0x80000000U) -/* The count of MPU_WORD */ -#define MPU_WORD_COUNT (12U) +/* The count of SYSMPU_WORD */ +#define SYSMPU_WORD_COUNT (12U) -/* The count of MPU_WORD */ -#define MPU_WORD_COUNT2 (4U) +/* The count of SYSMPU_WORD */ +#define SYSMPU_WORD_COUNT2 (4U) /*! @name RGDAAC - Region Descriptor Alternate Access Control n */ -#define MPU_RGDAAC_M0UM_MASK (0x7U) -#define MPU_RGDAAC_M0UM_SHIFT (0U) -#define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK) -#define MPU_RGDAAC_M0SM_MASK (0x18U) -#define MPU_RGDAAC_M0SM_SHIFT (3U) -#define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK) -#define MPU_RGDAAC_M0PE (0x20U) -#define MPU_RGDAAC_M1UM_MASK (0x1C0U) -#define MPU_RGDAAC_M1UM_SHIFT (6U) -#define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK) -#define MPU_RGDAAC_M1SM_MASK (0x600U) -#define MPU_RGDAAC_M1SM_SHIFT (9U) -#define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK) -#define MPU_RGDAAC_M1PE (0x800U) -#define MPU_RGDAAC_M2UM_MASK (0x7000U) -#define MPU_RGDAAC_M2UM_SHIFT (12U) -#define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK) -#define MPU_RGDAAC_M2SM_MASK (0x18000U) -#define MPU_RGDAAC_M2SM_SHIFT (15U) -#define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK) -#define MPU_RGDAAC_M2PE (0x20000U) -#define MPU_RGDAAC_M3UM_MASK (0x1C0000U) -#define MPU_RGDAAC_M3UM_SHIFT (18U) -#define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK) -#define MPU_RGDAAC_M3SM_MASK (0x600000U) -#define MPU_RGDAAC_M3SM_SHIFT (21U) -#define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK) -#define MPU_RGDAAC_M3PE (0x800000U) -#define MPU_RGDAAC_M4WE (0x1000000U) -#define MPU_RGDAAC_M4RE (0x2000000U) -#define MPU_RGDAAC_M5WE (0x4000000U) -#define MPU_RGDAAC_M5RE (0x8000000U) -#define MPU_RGDAAC_M6WE (0x10000000U) -#define MPU_RGDAAC_M6RE (0x20000000U) -#define MPU_RGDAAC_M7WE (0x40000000U) -#define MPU_RGDAAC_M7RE (0x80000000U) +#define SYSMPU_RGDAAC_M0UM_MASK (0x7U) +#define SYSMPU_RGDAAC_M0UM_SHIFT (0U) +#define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK) +#define SYSMPU_RGDAAC_M0SM_MASK (0x18U) +#define SYSMPU_RGDAAC_M0SM_SHIFT (3U) +#define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK) +#define SYSMPU_RGDAAC_M0PE (0x20U) +#define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U) +#define SYSMPU_RGDAAC_M1UM_SHIFT (6U) +#define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK) +#define SYSMPU_RGDAAC_M1SM_MASK (0x600U) +#define SYSMPU_RGDAAC_M1SM_SHIFT (9U) +#define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK) +#define SYSMPU_RGDAAC_M1PE (0x800U) +#define SYSMPU_RGDAAC_M2UM_MASK (0x7000U) +#define SYSMPU_RGDAAC_M2UM_SHIFT (12U) +#define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK) +#define SYSMPU_RGDAAC_M2SM_MASK (0x18000U) +#define SYSMPU_RGDAAC_M2SM_SHIFT (15U) +#define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK) +#define SYSMPU_RGDAAC_M2PE (0x20000U) +#define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U) +#define SYSMPU_RGDAAC_M3UM_SHIFT (18U) +#define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK) +#define SYSMPU_RGDAAC_M3SM_MASK (0x600000U) +#define SYSMPU_RGDAAC_M3SM_SHIFT (21U) +#define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK) +#define SYSMPU_RGDAAC_M3PE (0x800000U) +#define SYSMPU_RGDAAC_M4WE (0x1000000U) +#define SYSMPU_RGDAAC_M4RE (0x2000000U) +#define SYSMPU_RGDAAC_M5WE (0x4000000U) +#define SYSMPU_RGDAAC_M5RE (0x8000000U) +#define SYSMPU_RGDAAC_M6WE (0x10000000U) +#define SYSMPU_RGDAAC_M6RE (0x20000000U) +#define SYSMPU_RGDAAC_M7WE (0x40000000U) +#define SYSMPU_RGDAAC_M7RE (0x80000000U) -/* The count of MPU_RGDAAC */ -#define MPU_RGDAAC_COUNT (12U) +/* The count of SYSMPU_RGDAAC */ +#define SYSMPU_RGDAAC_COUNT (12U) /*! * @} - */ /* end of group MPU_Register_Masks */ + */ /* end of group SYSMPU_Register_Masks */ -/* MPU - Peripheral instance base addresses */ -/** Peripheral MPU base address */ -#define MPU_BASE (0x4000D000u) -/** Peripheral MPU base pointer */ -#define MPU ((MPU_TypeDef *)MPU_BASE) -/** Array initializer of MPU peripheral base addresses */ -#define MPU_BASE_ADDRS { MPU_BASE } -/** Array initializer of MPU peripheral base pointers */ -#define MPU_BASE_PTRS { MPU } +/* SYSMPU - Peripheral instance base addresses */ +/** Peripheral SYSMPU base address */ +#define SYSMPU_BASE (0x4000D000u) +/** Peripheral SYSMPU base pointer */ +#define SYSMPU ((SYSMPU_TypeDef *)SYSMPU_BASE) +/** Array initializer of SYSMPU peripheral base addresses */ +#define SYSMPU_BASE_ADDRS { SYSMPU_BASE } +/** Array initializer of SYSMPU peripheral base pointers */ +#define SYSMPU_BASE_PTRS { SYSMPU } /*! * @} - */ /* end of group MPU_Peripheral_Access_Layer */ + */ /* end of group SYSMPU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- diff --git a/os/common/ext/CMSIS/KINETIS/system_MK64F12.h b/os/common/ext/CMSIS/KINETIS/system_MK64F12.h new file mode 100644 index 00000000..45328053 --- /dev/null +++ b/os/common/ext/CMSIS/KINETIS/system_MK64F12.h @@ -0,0 +1,168 @@ +/* +** ################################################################### +** Processor: MK64FN1M0VMD12 +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** GNU C Compiler - CodeSourcery Sourcery G++ +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.5, 2014-02-10 +** Build: b140611 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2013-08-12) +** Initial version. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** MCG - registers updated. +** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-09) +** DMA - EARS register removed. +** AIPS0, AIPS1 - MPRA register updated. +** - rev. 2.3 (2014-01-24) +** Update according to reference manual rev. 2 +** ENET, MCG, MCM, SIM, USB - registers updated +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK64F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** - rev. 2.5 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK64F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** +** ################################################################### +*/ + +/*! + * @file MK64F12 + * @version 2.5 + * @date 2014-02-10 + * @brief Device specific configuration file for MK64F12 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MK64F12_H_ +#define _SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Define clock source values */ + +#define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */ +#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ +#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ +#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ +#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */ + +/* RTC oscillator setting */ +/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */ +#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */ + +/* Low power mode enable */ +/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */ +#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */ + +#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MK64F12_H_ */ diff --git a/os/hal/boards/PJRC_TEENSY_3_5/board.h b/os/hal/boards/PJRC_TEENSY_3_5/board.h index efa0a563..b363167c 100644 --- a/os/hal/boards/PJRC_TEENSY_3_5/board.h +++ b/os/hal/boards/PJRC_TEENSY_3_5/board.h @@ -31,7 +31,7 @@ #define KINETIS_XTAL_FREQUENCY 16000000UL /* Use internal capacitors for the crystal */ -#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P +#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P|OSC_CR_ERCLKEN /* * MCU type @@ -52,16 +52,16 @@ #define TEENSY_PIN40 28 #define TEENSY_PIN41 29 -#define TEENSY_PIN25_IOPORT IOPORT1 +#define TEENSY_PIN40_IOPORT IOPORT1 +#define TEENSY_PIN41_IOPORT IOPORT1 +#define TEENSY_PIN42_IOPORT IOPORT1 #define TEENSY_PIN3_IOPORT IOPORT1 #define TEENSY_PIN4_IOPORT IOPORT1 +#define TEENSY_PIN25_IOPORT IOPORT1 #define TEENSY_PIN26_IOPORT IOPORT1 #define TEENSY_PIN27_IOPORT IOPORT1 #define TEENSY_PIN28_IOPORT IOPORT1 #define TEENSY_PIN39_IOPORT IOPORT1 -#define TEENSY_PIN42_IOPORT IOPORT1 -#define TEENSY_PIN40_IOPORT IOPORT1 -#define TEENSY_PIN41_IOPORT IOPORT1 #define TEENSY_PIN16 0 #define TEENSY_PIN17 1 @@ -80,22 +80,22 @@ #define TEENSY_PIN44 22 #define TEENSY_PIN45 23 -#define TEENSY_PIN16_IOPORT IOPORT2 -#define TEENSY_PIN17_IOPORT IOPORT2 -#define TEENSY_PIN19_IOPORT IOPORT2 -#define TEENSY_PIN18_IOPORT IOPORT2 #define TEENSY_PIN49_IOPORT IOPORT2 #define TEENSY_PIN50_IOPORT IOPORT2 -#define TEENSY_PIN31_IOPORT IOPORT2 -#define TEENSY_PIN32_IOPORT IOPORT2 +#define TEENSY_PIN43_IOPORT IOPORT2 +#define TEENSY_PIN44_IOPORT IOPORT2 +#define TEENSY_PIN45_IOPORT IOPORT2 +#define TEENSY_PIN46_IOPORT IOPORT2 #define TEENSY_PIN0_IOPORT IOPORT2 #define TEENSY_PIN1_IOPORT IOPORT2 #define TEENSY_PIN29_IOPORT IOPORT2 #define TEENSY_PIN30_IOPORT IOPORT2 -#define TEENSY_PIN43_IOPORT IOPORT2 -#define TEENSY_PIN46_IOPORT IOPORT2 -#define TEENSY_PIN44_IOPORT IOPORT2 -#define TEENSY_PIN45_IOPORT IOPORT2 +#define TEENSY_PIN31_IOPORT IOPORT2 +#define TEENSY_PIN32_IOPORT IOPORT2 +#define TEENSY_PIN16_IOPORT IOPORT2 +#define TEENSY_PIN17_IOPORT IOPORT2 +#define TEENSY_PIN19_IOPORT IOPORT2 +#define TEENSY_PIN18_IOPORT IOPORT2 #define TEENSY_PIN15 0 #define TEENSY_PIN22 1 @@ -110,18 +110,18 @@ #define TEENSY_PIN37 10 #define TEENSY_PIN38 11 -#define TEENSY_PIN15_IOPORT IOPORT3 -#define TEENSY_PIN22_IOPORT IOPORT3 -#define TEENSY_PIN23_IOPORT IOPORT3 #define TEENSY_PIN9_IOPORT IOPORT3 #define TEENSY_PIN10_IOPORT IOPORT3 -#define TEENSY_PIN13_IOPORT IOPORT3 #define TEENSY_PIN11_IOPORT IOPORT3 #define TEENSY_PIN12_IOPORT IOPORT3 #define TEENSY_PIN35_IOPORT IOPORT3 #define TEENSY_PIN36_IOPORT IOPORT3 #define TEENSY_PIN37_IOPORT IOPORT3 #define TEENSY_PIN38_IOPORT IOPORT3 +#define TEENSY_PIN13_IOPORT IOPORT3 +#define TEENSY_PIN15_IOPORT IOPORT3 +#define TEENSY_PIN22_IOPORT IOPORT3 +#define TEENSY_PIN23_IOPORT IOPORT3 #define TEENSY_PIN2 0 #define TEENSY_PIN14 1 @@ -139,21 +139,21 @@ #define TEENSY_PIN51 14 #define TEENSY_PIN54 15 -#define TEENSY_PIN2_IOPORT IOPORT4 -#define TEENSY_PIN14_IOPORT IOPORT4 -#define TEENSY_PIN7_IOPORT IOPORT4 -#define TEENSY_PIN8_IOPORT IOPORT4 -#define TEENSY_PIN6_IOPORT IOPORT4 -#define TEENSY_PIN20_IOPORT IOPORT4 -#define TEENSY_PIN21_IOPORT IOPORT4 -#define TEENSY_PIN5_IOPORT IOPORT4 +#define TEENSY_PIN51_IOPORT IOPORT4 +#define TEENSY_PIN52_IOPORT IOPORT4 +#define TEENSY_PIN53_IOPORT IOPORT4 +#define TEENSY_PIN54_IOPORT IOPORT4 +#define TEENSY_PIN55_IOPORT IOPORT4 #define TEENSY_PIN47_IOPORT IOPORT4 #define TEENSY_PIN48_IOPORT IOPORT4 -#define TEENSY_PIN55_IOPORT IOPORT4 -#define TEENSY_PIN53_IOPORT IOPORT4 -#define TEENSY_PIN52_IOPORT IOPORT4 -#define TEENSY_PIN51_IOPORT IOPORT4 -#define TEENSY_PIN54_IOPORT IOPORT4 +#define TEENSY_PIN2_IOPORT IOPORT4 +#define TEENSY_PIN5_IOPORT IOPORT4 +#define TEENSY_PIN6_IOPORT IOPORT4 +#define TEENSY_PIN7_IOPORT IOPORT4 +#define TEENSY_PIN8_IOPORT IOPORT4 +#define TEENSY_PIN14_IOPORT IOPORT4 +#define TEENSY_PIN20_IOPORT IOPORT4 +#define TEENSY_PIN21_IOPORT IOPORT4 #define TEENSY_PIN56 10 #define TEENSY_PIN57 11 @@ -163,9 +163,9 @@ #define TEENSY_PIN56_IOPORT IOPORT5 #define TEENSY_PIN57_IOPORT IOPORT5 +#define TEENSY_PIN24_IOPORT IOPORT5 #define TEENSY_PIN33_IOPORT IOPORT5 #define TEENSY_PIN34_IOPORT IOPORT5 -#define TEENSY_PIN24_IOPORT IOPORT5 #define LINE_PIN0 PAL_LINE(TEENSY_PIN0_IOPORT, TEENSY_PIN0) #define LINE_PIN1 PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1) diff --git a/os/hal/ports/KINETIS/K60x/hal_lld.c b/os/hal/ports/KINETIS/K60x/hal_lld.c index cfe633bd..9ba82a6f 100644 --- a/os/hal/ports/KINETIS/K60x/hal_lld.c +++ b/os/hal/ports/KINETIS/K60x/hal_lld.c @@ -82,6 +82,11 @@ const uint8_t _cfm[0x10] = { */ void hal_lld_init(void) { +#if defined(K64F) + /* Disable the MPU by default */ + SYSMPU->CESR &= ~SYSMPU_CESR_VLD; +#endif + } /** @@ -216,7 +221,9 @@ void k60x_clock_init(void) { SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) | SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1); SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); - SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL_IRC48M; /* FIXME ? Why this? */ + + /* Configure peripherals to use MCGPLLCLK */ + SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL_MCGPLL; /* Switch to PLL as clock source */ MCG->C1 = MCG_C1_CLKS(0); diff --git a/os/hal/ports/KINETIS/K60x/hal_lld.h b/os/hal/ports/KINETIS/K60x/hal_lld.h index 8da89b30..ac1a083f 100644 --- a/os/hal/ports/KINETIS/K60x/hal_lld.h +++ b/os/hal/ports/KINETIS/K60x/hal_lld.h @@ -119,6 +119,21 @@ #endif #endif +/** + * @brief Clock divider for FlexBus clock (OUTDIV3). + * @note The allowed range is 1..16 + * @note The default value is calculated for a 48 MHz clock + * from a 96 MHz PLL output. + */ +#if !defined(KINETIS_CLKDIV1_OUTDIV3) || defined(__DOXYGEN__) + #if defined(KINETIS_FLEXBUSCLK_FREQUENCY) && KINETIS_FLEXBUSCLK_FREQUENCY > 0 + #define KINETIS_CLKDIV1_OUTDIV3 (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLEXBUSCLK_FREQUENCY) + #else + /* If no FlexBus frequency provided, use bus speed divider */ + #define KINETIS_CLKDIV1_OUTDIV3 KINETIS_CLKDIV1_OUTDIV2 + #endif +#endif + /** * @brief Clock divider for flash clock (OUTDIV4). * @note The allowed range is 1..16 @@ -228,6 +243,11 @@ #error KINETIS_CLKDIV1_OUTDIV2 must be 1 through 16 #endif +#if !(defined(KINETIS_CLKDIV1_OUTDIV3) && \ + KINETIS_CLKDIV1_OUTDIV3 >= 1 && KINETIS_CLKDIV1_OUTDIV3 <= 16) +#error KINETIS_CLKDIV1_OUTDIV3 must be 1 through 16 +#endif + #if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \ KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16) #error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16 diff --git a/os/hal/ports/KINETIS/K60x/platform.mk b/os/hal/ports/KINETIS/K60x/platform.mk index 978d8df7..de31fd4b 100644 --- a/os/hal/ports/KINETIS/K60x/platform.mk +++ b/os/hal/ports/KINETIS/K60x/platform.mk @@ -19,11 +19,11 @@ endif include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/GPIOv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/UARTv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/I2Cv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PORTv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ADCv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SDHCv1/driver.mk -include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/I2Cv1/driver.mk -include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ADCv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/USBHSv1/driver.mk # Shared variables diff --git a/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c index da75f0c5..3ba2b7c1 100644 --- a/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c +++ b/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c @@ -407,7 +407,7 @@ void usb_lld_init(void) { #elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE -#if !defined(MK66F18) +#if !defined(MK66F18) && !defined(K64F) /* Note: We don't need this for MK66F18, we can use IRC48M clock for USB */ #define KINETIS_USBCLK_FREQUENCY 48000000UL uint32_t i,j; @@ -427,6 +427,12 @@ void usb_lld_init(void) { #error USB clock setting not implemented for this KINETIS_MCG_MODE #endif /* KINETIS_MCG_MODE == ... */ +#if defined(K64F) + /* Switch from default MCGPLLCLK to IRC48M for USB */ + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); + SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_IRC48M; +#endif + #if defined(MK66F18) /* Switch from default MCGPLLCLK to IRC48M for USB */ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); From 59c69afd89f06848606478fb10d351cd256cbf99 Mon Sep 17 00:00:00 2001 From: fauxpark Date: Fri, 19 Nov 2021 20:44:14 +1100 Subject: [PATCH 2/4] Comment out switch to IRC48M for now, set USBDIV to /2 (assume 96MHz clock) --- os/hal/ports/KINETIS/K60x/hal_lld.c | 2 +- os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/os/hal/ports/KINETIS/K60x/hal_lld.c b/os/hal/ports/KINETIS/K60x/hal_lld.c index 9ba82a6f..45b20132 100644 --- a/os/hal/ports/KINETIS/K60x/hal_lld.c +++ b/os/hal/ports/KINETIS/K60x/hal_lld.c @@ -220,7 +220,7 @@ void k60x_clock_init(void) { SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) | SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) | SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1); - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1); /* Configure peripherals to use MCGPLLCLK */ SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL_MCGPLL; diff --git a/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c index 3ba2b7c1..e8838c16 100644 --- a/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c +++ b/os/hal/ports/KINETIS/LLD/USBHSv1/hal_usb_lld.c @@ -429,8 +429,8 @@ void usb_lld_init(void) { #if defined(K64F) /* Switch from default MCGPLLCLK to IRC48M for USB */ - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); - SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_IRC48M; + //SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); + //SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_IRC48M; #endif #if defined(MK66F18) From c86935b81f2a0fd5bd4a0a3dac8beb3ad1ed35c9 Mon Sep 17 00:00:00 2001 From: fauxpark Date: Fri, 19 Nov 2021 21:57:12 +1100 Subject: [PATCH 3/4] Modifications to run at 120MHz --- os/hal/ports/KINETIS/K60x/hal_lld.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/os/hal/ports/KINETIS/K60x/hal_lld.c b/os/hal/ports/KINETIS/K60x/hal_lld.c index 45b20132..1efa47aa 100644 --- a/os/hal/ports/KINETIS/K60x/hal_lld.c +++ b/os/hal/ports/KINETIS/K60x/hal_lld.c @@ -186,9 +186,9 @@ void k60x_clock_init(void) { /* * Now in FBE mode */ - #define KINETIS_PLLIN_FREQUENCY 2000000UL + #define KINETIS_PLLIN_FREQUENCY 4000000UL /* - * Config PLL input for 2 MHz + * Config PLL input for 4 MHz * TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz */ MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1); @@ -220,7 +220,7 @@ void k60x_clock_init(void) { SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) | SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) | SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1); - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1); + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC; /* Configure peripherals to use MCGPLLCLK */ SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL_MCGPLL; From 3d85866587ff5a6e82b4040381c401b100516219 Mon Sep 17 00:00:00 2001 From: fauxpark Date: Fri, 19 Nov 2021 22:18:40 +1100 Subject: [PATCH 4/4] No need for system_MK64F12.h --- os/common/ext/CMSIS/KINETIS/k64f.h | 1 - os/common/ext/CMSIS/KINETIS/system_MK64F12.h | 168 ------------------- 2 files changed, 169 deletions(-) delete mode 100644 os/common/ext/CMSIS/KINETIS/system_MK64F12.h diff --git a/os/common/ext/CMSIS/KINETIS/k64f.h b/os/common/ext/CMSIS/KINETIS/k64f.h index 0eb67acc..76285dec 100644 --- a/os/common/ext/CMSIS/KINETIS/k64f.h +++ b/os/common/ext/CMSIS/KINETIS/k64f.h @@ -284,7 +284,6 @@ typedef enum IRQn { #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_MK64F12.h" /* Device specific configuration file */ /*! * @} diff --git a/os/common/ext/CMSIS/KINETIS/system_MK64F12.h b/os/common/ext/CMSIS/KINETIS/system_MK64F12.h deleted file mode 100644 index 45328053..00000000 --- a/os/common/ext/CMSIS/KINETIS/system_MK64F12.h +++ /dev/null @@ -1,168 +0,0 @@ -/* -** ################################################################### -** Processor: MK64FN1M0VMD12 -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 -** Version: rev. 2.5, 2014-02-10 -** Build: b140611 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright (c) 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2013-08-12) -** Initial version. -** - rev. 2.0 (2013-10-29) -** Register accessor macros added to the memory map. -** Symbols for Processor Expert memory map compatibility added to the memory map. -** Startup file for gcc has been updated according to CMSIS 3.2. -** System initialization updated. -** MCG - registers updated. -** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. -** - rev. 2.1 (2013-10-30) -** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. -** - rev. 2.2 (2013-12-09) -** DMA - EARS register removed. -** AIPS0, AIPS1 - MPRA register updated. -** - rev. 2.3 (2014-01-24) -** Update according to reference manual rev. 2 -** ENET, MCG, MCM, SIM, USB - registers updated -** - rev. 2.4 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** - rev. 2.5 (2014-02-10) -** The declaration of clock configurations has been moved to separate header file system_MK64F12.h -** Update of SystemInit() and SystemCoreClockUpdate() functions. -** Module access macro module_BASES replaced by module_BASE_PTRS. -** -** ################################################################### -*/ - -/*! - * @file MK64F12 - * @version 2.5 - * @date 2014-02-10 - * @brief Device specific configuration file for MK64F12 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_MK64F12_H_ -#define _SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -#ifndef DISABLE_WDOG - #define DISABLE_WDOG 1 -#endif - -/* Define clock source values */ - -#define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */ -#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ -#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ -#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ -#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */ - -/* RTC oscillator setting */ -/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */ -#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */ - -/* Low power mode enable */ -/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */ -#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */ - -#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -/** - * @brief SystemInit function hook. - * - * This weak function allows to call specific initialization code during the - * SystemInit() execution.This can be used when an application specific code needs - * to be called as close to the reset entry as possible (for example the Multicore - * Manager MCMGR_EarlyInit() function call). - * NOTE: No global r/w variables can be used in this hook function because the - * initialization of these variables happens after this function. - */ -void SystemInitHook (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_MK64F12_H_ */