From 325bd43323d7ff3af2198bd6bbeab75cc5773737 Mon Sep 17 00:00:00 2001 From: codetector Date: Thu, 26 Nov 2020 16:04:08 -0500 Subject: [PATCH] [LPC11Uxx]: Initial Support: RT + HAL ClockInit --- AUTHORS.txt | 13 +- os/common/ext/CMSIS/LPC/LPC11Uxx.h | 694 ++++++++++++++++++ .../ARMCMx/compilers/GCC/ld/LPC11U35_401.ld | 104 +++ .../compilers/GCC/mk/startup_lpc11uxx.mk | 20 + .../ARMCMx/devices/LPC11Uxx/cmparams.h | 81 ++ os/hal/ports/LPC/LLD/STM/driver.mk | 5 + os/hal/ports/LPC/LLD/STM/hal_st_lld.c | 100 +++ os/hal/ports/LPC/LLD/STM/hal_st_lld.h | 154 ++++ os/hal/ports/LPC/LPC11Uxx/hal_lld.c | 94 +++ os/hal/ports/LPC/LPC11Uxx/hal_lld.h | 159 ++++ os/hal/ports/LPC/LPC11Uxx/lpc_registry.h | 48 ++ os/hal/ports/LPC/LPC11Uxx/platform.mk | 13 + 12 files changed, 1480 insertions(+), 5 deletions(-) create mode 100644 os/common/ext/CMSIS/LPC/LPC11Uxx.h create mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/LPC11U35_401.ld create mode 100644 os/common/startup/ARMCMx/compilers/GCC/mk/startup_lpc11uxx.mk create mode 100644 os/common/startup/ARMCMx/devices/LPC11Uxx/cmparams.h create mode 100644 os/hal/ports/LPC/LLD/STM/driver.mk create mode 100644 os/hal/ports/LPC/LLD/STM/hal_st_lld.c create mode 100644 os/hal/ports/LPC/LLD/STM/hal_st_lld.h create mode 100644 os/hal/ports/LPC/LPC11Uxx/hal_lld.c create mode 100644 os/hal/ports/LPC/LPC11Uxx/hal_lld.h create mode 100644 os/hal/ports/LPC/LPC11Uxx/lpc_registry.h create mode 100644 os/hal/ports/LPC/LPC11Uxx/platform.mk diff --git a/AUTHORS.txt b/AUTHORS.txt index 73053a35..09f64c1b 100644 --- a/AUTHORS.txt +++ b/AUTHORS.txt @@ -2,19 +2,19 @@ Joel Bodenmann aka Tectu https://github.com/Tectu Git repository maintainer -Uladzimir Pylinsky aka barthess +Uladzimir Pylinsky aka barthess https://github.com/barthess Git repository maintainer -Marco Veeneman aka Marco +Marco Veeneman aka Marco https://github.com/marcoveeneman -Maintainer of the ChibiOS port for the Texas Instruments +Maintainer of the ChibiOS port for the Texas Instruments Tiva C Series Microcontrollers -Fabien Poussin aka fpoussin +Fabien Poussin aka fpoussin https://github.com/fpoussin -Matthias Blaicher aka mabl +Matthias Blaicher aka mabl https://github.com/mabl Andrea Zoppi aka TexZK @@ -23,3 +23,6 @@ https://github.com/TexZK Diego Ismirlian aka dismirlian https://github.com/dismirlian USB Host stack author + +Yaotian Feng aka Codetector +https://github.com/Codetector1374 diff --git a/os/common/ext/CMSIS/LPC/LPC11Uxx.h b/os/common/ext/CMSIS/LPC/LPC11Uxx.h new file mode 100644 index 00000000..50cf9fab --- /dev/null +++ b/os/common/ext/CMSIS/LPC/LPC11Uxx.h @@ -0,0 +1,694 @@ + +/****************************************************************************************************//** + * @file LPC11Uxx.h + * + * + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for + * default LPC11Uxx Device Series + * + * @version V0.1 + * @date 21. March 2011 + * + * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45 + * + * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1, + * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40 + * + *******************************************************************************************************/ + +/** @addtogroup NXP + * @{ + */ + +/** @addtogroup LPC11Uxx + * @{ + */ + +#ifndef __LPC11UXX_H__ +#define __LPC11UXX_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + + /* Interrupt Number Definition */ + +typedef enum { +// ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------ + FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */ + FLEX_INT1_IRQn = 1, + FLEX_INT2_IRQn = 2, + FLEX_INT3_IRQn = 3, + FLEX_INT4_IRQn = 4, + FLEX_INT5_IRQn = 5, + FLEX_INT6_IRQn = 6, + FLEX_INT7_IRQn = 7, + GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */ + GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */ + Reserved0_IRQn = 10, /*!< Reserved Interrupt */ + Reserved1_IRQn = 11, + Reserved2_IRQn = 12, + Reserved3_IRQn = 13, + SSP1_IRQn = 14, /*!< SSP1 Interrupt */ + I2C_IRQn = 15, /*!< I2C Interrupt */ + TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */ + TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */ + TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */ + TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */ + SSP0_IRQn = 20, /*!< SSP0 Interrupt */ + UART_IRQn = 21, /*!< UART Interrupt */ + USB_IRQn = 22, /*!< USB IRQ Interrupt */ + USB_FIQn = 23, /*!< USB FIQ Interrupt */ + ADC_IRQn = 24, /*!< A/D Converter Interrupt */ + WDT_IRQn = 25, /*!< Watchdog timer Interrupt */ + BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */ + FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */ + Reserved4_IRQn = 28, /*!< Reserved Interrupt */ + Reserved5_IRQn = 29, /*!< Reserved Interrupt */ + USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */ + Reserved6_IRQn = 31, /*!< Reserved Interrupt */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */ + +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +// ------------------------------------------------------------------------------------------------ +// ----- I2C ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C) + */ + +typedef struct { /*!< (@ 0x40000000) I2C Structure */ + __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */ + __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */ + __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */ + __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */ + __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */ + __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */ + __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/ + __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/ + __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/ + __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/ + __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/ + __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */ +union{ + __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */ + struct{ + __IO uint32_t MASK0; + __IO uint32_t MASK1; + __IO uint32_t MASK2; + __IO uint32_t MASK3; + }; + }; +} LPC_I2C_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- WWDT ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT) + */ + +typedef struct { /*!< (@ 0x40004000) WWDT Structure */ + __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/ + __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */ + __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */ + __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */ + __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */ + __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */ + __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */ +} LPC_WWDT_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- USART ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART) + */ + +typedef struct { /*!< (@ 0x40008000) USART Structure */ + + union { + __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ + __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */ + __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */ + }; + + union { + __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */ + __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ + }; + + union { + __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */ + __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ + }; + __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */ + __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */ + __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ + __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */ + __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */ + __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ + __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */ + __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ + __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */ + __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */ + __I uint32_t RESERVED0[3]; + __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */ + __I uint32_t RESERVED1; + __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */ + __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ + __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ + __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */ + __IO uint32_t SYNCCTRL; +} LPC_USART_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- Timer ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3 + */ + +typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */ + __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */ + __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */ + __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */ + __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */ + __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */ + __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */ + union { + __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */ + struct{ + __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */ + __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */ + __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */ + __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */ + }; + }; + __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */ + union{ + __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */ + struct{ + __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */ + __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */ + __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */ + __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */ + }; + }; +__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */ + __I uint32_t RESERVED0[12]; + __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */ + __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */ +} LPC_CTxxBx_Type; + + + +// ------------------------------------------------------------------------------------------------ +// ----- ADC ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC) + */ + +typedef struct { /*!< (@ 0x4001C000) ADC Structure */ + __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */ + __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */ + __I uint32_t RESERVED0[1]; + __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */ + union{ + __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/ + struct{ + __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/ + __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/ + __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/ + __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/ + __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/ + __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/ + __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/ + __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/ + }; + }; + __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */ +} LPC_ADC_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- PMU ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU) + */ + +typedef struct { /*!< (@ 0x40038000) PMU Structure */ + __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */ + union{ + __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */ + struct{ + __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */ + __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */ + __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */ + __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */ + }; + }; +} LPC_PMU_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- FLASHCTRL ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL) + */ + +typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */ + __I uint32_t RESERVED0[4]; + __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */ + __I uint32_t RESERVED1[3]; + __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */ + __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */ + __I uint32_t RESERVED2[1]; + __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */ + __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */ + __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */ + __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */ + __I uint32_t RESERVED3[1001]; + __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */ + __I uint32_t RESERVED4[1]; + __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */ +} LPC_FLASHCTRL_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- SSP0/1 ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0) + */ + +typedef struct { /*!< (@ 0x40040000) SSP0 Structure */ + __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */ + __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */ + __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ + __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */ + __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */ + __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */ + __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */ + __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */ + __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */ +} LPC_SSPx_Type; + + + +// ------------------------------------------------------------------------------------------------ +// ----- IOCONFIG ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) + */ + +typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ + __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */ + __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */ + __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */ + __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */ + __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */ + __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */ + __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */ + __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */ + __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */ + __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */ + __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */ + __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */ + __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */ + __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */ + __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */ + __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */ + __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */ + __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */ + __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */ + __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */ + __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */ + __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */ + __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */ + __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */ + __IO uint32_t PIO1_0; /*!< Offset: 0x060 */ + __IO uint32_t PIO1_1; + __IO uint32_t PIO1_2; + __IO uint32_t PIO1_3; + __IO uint32_t PIO1_4; /*!< Offset: 0x070 */ + __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */ + __IO uint32_t PIO1_6; + __IO uint32_t PIO1_7; + __IO uint32_t PIO1_8; /*!< Offset: 0x080 */ + __IO uint32_t PIO1_9; + __IO uint32_t PIO1_10; + __IO uint32_t PIO1_11; + __IO uint32_t PIO1_12; /*!< Offset: 0x090 */ + __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */ + __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */ + __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */ + __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */ + __IO uint32_t PIO1_17; + __IO uint32_t PIO1_18; + __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */ + __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */ + __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */ + __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */ + __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */ + __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */ + __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */ + __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */ + __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */ + __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */ + __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */ + __IO uint32_t PIO1_30; + __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */ +} LPC_IOCON_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- SYSCON ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON) + */ + +typedef struct { /*!< (@ 0x40048000) SYSCON Structure */ + __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */ + __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */ + __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */ + __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */ + __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */ + __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */ + __I uint32_t RESERVED0[2]; + __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */ + __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */ + __I uint32_t RESERVED1[2]; + __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */ + __I uint32_t RESERVED2[3]; + __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */ + __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */ + __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */ + __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */ + __I uint32_t RESERVED3[8]; + __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */ + __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */ + __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */ + __I uint32_t RESERVED4[1]; + __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */ + __I uint32_t RESERVED5[4]; + __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */ + __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */ + __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */ + __I uint32_t RESERVED6[8]; + __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */ + __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */ + __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */ + __I uint32_t RESERVED7[5]; + __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */ + __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */ + __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */ + __I uint32_t RESERVED8[5]; + __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */ + __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */ + __I uint32_t RESERVED9[18]; + __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */ + __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */ + __I uint32_t RESERVED10[6]; + __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */ + __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ + __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ + __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */ + __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */ + __I uint32_t RESERVED11[25]; + __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */ + __I uint32_t RESERVED12[3]; + __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */ + __I uint32_t RESERVED13[6]; + __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */ + __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */ + __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */ + __I uint32_t RESERVED14[110]; + __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */ +} LPC_SYSCON_Type; + +// SYSCON_SYSPLLCTRL +#define SYSCON_SYSPLLCTRL_MSEL_POS 0U +#define SYSCON_SYSPLLCTRL_MSEL_MASK 0x1FU << SYSPLLCTRL_MSEL_POS +#define SYSCON_SYSPLLCTRL_PSEL_POS 5U +#define SYSCON_SYSPLLCTRL_PSEL_MASK 0x03U << SYSPLLCTRL_PSEL_POS +// SYSCON_SYSPLLSTAT +#define SYSCON_SYSPLLSTAT_LOCK 0x1 +// SYSCON_SYSPLLCLKSEL +#define SYSCON_SYSPLLCLKSEL_IRC 0x00U << 0 +#define SYSCON_SYSPLLCLKSEL_SYSOSC 0x01U << 0 + +#define SYSCON_SYSPLLCLKUEN_ENA 0x01 + +#define SYSCON_MAINCLKSEL_IRC 0x00U << 0 +#define SYSCON_MAINCLKSEL_PLLIN 0x01U << 0 +#define SYSCON_MAINCLKSEL_WATCHDOG 0x02U << 0 +#define SYSCON_MAINCLKSEL_PLLOUT 0x03U << 0 + +#define SYSCON_MAINCLKUEN_ENA 0x01 + +#define SYS_CON_PDRUNCFG_IRCOUT_PD 0x1U << 0U +#define SYS_CON_PDRUNCFG_IRC_PD 0x1U << 1U +#define SYS_CON_PDRUNCFG_FLASH_PD 0x1U << 2U +#define SYS_CON_PDRUNCFG_BOD_PD 0x1U << 3U +#define SYS_CON_PDRUNCFG_ADC_PD 0x1U << 4U +#define SYS_CON_PDRUNCFG_SYSSOC_PD 0x1U << 5U +#define SYS_CON_PDRUNCFG_WDTOSC_PD 0x1U << 6U +#define SYS_CON_PDRUNCFG_SYSPLL_PD 0x1U << 7U +#define SYS_CON_PDRUNCFG_USBPLL_PD 0x1U << 8U +#define SYS_CON_PDRUNCFG_USBPAD_PD 0x1U << 10U +// ------------------------------------------------------------------------------------------------ +// ----- GPIO_PIN_INT ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT) + */ + +typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */ + __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */ + __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */ + __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */ + __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */ + __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */ + __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */ + __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ + __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */ + __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */ + __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */ +} LPC_GPIO_PIN_INT_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- GPIO_GROUP_INT0/1 ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0) + */ + +typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */ + __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */ + __I uint32_t RESERVED0[7]; + __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */ + __I uint32_t RESERVED1[6]; + __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */ +} LPC_GPIO_GROUP_INTx_Type; + + + +// ------------------------------------------------------------------------------------------------ +// ----- USB ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB) + */ + +typedef struct { /*!< (@ 0x40080000) USB Structure */ + __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */ + __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */ + __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */ + __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */ + __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */ + __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */ + __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */ + __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */ + __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */ + __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */ + __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */ + __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */ + __I uint32_t RESERVED0[1]; + __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */ +} LPC_USB_Type; + + +// ------------------------------------------------------------------------------------------------ +// ----- GPIO_PORT ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) + */ + +typedef struct { + union { + struct { + __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */ + __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */ + }; + __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */ + }; + __I uint32_t RESERVED0[1008]; + union { + struct { + __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */ + __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */ + }; + __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */ + }; + uint32_t RESERVED1[960]; + __IO uint32_t DIR[2]; /* 0x2000 */ + uint32_t RESERVED2[30]; + __IO uint32_t MASK[2]; /* 0x2080 */ + uint32_t RESERVED3[30]; + __IO uint32_t PIN[2]; /* 0x2100 */ + uint32_t RESERVED4[30]; + __IO uint32_t MPIN[2]; /* 0x2180 */ + uint32_t RESERVED5[30]; + __IO uint32_t SET[2]; /* 0x2200 */ + uint32_t RESERVED6[30]; + __O uint32_t CLR[2]; /* 0x2280 */ + uint32_t RESERVED7[30]; + __O uint32_t NOT[2]; /* 0x2300 */ +} LPC_GPIO_Type; + + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + + +// ------------------------------------------------------------------------------------------------ +// ----- Peripheral memory map ----- +// ------------------------------------------------------------------------------------------------ + +#define LPC_I2C_BASE (0x40000000) +#define LPC_WWDT_BASE (0x40004000) +#define LPC_USART_BASE (0x40008000) +#define LPC_CT16B0_BASE (0x4000C000) +#define LPC_CT16B1_BASE (0x40010000) +#define LPC_CT32B0_BASE (0x40014000) +#define LPC_CT32B1_BASE (0x40018000) +#define LPC_ADC_BASE (0x4001C000) +#define LPC_PMU_BASE (0x40038000) +#define LPC_FLASHCTRL_BASE (0x4003C000) +#define LPC_SSP0_BASE (0x40040000) +#define LPC_SSP1_BASE (0x40058000) +#define LPC_IOCON_BASE (0x40044000) +#define LPC_SYSCON_BASE (0x40048000) +#define LPC_GPIO_PIN_INT_BASE (0x4004C000) +#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000) +#define LPC_GPIO_GROUP_INT1_BASE (0x40060000) +#define LPC_USB_BASE (0x40080000) +#define LPC_GPIO_BASE (0x50000000) + + +// ------------------------------------------------------------------------------------------------ +// ----- Peripheral declaration ----- +// ------------------------------------------------------------------------------------------------ + +#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE) +#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) +#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE) +#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE) +#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE) +#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE) +#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE) +#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE) +#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE) +#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE) +#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE) +#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE) +#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE) +#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE) +#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE) +#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE) +#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE) +#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE) +#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group (null) */ +/** @} */ /* End of group LPC11Uxx */ + +#ifdef __cplusplus +} +#endif + + +#endif // __LPC11UXX_H__ diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/LPC11U35_401.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/LPC11U35_401.ld new file mode 100644 index 00000000..a6757a2c --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/LPC11U35_401.ld @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2020 Yaotian Feng / Codetector + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +/* + * LPC11U35_401 memory setup + */ + + + +MEMORY { + flash0 : org = 0x00000000, len = 64k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x10000000, len = 8k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +Vector1C = (0 - + ((__main_stack_end__) + + (Reset_Handler + 1) + + (NMI_Handler + 1) + + (HardFault_Handler + 1) + + (MemManage_Handler + 1) + + (BusFault_Handler + 1) + + (UsageFault_Handler + 1)) + ); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_lpc11uxx.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_lpc11uxx.mk new file mode 100644 index 00000000..837b752f --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_lpc11uxx.mk @@ -0,0 +1,20 @@ +# List of the ChibiOS generic LPC11Uxx startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c + + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + + +STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/LPC11Uxx \ + $(CHIBIOS)/os/common/ext/CMSIS/include \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/LPC + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) diff --git a/os/common/startup/ARMCMx/devices/LPC11Uxx/cmparams.h b/os/common/startup/ARMCMx/devices/LPC11Uxx/cmparams.h new file mode 100644 index 00000000..cb399b0f --- /dev/null +++ b/os/common/startup/ARMCMx/devices/LPC11Uxx/cmparams.h @@ -0,0 +1,81 @@ +/* + ChibiOS - Copyright (C) 2020 Yaotian Feng / Codetector + + This file is part of ChibiOS. + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC11Uxx/cmparams.h + * @brief ARM Cortex-M0 parameters for the NXP LPC11Uxx family. + * + * @defgroup ARMCMx_LPC11Uxx NXP Semi. LPC11Uxx. + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * NRF51x platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 0 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 32 + +#define LPC_VECTOR_CHECKSUM TRUE + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "LPC11Uxx.h" + +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/hal/ports/LPC/LLD/STM/driver.mk b/os/hal/ports/LPC/LLD/STM/driver.mk new file mode 100644 index 00000000..90a812f8 --- /dev/null +++ b/os/hal/ports/LPC/LLD/STM/driver.mk @@ -0,0 +1,5 @@ +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/LPC/LLD/STM/hal_st_lld.c + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/LPC/LLD/STM + + diff --git a/os/hal/ports/LPC/LLD/STM/hal_st_lld.c b/os/hal/ports/LPC/LLD/STM/hal_st_lld.c new file mode 100644 index 00000000..04dd4877 --- /dev/null +++ b/os/hal/ports/LPC/LLD/STM/hal_st_lld.c @@ -0,0 +1,100 @@ +/* + ChibiOS - Copyright (C) 2020 Yaotian Feng / Codetector + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_st_lld.c + * @brief LPC11Uxx ST subsystem low level driver source. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__) +/** + * @brief System Timer vector. + * @details This interrupt is used for system tick in periodic mode. + * + * @isr + */ +OSAL_IRQ_HANDLER(SysTick_Handler) { + OSAL_IRQ_PROLOGUE(); + + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) { +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + #ifndef LPC_SYS_FREQUENCY + #error "No LPC_SYS_FREQUENCY defined" + #endif + /* Periodic systick mode, the Cortex-Mx internal systick timer is used + in this mode.*/ + SysTick->LOAD = (LPC_SYS_FREQUENCY / OSAL_ST_FREQUENCY) - 1; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + SysTick->VAL = 0; + + /* IRQ enabled.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, LPC_ST_IRQ_PRIORITY); +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ +} + +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** @} */ diff --git a/os/hal/ports/LPC/LLD/STM/hal_st_lld.h b/os/hal/ports/LPC/LLD/STM/hal_st_lld.h new file mode 100644 index 00000000..a12571ce --- /dev/null +++ b/os/hal/ports/LPC/LLD/STM/hal_st_lld.h @@ -0,0 +1,154 @@ +/* + ChibiOS - Copyright (C) 2020 Yaotian Feng / Codetector + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_st_lld.h + * @brief PLATFORM ST subsystem low level driver header. + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H +#define HAL_ST_LLD_H + +#include "hal.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SysTick timer IRQ priority. + */ +#if !defined(LPC_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_ST_IRQ_PRIORITY 8 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void st_lld_init(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) { + return (systime_t) SysTick->VAL; +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] abstime the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t abstime) { + SysTick->LOAD = (uint32_t)abstime; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | // No External Clock + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + SysTick->VAL = 0; // Trigger reload +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) { + SysTick->CTRL &= ~((uint32_t)0b10); +} + +/** + * @brief Sets the alarm time. + * + * @param[in] abstime the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t abstime) { + SysTick->VAL = (uint32_t)abstime; +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) { + return (systime_t)SysTick->LOAD; +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) { + return ((SysTick->CTRL & 0b10) != 0); +} + +#endif /* HAL_ST_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/LPC/LPC11Uxx/hal_lld.c b/os/hal/ports/LPC/LPC11Uxx/hal_lld.c new file mode 100644 index 00000000..58c21578 --- /dev/null +++ b/os/hal/ports/LPC/LPC11Uxx/hal_lld.c @@ -0,0 +1,94 @@ +/* + ChibiOS - Copyright (C) 2020 Yaotian Feng / Codetector + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.c + * @brief PLATFORM HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" + + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +void lpc_clock_init(void) { + #if LPC_MAINCLKSEL == SYSCON_MAINCLKSEL_PLLOUT ||\ + LPC_MAINCLKSEL == SYSCON_MAINCLKSEL_PLLIN + // 1. Config PLL input clock + LPC_SYSCON->SYSPLLCLKSEL = LPC_SYSPLLCLKSEL; + // Switch Clock + LPC_SYSCON->SYSPLLCLKUEN = 0; + LPC_SYSCON->SYSPLLCLKUEN = SYSCON_SYSPLLCLKUEN_ENA; + + #if LPC_MAINCLKSEL == SYSCON_MAINCLKSEL_PLLOUT + + // 2. Config PLL + // Enable PLL power + LPC_SYSCON->PDRUNCFG &= (~SYS_CON_PDRUNCFG_SYSPLL_PD); + // Apply PLL Config + LPC_SYSCON->SYSPLLCTRL = (LPC_SYSPLL_PSEL_VAL << SYSCON_SYSPLLCTRL_PSEL_POS) + | (LPC_SYSPLL_MSEL_VAL << SYSCON_SYSPLLCTRL_MSEL_POS); + // Wait for PLLLock + while(!(LPC_SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK)){} + #endif // LPC_MAINCLKSEL == SYSCON_MAINCLKSEL_PLLOUT + + #endif /* LPC_MAINCLKSEL == SYSCON_MAINCLKSEL_PLLOUT || + LPC_MAINCLKSEL == SYSCON_MAINCLKSEL_PLLIN */ + + // Config SYSDIV + LPC_SYSCON->SYSAHBCLKDIV = LPC_SYS_DIV & 0xFF; + + // Select Main Clock + LPC_SYSCON->MAINCLKSEL = LPC_MAINCLKSEL; + LPC_SYSCON->MAINCLKUEN = 0; + LPC_SYSCON->MAINCLKUEN = SYSCON_MAINCLKUEN_ENA; +} + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + lpc_clock_init(); +} + +/** @} */ diff --git a/os/hal/ports/LPC/LPC11Uxx/hal_lld.h b/os/hal/ports/LPC/LPC11Uxx/hal_lld.h new file mode 100644 index 00000000..4c2b0eb8 --- /dev/null +++ b/os/hal/ports/LPC/LPC11Uxx/hal_lld.h @@ -0,0 +1,159 @@ +/* + ChibiOS - Copyright (C) 2020 Yaotian Feng / Codetector + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/hal_lld.h + * @brief NXP LPC 11Uxx HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ +#ifndef HAL_LLD_H +#define HAL_LLD_H + +#include "LPC11Uxx.h" +#include "lpc_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification macros + * @{ + */ +#define PLATFORM_NAME "LPC" +/** @} */ + + +/** + * @name PLATFORM configuration options + * @{ + */ +#define LPC_IRC_FREQUENCY 12000000UL // 12MHz +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(LPC11Uxx_MCUCONF) && !defined(LPC11U35_MCUCONF) && \ + !defined(LPC11U35_401_MCUCONF) + #error "Using a wrong mcuconf.h file, LPC11Uxx_MCUCONF not defined" +#endif + +#if (defined(LPC_USE_SYSOSC) && LPC_USE_SYSOSC == FALSE) || !defined(LPC_SYSOSC_FREQUENCY) + #error "LPC_SYSOSC_FREQUENCY must be defined if LPC_USE_SYSOSC" +#endif + +// SYSTEMPLL SEL +#if defined(LPC_SYSPLLCLKSEL) && LPC_SYSPLLCLKSEL == SYSCON_SYSPLLCLKSEL_IRC + #define LPC_SYSPLLIN_FREQUENCY (LPC_IRC_FREQUENCY) +#elif defined(LPC_SYSPLLCLKSEL) && LPC_SYSPLLCLKSEL == SYSCON_SYSPLLCLKSEL_SYSOSC + #ifndef LPC_USE_SYSOSC + #error "LPC_USE_SYSOSC must be defined when using SYSOSC" + #endif + #define LPC_SYSPLLIN_FREQUENCY (LPC_SYSOSC_FREQUENCY) +#else +#error "LPC_SYSPLLCLKSEL must be one of SYSCON_SYSPLLCLKSEL_IRC, \ +SYSCON_SYSPLLCLKSEL_SYSOSC" +#endif + +#if defined(LPC_MAINCLKSEL) && LPC_MAINCLKSEL == SYSCON_MAINCLKSEL_IRC + // Using Internal OSC + #define LPC_MAINCLK_FREQUENCY (LPC_IRC_FREQUENCY) + +#elif defined(LPC_MAINCLKSEL) && LPC_MAINCLKSEL == SYSCON_MAINCLKSEL_PLLIN + #define LPC_MAINCLK_FREQUENCY (LPC_SYSPLLIN_FREQUENCY) +#elif defined(LPC_MAINCLKSEL) && LPC_MAINCLKSEL == SYSCON_MAINCLKSEL_WATCHDOG + + #error "Unsupported clock select" + +#elif defined(LPC_MAINCLKSEL) && LPC_MAINCLKSEL == SYSCON_MAINCLKSEL_PLLOUT + // PLL OUT + #if defined(LPC_SYSPLL_MULT) && LPC_SYSPLL_MULT > 0 && LPC_SYSPLL_MULT <= 32 \ + && defined(LPC_SYSPLL_PDIV) && (LPC_SYSPLL_PDIV == 2 || LPC_SYSPLL_PDIV == 4 \ + && LPC_SYSPLL_PDIV == 8 || LPC_SYSPLL_PDIV == 16) + + #if LPC_SYSPLL_PDIV == 2 + #define LPC_SYSPLL_PSEL_VAL 0x0U + #elif LPC_SYSPLL_PDIV == 4 + #define LPC_SYSPLL_PSEL_VAL 0x1U + #elif LPC_SYSPLL_PDIV == 8 + #define LPC_SYSPLL_PSEL_VAL 0x2U + #elif LPC_SYSPLL_PDIV == 16 + #define LPC_SYSPLL_PSEL_VAL 0x3U + #endif + + #if (LPC_SYSPLLIN_FREQUENCY * LPC_SYSPLL_MULT * LPC_SYSPLL_PDIV < 156000000UL) ||\ + (LPC_SYSPLLIN_FREQUENCY * LPC_SYSPLL_MULT * LPC_SYSPLL_PDIV > 320000000UL) + #error "Please check the documentation about how to pick MULT and PDIV. \ +current value gives a out of range CCO frequency" + #endif + + #define LPC_MAINCLK_FREQUENCY (LPC_SYSPLLIN_FREQUENCY * LPC_SYSPLL_MULT) + #define LPC_SYSPLL_MSEL_VAL (LPC_SYSPLL_MULT - 1) + + #else + #error "LPC_SYSPLL_MULT must be defined and btween 1 and 32, \ + LPC_SYSPLL_PDIV must be one of 2, 4, 8, 16." + #endif +#else + #error "Invalid LPC_MAINCLKSEL. Must be one of SYSCON_MAINCLKSEL_IRC, \ +SYSCON_MAINCLKSEL_PLLIN, SYSCON_MAINCLKSEL_WATCHDOG, SYSCON_MAINCLKSEL_PLLOUT" +#endif + +#if !defined(LPC_SYS_DIV) || LPC_SYS_DIV < 1 || LPC_SYS_DIV > 255 + #error "LPC_SYS_DIV must be between 1 and 255" +#else + #define LPC_SYS_FREQUENCY (LPC_MAINCLK_FREQUENCY / LPC_SYS_DIV) +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#include "nvic.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void lpc_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_LLD_H_ */ + +/** @} */ + diff --git a/os/hal/ports/LPC/LPC11Uxx/lpc_registry.h b/os/hal/ports/LPC/LPC11Uxx/lpc_registry.h new file mode 100644 index 00000000..251c1e6d --- /dev/null +++ b/os/hal/ports/LPC/LPC11Uxx/lpc_registry.h @@ -0,0 +1,48 @@ +/* + ChibiOS - Copyright (C) 2020 Yaotian Feng / Codetector + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file LPC11Uxx/lpc_registry.h + * @brief LPC11U11 capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef LPC_REGISTRY_H_ +#define LPC_REGISTRY_H_ + +/** + * @brief Sub-family identifier. + */ +#if defined(LPC11U35) || \ +defined(__DOXYGEN__) + #define LPC11Uxx +#else +#error unknown/unsupported LPC11Uxx microcontroller +#endif + +#if defined(LPC11Uxx) || defined(__DOXYGEN__) + + +#endif + + +/** @} */ + +#endif /* LPC_REGISTRY_H_ */ + +/** @} */ diff --git a/os/hal/ports/LPC/LPC11Uxx/platform.mk b/os/hal/ports/LPC/LPC11Uxx/platform.mk new file mode 100644 index 00000000..fd67a85d --- /dev/null +++ b/os/hal/ports/LPC/LPC11Uxx/platform.mk @@ -0,0 +1,13 @@ +# List of all the LPC11Uxx platform files. +PLATFORMSRC := ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/LPC/LPC11Uxx/hal_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ + ${CHIBIOS_CONTRIB}/os/hal/ports/LPC/LPC11Uxx + +include $(CHIBIOS_CONTRIB)/os/hal/ports/LPC/LLD/STM/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC)