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Updated for better compatibility.

This commit is contained in:
Joy 2022-04-14 11:19:43 +08:00
parent 74fce1d693
commit 3691f9affd
6 changed files with 186 additions and 16 deletions
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2
demos/WB32/RT-WB32FQ95-GENERIC/cfg/mcuconf.h
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@ -20,7 +20,7 @@
#define WB32FQ95xx_MCUCONF TRUE #define WB32FQ95xx_MCUCONF TRUE
/* /*
* WB32F3G71 drivers configuration. * WB32FQ95 drivers configuration.
* The following settings override the default settings present in * The following settings override the default settings present in
* the various device driver implementation headers. * the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole * Note that the settings for each driver only have effect if the whole

85
os/common/startup/ARMCMx/compilers/GCC/ld/WB32FQ95x9.ld Normal file
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@ -0,0 +1,85 @@
/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* WB32FQ95x9 memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 96k
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 28k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld

85
os/common/startup/ARMCMx/compilers/GCC/ld/WB32FQ95xB.ld Normal file
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@ -0,0 +1,85 @@
/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* WB32FQ95xB memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 128k
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 28k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld

12
os/hal/ports/WB32/LLD/I2Cv1/hal_i2c_lld.c
View File

@ -106,7 +106,7 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) {
* @notapi * @notapi
*/ */
static void i2c_lld_configuration(I2CDriver *i2cp) { static void i2c_lld_configuration(I2CDriver *i2cp) {
I2C_TypeDef *dp = i2cp->i2c; I2C_TypeDef *dp = i2cp->i2c;
float tclk, tval; float tclk, tval;
uint32_t con_reg; uint32_t con_reg;
i2copmode_t opmode = i2cp->config->op_mode; i2copmode_t opmode = i2cp->config->op_mode;
@ -150,7 +150,7 @@ static void i2c_lld_configuration(I2CDriver *i2cp) {
dp->FS_SCL_LCNT = (uint32_t)(tval - 1); dp->FS_SCL_LCNT = (uint32_t)(tval - 1);
} }
dp->CON = con_reg; dp->CON = con_reg;
} }
/** /**
@ -400,7 +400,7 @@ void i2c_lld_stop(I2CDriver *i2cp) {
/** /**
* @brief Receives data via the I2C bus as master. * @brief Receives data via the I2C bus as master.
* @details Number of receiving bytes must be more than 1 on WB32F3G71x. * @details Number of receiving bytes must be more than 1.
* This is hardware restriction. * This is hardware restriction.
* *
* @param[in] i2cp pointer to the @p I2CDriver object * @param[in] i2cp pointer to the @p I2CDriver object
@ -427,7 +427,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
I2C_TypeDef *dp = i2cp->i2c; I2C_TypeDef *dp = i2cp->i2c;
msg_t msg; msg_t msg;
#if defined(WB32F3G71xx_I2C) #if defined(WB32_I2C)
osalDbgCheck(rxbytes > 0); osalDbgCheck(rxbytes > 0);
#endif #endif
/* Resetting error flags for this transfer.*/ /* Resetting error flags for this transfer.*/
@ -472,7 +472,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
/** /**
* @brief Transmits data via the I2C bus as master. * @brief Transmits data via the I2C bus as master.
* @details Number of receiving bytes must be 0 or more than 1 on WB32F3G71x. * @details Number of receiving bytes must be 0 or more than 1.
* This is hardware restriction. * This is hardware restriction.
* *
* @param[in] i2cp pointer to the @p I2CDriver object * @param[in] i2cp pointer to the @p I2CDriver object
@ -503,7 +503,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
I2C_TypeDef *dp = i2cp->i2c; I2C_TypeDef *dp = i2cp->i2c;
__IO msg_t msg; __IO msg_t msg;
#if defined(WB32F3G71xx_I2C) #if defined(WB32_I2C)
osalDbgCheck((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL))); osalDbgCheck((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL)));
#endif #endif
/* Resetting error flags for this transfer.*/ /* Resetting error flags for this transfer.*/

12
os/hal/ports/WB32/LLD/I2Cv1/hal_i2c_lld.h
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@ -82,8 +82,8 @@
#define WB32_I2C_I2C2_IRQ_PRIORITY 10 #define WB32_I2C_I2C2_IRQ_PRIORITY 10
#endif #endif
#if defined(WB32F3G71xx) #if defined(WB32F3G71xx) || defined(WB32FQ95xx)
#define WB32F3G71xx_I2C #define WB32_I2C
#endif #endif
/** @} */ /** @} */
@ -136,22 +136,22 @@ typedef struct {
volatile uint32_t rx_cmd_len; volatile uint32_t rx_cmd_len;
uint32_t tx_abrt_source; uint32_t tx_abrt_source;
} i2c_xfer_info_t; } i2c_xfer_info_t;
typedef enum { typedef enum {
OPMODE_I2C = 1, OPMODE_I2C = 1,
OPMODE_SMBUS_DEVICE = 2, OPMODE_SMBUS_DEVICE = 2,
OPMODE_SMBUS_HOST = 3, OPMODE_SMBUS_HOST = 3,
} i2copmode_t; } i2copmode_t;
/** /**
* @brief Type of I2C driver configuration structure. * @brief Type of I2C driver configuration structure.
*/ */
typedef struct { typedef struct {
/* End of the mandatory fields.*/ /* End of the mandatory fields.*/
i2copmode_t op_mode; /**< @brief Specifies the I2C mode. */ i2copmode_t op_mode; /**< @brief Specifies the I2C mode. */
uint32_t clock_speed; /**< @brief Specifies the clock frequency. uint32_t clock_speed; /**< @brief Specifies the clock frequency.
@note Must be set to a value lower @note Must be set to a value lower
than 400kHz. */ than 400kHz. */
} I2CConfig; } I2CConfig;
/** /**

6
os/hal/ports/WB32/LLD/TIMv1/hal_st_lld.c
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@ -52,7 +52,7 @@
#define ST_NUMBER WB32_TIM2_NUMBER #define ST_NUMBER WB32_TIM2_NUMBER
#define ST_CLOCK_SRC WB32_TIMCLK1 #define ST_CLOCK_SRC WB32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM2() #define ST_ENABLE_CLOCK() rccEnableTIM2()
#if defined(WB32F3G71xx) #if defined(WB32F3G71xx) || defined(WB32FQ95xx)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP #define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP
#endif #endif
@ -70,7 +70,7 @@
#define ST_NUMBER WB32_TIM3_NUMBER #define ST_NUMBER WB32_TIM3_NUMBER
#define ST_CLOCK_SRC WB32_TIMCLK1 #define ST_CLOCK_SRC WB32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM3() #define ST_ENABLE_CLOCK() rccEnableTIM3()
#if defined(WB32F3G71xx) #if defined(WB32F3G71xx) || defined(WB32FQ95xx)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM3_STOP #define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM3_STOP
#endif #endif
@ -88,7 +88,7 @@
#define ST_NUMBER WB32_TIM4_NUMBER #define ST_NUMBER WB32_TIM4_NUMBER
#define ST_CLOCK_SRC WB32_TIMCLK1 #define ST_CLOCK_SRC WB32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM4() #define ST_ENABLE_CLOCK() rccEnableTIM4()
#if defined(WB32F3G71xx) #if defined(WB32F3G71xx) || defined(WB32FQ95xx)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM4_STOP #define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM4_STOP
#endif #endif