FSMC. SDRAM. Improved stop function
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@ -42,13 +42,13 @@
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/**
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/**
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* FMC_Command_Mode
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* FMC_Command_Mode
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*/
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*/
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#define FMC_Command_Mode_normal ((uint32_t)0x00000000)
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#define FMCCM_NORMAL ((uint32_t)0x00000000)
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#define FMC_Command_Mode_CLK_Enabled ((uint32_t)0x00000001)
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#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001)
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#define FMC_Command_Mode_PALL ((uint32_t)0x00000002)
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#define FMCCM_PALL ((uint32_t)0x00000002)
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#define FMC_Command_Mode_AutoRefresh ((uint32_t)0x00000003)
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#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003)
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#define FMC_Command_Mode_LoadMode ((uint32_t)0x00000004)
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#define FMCCM_LOAD_MODE ((uint32_t)0x00000004)
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#define FMC_Command_Mode_Selfrefresh ((uint32_t)0x00000005)
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#define FMCCM_SELFREFRESH ((uint32_t)0x00000005)
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#define FMC_Command_Mode_PowerDown ((uint32_t)0x00000006)
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#define FMCCM_POWER_DOWN ((uint32_t)0x00000006)
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/* Driver exported variables. */
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@ -100,27 +100,27 @@ static void _sdram_init_sequence(const SDRAMConfig *cfgp) {
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/* Step 3: Configure a clock configuration enable command.*/
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/* Step 3: Configure a clock configuration enable command.*/
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_sdram_wait_ready();
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_sdram_wait_ready();
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SDRAMD.sdram->SDCMR = FMC_Command_Mode_CLK_Enabled | command_target;
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SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target;
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/* Step 4: Insert 1 ms delay (tipically 100uS).*/
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/* Step 4: Insert 1 ms delay (tipically 100uS).*/
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osalThreadSleepMilliseconds(1);
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osalThreadSleepMilliseconds(1);
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/* Step 5: Configure a PALL (precharge all) command.*/
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/* Step 5: Configure a PALL (precharge all) command.*/
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_sdram_wait_ready();
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_sdram_wait_ready();
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SDRAMD.sdram->SDCMR = FMC_Command_Mode_PALL | command_target;
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SDRAMD.sdram->SDCMR = FMCCM_PALL | command_target;
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/* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
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/* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
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_sdram_wait_ready();
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_sdram_wait_ready();
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SDRAMD.sdram->SDCMR = FMC_Command_Mode_AutoRefresh | command_target |
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SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
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(cfgp->sdcmr & FMC_SDCMR_NRFS);
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(cfgp->sdcmr & FMC_SDCMR_NRFS);
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/* Step 6.2: Send the second command.*/
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/* Step 6.2: Send the second command.*/
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SDRAMD.sdram->SDCMR = FMC_Command_Mode_AutoRefresh | command_target |
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SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
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(cfgp->sdcmr & FMC_SDCMR_NRFS);
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(cfgp->sdcmr & FMC_SDCMR_NRFS);
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/* Step 7: Program the external memory mode register.*/
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/* Step 7: Program the external memory mode register.*/
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_sdram_wait_ready();
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_sdram_wait_ready();
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SDRAMD.sdram->SDCMR = FMC_Command_Mode_LoadMode | command_target |
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SDRAMD.sdram->SDCMR = FMCCM_LOAD_MODE | command_target |
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(cfgp->sdcmr & FMC_SDCMR_MRD);
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(cfgp->sdcmr & FMC_SDCMR_MRD);
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/* Step 8: Set clock.*/
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/* Step 8: Set clock.*/
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@ -188,7 +188,17 @@ void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) {
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*/
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*/
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void fsmcSdramStop(SDRAMDriver *sdramp) {
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void fsmcSdramStop(SDRAMDriver *sdramp) {
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uint32_t command_target = 0;
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#if STM32_SDRAM_USE_FSMC_SDRAM1
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command_target |= FMC_SDCMR_CTB1;
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#endif
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#if STM32_SDRAM_USE_FSMC_SDRAM2
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command_target |= FMC_SDCMR_CTB2;
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#endif
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if (sdramp->state == SDRAM_READY) {
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if (sdramp->state == SDRAM_READY) {
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SDRAMD.sdram->SDCMR = FMCCM_POWER_DOWN | command_target;
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sdramp->state = SDRAM_STOP;
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sdramp->state = SDRAM_STOP;
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}
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}
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}
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}
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