From 3dfa6a59051f912ec035a3046b40d7bf84de0133 Mon Sep 17 00:00:00 2001 From: andru Date: Fri, 14 May 2021 22:04:00 +0300 Subject: [PATCH] added nrf52 uart driver, changed icu, radio drivers --- os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.c | 359 +++++---- os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.h | 2 +- os/hal/ports/NRF5/LLD/UARTEv1/driver.mk | 8 + os/hal/ports/NRF5/LLD/UARTEv1/hal_uart_lld.c | 548 +++++++++++++ os/hal/ports/NRF5/LLD/UARTEv1/hal_uart_lld.h | 259 ++++++ os/hal/ports/NRF5/NRF52832/nrf52_isr.c | 14 + os/hal/ports/NRF5/NRF52832/platform.mk | 1 + os/various/devices_lib/rf/nrf52_radio.c | 33 +- os/various/devices_lib/rf/nrf52_radio.h | 4 +- testhal/NRF52/NRF52832/RADIO-ESB/Makefile | 2 +- .../NRF52/NRF52832/RADIO-ESB/nrf52_radio.c | 33 +- .../NRF52/NRF52832/RADIO-ESB/nrf52_radio.h | 4 +- testhal/NRF52/NRF52832/UART/Makefile | 211 +++++ testhal/NRF52/NRF52832/UART/chconf.h | 757 ++++++++++++++++++ testhal/NRF52/NRF52832/UART/halconf.h | 533 ++++++++++++ .../NRF52/NRF52832/UART/halconf_community.h | 173 ++++ testhal/NRF52/NRF52832/UART/main.c | 144 ++++ testhal/NRF52/NRF52832/UART/mcuconf.h | 29 + testhal/NRF52/NRF52832/UART/readme.txt | 17 + 19 files changed, 2945 insertions(+), 186 deletions(-) create mode 100644 os/hal/ports/NRF5/LLD/UARTEv1/driver.mk create mode 100644 os/hal/ports/NRF5/LLD/UARTEv1/hal_uart_lld.c create mode 100644 os/hal/ports/NRF5/LLD/UARTEv1/hal_uart_lld.h create mode 100644 testhal/NRF52/NRF52832/UART/Makefile create mode 100644 testhal/NRF52/NRF52832/UART/chconf.h create mode 100644 testhal/NRF52/NRF52832/UART/halconf.h create mode 100644 testhal/NRF52/NRF52832/UART/halconf_community.h create mode 100644 testhal/NRF52/NRF52832/UART/main.c create mode 100644 testhal/NRF52/NRF52832/UART/mcuconf.h create mode 100644 testhal/NRF52/NRF52832/UART/readme.txt diff --git a/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.c b/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.c index bca88557..12179fc7 100644 --- a/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.c +++ b/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.c @@ -82,50 +82,6 @@ ICUDriver ICUD5; /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ -/** - * @brief Returns pulse width. - * @details The time is defined as number of ticks. - * - * @param[in] icup Pointer to the ICUDriver object. - * @param[in] channel The timer channel that fired the interrupt. - * @param[in] compare Content of the CC register. - * @return The number of ticks. - * - * @notapi - */ -static icucnt_t get_time_width(const ICUDriver *icup, - uint8_t channel, - icucnt_t compare) { - - const ICUChannel *chp = &icup->channel[channel]; - - /* Note! there is no overflow check because it handles under the hood of - unsigned subtraction math.*/ - return compare - chp->last_idle; -} - -/** - * @brief Returns pulse period. - * @details The time is defined as number of ticks. - * - * @param[in] icup Pointer to the ICUDriver object. - * @param[in] channel The timer channel that fired the interrupt. - * @param[in] compare Content of the CC register. - * @return The number of ticks. - * - * @notapi - */ -static icucnt_t get_time_period(const ICUDriver *icup, - uint8_t channel, - icucnt_t compare) { - - const ICUChannel *chp = &icup->channel[channel]; - - /* Note! there is no overflow check because it handles under the hood of - unsigned subtraction math.*/ - return compare - chp->last_idle; -} - /** * @brief ICU width event. * @@ -134,15 +90,12 @@ static icucnt_t get_time_period(const ICUDriver *icup, * * @notapi */ -static void _isr_invoke_width_cb(ICUDriver *icup, uint8_t channel) { +static inline void _isr_invoke_width_cb(ICUDriver *icup, uint8_t channel) { ICUChannel *chp = &icup->channel[channel]; - icucnt_t compare = icup->timer->CC[channel+2]; - chp->last_active = compare; - if (ICU_CH_ACTIVE == chp->state) { - icup->result.width = get_time_width(icup, channel, compare); + if (chp->state == ICU_CH_ACTIVE) { + icup->result.width = icup->timer->CC[channel+2] - chp->last_idle; if ((icup->state == ICU_ACTIVE) && (icup->config->width_cb != NULL)) icup->config->width_cb(icup); - chp->state = ICU_CH_IDLE; } } @@ -154,15 +107,21 @@ static void _isr_invoke_width_cb(ICUDriver *icup, uint8_t channel) { * * @notapi */ -static void _isr_invoke_period_cb(ICUDriver *icup, uint8_t channel) { +static inline void _isr_invoke_period_cb(ICUDriver *icup, uint8_t channel) { ICUChannel *chp = &icup->channel[channel]; - icucnt_t compare = (uint32_t)icup->timer->CC[channel]; - icup->result.period = get_time_period(icup, channel, compare); - chp->last_idle = compare; - chp->state = ICU_CH_ACTIVE; - if ((icup->state == ICU_ACTIVE) && (icup->config->period_cb != NULL)) - icup->config->period_cb(icup); - icup->state = ICU_ACTIVE; + icucnt_t compare = (uint32_t) icup->timer->CC[channel]; + if (chp->state == ICU_CH_ACTIVE) { + icup->result.period = compare - chp->last_idle; + chp->last_idle = compare; + } else { + chp->state = ICU_CH_ACTIVE; + } + if (icup->state == ICU_ACTIVE) { + if (icup->config->period_cb != NULL) + icup->config->period_cb(icup); + } else { + icup->state = ICU_ACTIVE; + } /* Set overflow timeout */ icup->timer->CC[channel] = compare + ICU_WAIT_TIMEOUT; } @@ -176,19 +135,21 @@ void icu_lld_serve_gpiote_interrupt(ICUDriver *icup) { uint8_t ch; for (ch=0; chconfig->iccfgp[ch]; + if (cfg_channel == NULL || cfg_channel->mode == ICU_INPUT_DISABLED) continue; + const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; /* Period event */ if (NRF_GPIOTE->INTENSET & (1 << gpiote_channel[0]) && NRF_GPIOTE->EVENTS_IN[gpiote_channel[0]]) { - _isr_invoke_period_cb(icup, ch); NRF_GPIOTE->EVENTS_IN[gpiote_channel[0]] = 0; (void) NRF_GPIOTE->EVENTS_IN[gpiote_channel[0]]; + _isr_invoke_period_cb(icup, ch); } /* Width event */ if (NRF_GPIOTE->INTENSET & (1 << gpiote_channel[1]) && NRF_GPIOTE->EVENTS_IN[gpiote_channel[1]]) { - _isr_invoke_width_cb(icup, ch); NRF_GPIOTE->EVENTS_IN[gpiote_channel[1]] = 0; (void) NRF_GPIOTE->EVENTS_IN[gpiote_channel[1]]; + _isr_invoke_width_cb(icup, ch); } } } @@ -198,7 +159,7 @@ void icu_lld_serve_gpiote_interrupt(ICUDriver *icup) { * * @param[in] icup Pointer to the @p ICUDriver object */ -void icu_lld_serve_interrupt(ICUDriver *icup) { +void icu_lld_serve_timer_interrupt(ICUDriver *icup) { uint8_t ch; for (ch=0; ch GPIOTE channel[1] will detect end edge. */ static void start_channels(ICUDriver *icup) { - /* Set each input channel that is used as: a normal input capture channel. */ #if NRF5_ICU_USE_GPIOTE_PPI uint8_t channel; for (channel = 0; channelconfig->iccfgp[channel]; - if (cfg_channel->mode == ICU_INPUT_DISABLED) continue; + if (cfg_channel == NULL || cfg_channel->mode == ICU_INPUT_DISABLED) continue; const uint32_t gpio_pin0 = PAL_PAD(cfg_channel->ioline[0]); const uint32_t gpio_pin1 = PAL_PAD(cfg_channel->ioline[1]); - osalDbgAssert((gpio_pin0 < 32) && - (gpio_pin1 < 32) && - (gpio_pin0 != gpio_pin1), - "invalid Line configuration"); /* NRF52832 GPIOTE channels 0..7 */ const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; - osalDbgAssert((gpiote_channel[0] < 8) && - (gpiote_channel[1] < 8) && - (gpiote_channel[0] != gpiote_channel[1]), - "invalid GPIOTE configuration"); + + // nRF52832 Rev 1 Errata 3.45 [155] GPIOTE: IN event may occur more than once on input edge + *(volatile uint32_t *)(NRF_GPIOTE_BASE + 0x600 + (4 * 0)) = 1; + *(volatile uint32_t *)(NRF_GPIOTE_BASE + 0x600 + (4 * 1)) = 1; + + /* Clear GPIOTE events */ + NRF_GPIOTE->INTENCLR = (GPIOTE_INTENCLR_PORT_Clear << GPIOTE_INTENCLR_PORT_Pos) | + (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + NRF_GPIOTE->EVENTS_PORT = 1; + + /* Set GPIOTE channels */ + if (cfg_channel->mode == ICU_INPUT_ACTIVE_HIGH) { + NRF_GPIOTE->CONFIG[gpiote_channel[0]] = + (GPIOTE_CONFIG_MODE_Disabled << GPIOTE_CONFIG_MODE_Pos) | + ((gpio_pin0 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | + ((GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk); + NRF_GPIOTE->CONFIG[gpiote_channel[1]] = + (GPIOTE_CONFIG_MODE_Disabled << GPIOTE_CONFIG_MODE_Pos) | + ((gpio_pin1 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | + ((GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk); + } else { + NRF_GPIOTE->CONFIG[gpiote_channel[0]] = + (GPIOTE_CONFIG_MODE_Disabled << GPIOTE_CONFIG_MODE_Pos) | + ((gpio_pin0 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | + ((GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk); + NRF_GPIOTE->CONFIG[gpiote_channel[1]] = + (GPIOTE_CONFIG_MODE_Disabled << GPIOTE_CONFIG_MODE_Pos) | + ((gpio_pin1 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | + ((GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk); + } /* NRF52832 PPI channels 0..19 */ const uint8_t *ppi_channel = cfg_channel->ppi_channel; - osalDbgAssert((gpiote_channel[0] < 20) && - (gpiote_channel[1] < 20) && - (gpiote_channel[0] != gpiote_channel[1]), - "invalid PPI configuration"); /* Program PPI events for period */ NRF_PPI->CH[ppi_channel[0]].EEP = (uint32_t) &NRF_GPIOTE->EVENTS_IN[gpiote_channel[0]]; @@ -260,38 +238,52 @@ static void start_channels(ICUDriver *icup) { /* Program PPI events for width */ NRF_PPI->CH[ppi_channel[1]].EEP = (uint32_t) &NRF_GPIOTE->EVENTS_IN[gpiote_channel[1]]; NRF_PPI->CH[ppi_channel[1]].TEP = (uint32_t) &icup->timer->TASKS_CAPTURE[channel+2]; + } +#endif - /* Disable GPIOTE interrupts */ - NRF_GPIOTE->INTENCLR = (GPIOTE_INTENCLR_PORT_Clear << GPIOTE_INTENCLR_PORT_Pos) | - (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); - NRF_GPIOTE->EVENTS_PORT = 1; +} + +/** + * @brief Stops every channel. + * + * @param[in] icup Pointer to the @p ICUDriver object + * + * @note GPIO Line[0] -> GPIOTE channel[0] will detect start edge. + * @note GPIO Line[1] -> GPIOTE channel[1] will detect end edge. + */ +static void stop_channels(ICUDriver *icup) { +#if NRF5_ICU_USE_GPIOTE_PPI + uint8_t channel; + for (channel = 0; channelconfig->iccfgp[channel]; + if (cfg_channel == NULL || cfg_channel->mode == ICU_INPUT_DISABLED) continue; + + const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; + const uint8_t *ppi_channel = cfg_channel->ppi_channel; + + /* Disable PPI channels */ + NRF_PPI->CHENCLR = (1 << ppi_channel[0]) | (1 << ppi_channel[1]); + + /* Disable PPI events for period */ + NRF_PPI->CH[ppi_channel[0]].EEP = (uint32_t) 0; + NRF_PPI->CH[ppi_channel[0]].TEP = (uint32_t) 0; + + /* Disable PPI events for width */ + NRF_PPI->CH[ppi_channel[1]].EEP = (uint32_t) 0; + NRF_PPI->CH[ppi_channel[1]].TEP = (uint32_t) 0; /* Clear GPIOTE channels */ - NRF_GPIOTE->CONFIG[gpiote_channel[0]] &= ~(GPIOTE_CONFIG_PSEL_Msk | GPIOTE_CONFIG_POLARITY_Msk); - NRF_GPIOTE->CONFIG[gpiote_channel[1]] &= ~(GPIOTE_CONFIG_PSEL_Msk | GPIOTE_CONFIG_POLARITY_Msk); + NRF_GPIOTE->CONFIG[gpiote_channel[0]] = 0; + NRF_GPIOTE->CONFIG[gpiote_channel[1]] = 0; - /* Set GPIOTE channels */ - if (cfg_channel->mode == ICU_INPUT_ACTIVE_HIGH) { - NRF_GPIOTE->CONFIG[gpiote_channel[0]] = - (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos) | - ((gpio_pin0 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | - ((GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk); - NRF_GPIOTE->CONFIG[gpiote_channel[1]] = - (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos) | - ((gpio_pin1 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | - ((GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk); - } else { - NRF_GPIOTE->CONFIG[gpiote_channel[0]] = - (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos) | - ((gpio_pin0 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | - ((GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos) - & GPIOTE_CONFIG_POLARITY_Msk); - NRF_GPIOTE->CONFIG[gpiote_channel[1]] = - (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos) | - ((gpio_pin1 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) | - ((GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos) - & GPIOTE_CONFIG_POLARITY_Msk); - } + const uint32_t gpio_pin0 = PAL_PAD(cfg_channel->ioline[0]); + const uint32_t gpio_pin1 = PAL_PAD(cfg_channel->ioline[1]); + + /* Disable GPIO sense */ + NRF_P0->PIN_CNF[gpio_pin0] = ((NRF_P0->PIN_CNF[gpio_pin0] & ~(GPIO_PIN_CNF_SENSE_Msk << GPIO_PIN_CNF_SENSE_Pos)) | + (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)); + NRF_P0->PIN_CNF[gpio_pin1] = ((NRF_P0->PIN_CNF[gpio_pin1] & ~(GPIO_PIN_CNF_SENSE_Msk << GPIO_PIN_CNF_SENSE_Pos)) | + (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)); } #endif @@ -301,6 +293,17 @@ static void start_channels(ICUDriver *icup) { /* Driver interrupt handlers. */ /*===========================================================================*/ +#if NRF5_ICU_USE_GPIOTE_PPI +/** + * @brief GPIOTE events interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr moved to nrf52_isr.c + */ +#endif /* NRF5_ICU_USE_GPIOTE_PPI */ + #if NRF5_ICU_USE_TIMER0 /** * @brief TIMER0 compare interrupt handler. @@ -314,7 +317,7 @@ OSAL_IRQ_HANDLER(Vector60) { OSAL_IRQ_PROLOGUE(); - icu_lld_serve_interrupt(&ICUD1); + icu_lld_serve_timer_interrupt(&ICUD1); OSAL_IRQ_EPILOGUE(); } @@ -333,7 +336,7 @@ OSAL_IRQ_HANDLER(Vector64) { OSAL_IRQ_PROLOGUE(); - icu_lld_serve_interrupt(&ICUD2); + icu_lld_serve_timer_interrupt(&ICUD2); OSAL_IRQ_EPILOGUE(); } @@ -352,7 +355,7 @@ OSAL_IRQ_HANDLER(Vector68) { OSAL_IRQ_PROLOGUE(); - icu_lld_serve_interrupt(&ICUD3); + icu_lld_serve_timer_interrupt(&ICUD3); OSAL_IRQ_EPILOGUE(); } @@ -371,7 +374,7 @@ OSAL_IRQ_HANDLER(VectorA8) { OSAL_IRQ_PROLOGUE(); - icu_lld_serve_interrupt(&ICUD4); + icu_lld_serve_timer_interrupt(&ICUD4); OSAL_IRQ_EPILOGUE(); } @@ -390,7 +393,7 @@ OSAL_IRQ_HANDLER(VectorAC) { OSAL_IRQ_PROLOGUE(); - icu_lld_serve_interrupt(&ICUD5); + icu_lld_serve_timer_interrupt(&ICUD5); OSAL_IRQ_EPILOGUE(); } @@ -445,7 +448,6 @@ void icu_lld_init(void) { * @notapi */ void icu_lld_start(ICUDriver *icup) { - size_t ch; osalDbgAssert((&icup->config->iccfgp[0] != NULL) || (&icup->config->iccfgp[1] != NULL), "invalid input configuration"); @@ -490,9 +492,38 @@ void icu_lld_start(ICUDriver *icup) { (void) icup->timer->EVENTS_COMPARE[2]; (void) icup->timer->EVENTS_COMPARE[3]; - /* Enable GPIOTE and TIMER interrupt vectors.*/ +/* Enable GPIOTE and TIMER interrupt vectors.*/ #if NRF5_ICU_USE_GPIOTE_PPI - nvicEnableVector(GPIOTE_IRQn, NRF5_ICU_GPIOTE_IRQ_PRIORITY); + uint8_t channel; + for (channel = 0; channelconfig->iccfgp[channel]; + if (cfg_channel == NULL || cfg_channel->mode == ICU_INPUT_DISABLED) continue; + + const uint32_t gpio_pin0 = PAL_PAD(cfg_channel->ioline[0]); + const uint32_t gpio_pin1 = PAL_PAD(cfg_channel->ioline[1]); + osalDbgAssert((gpio_pin0 < 32) && + (gpio_pin1 < 32) && + (gpio_pin0 != gpio_pin1), + "invalid Line configuration"); + + /* NRF52832 GPIOTE channels 0..7 */ + const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; + osalDbgAssert((gpiote_channel[0] < 8) && + (gpiote_channel[1] < 8) && + (gpiote_channel[0] != gpiote_channel[1]), + "invalid GPIOTE configuration"); + + /* NRF52832 PPI channels 0..19 */ + osalDbgAssert((gpiote_channel[0] < 20) && + (gpiote_channel[1] < 20) && + (gpiote_channel[0] != gpiote_channel[1]), + "invalid PPI configuration"); + } + + /* Set GPIOTE & PPI channels */ + start_channels(icup); + + nvicEnableVector(GPIOTE_IRQn, NRF5_ICU_GPIOTE_IRQ_PRIORITY); #endif #if NRF5_ICU_USE_TIMER0 if (&ICUD1 == icup) { @@ -520,14 +551,6 @@ void icu_lld_start(ICUDriver *icup) { } #endif - /* clean channel structures and set pointers to channel configs */ - for (ch=0; chchannel[ch].last_active = 0; - icup->channel[ch].last_idle = 0; - icup->channel[ch].state = ICU_CH_IDLE; - } - /* Set GPIOTE & PPI channels */ - start_channels(icup); } /** @@ -542,33 +565,35 @@ void icu_lld_stop(ICUDriver *icup) { if (icup->state == ICU_READY) { /* Timer stop.*/ icup->timer->TASKS_STOP = 1; + icup->timer->TASKS_SHUTDOWN = 1; #if NRF5_ICU_USE_GPIOTE_PPI uint8_t channel; for (channel = 0; channelconfig->iccfgp[channel]; - if (cfg_channel == NULL) continue; - const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; - const uint8_t *ppi_channel = cfg_channel->ppi_channel; + if (cfg_channel == NULL || cfg_channel->mode == ICU_INPUT_DISABLED) continue; /* Disable Timer interrupt */ icup->timer->INTENCLR = 1 << (TIMER_INTENCLR_COMPARE0_Pos + channel); - /* Disable GPIOTE interrupts */ - NRF_GPIOTE->INTENCLR = (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + /* Disable GPIOTE interrupt */ + const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; + NRF_GPIOTE->INTENCLR = (GPIOTE_INTENCLR_PORT_Clear << GPIOTE_INTENCLR_PORT_Pos) | + (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + NRF_GPIOTE->EVENTS_PORT = 0; + (void) NRF_GPIOTE->EVENTS_PORT; - /* Disable PPI channels */ - NRF_PPI->CHENCLR = ((1 << ppi_channel[0]) | (1 << ppi_channel[1])); - - /* Clear GPIOTE channels */ - NRF_GPIOTE->CONFIG[gpiote_channel[0]] &= ~(GPIOTE_CONFIG_PSEL_Msk | GPIOTE_CONFIG_POLARITY_Msk); - NRF_GPIOTE->CONFIG[gpiote_channel[1]] &= ~(GPIOTE_CONFIG_PSEL_Msk | GPIOTE_CONFIG_POLARITY_Msk); + NRF_GPIOTE->EVENTS_IN[gpiote_channel[0]] = 0; + NRF_GPIOTE->EVENTS_IN[gpiote_channel[1]] = 0; + (void) NRF_GPIOTE->EVENTS_IN[gpiote_channel[0]]; + (void) NRF_GPIOTE->EVENTS_IN[gpiote_channel[1]]; } -#endif -#if NRF5_ICU_USE_GPIOTE_PPI - nvicDisableVector(GPIOTE_IRQn); + nvicDisableVector(GPIOTE_IRQn); + + /* Stop GPIOTE & PPI channels */ + stop_channels(icup); #endif #if NRF5_ICU_USE_TIMER0 if (&ICUD1 == icup) { @@ -606,28 +631,49 @@ void icu_lld_stop(ICUDriver *icup) { * @notapi */ void icu_lld_start_capture(ICUDriver *icup) { + uint8_t channel; + /* Clear and start Timer */ icup->timer->TASKS_CLEAR = 1; icup->timer->TASKS_START = 1; #if NRF5_ICU_USE_GPIOTE_PPI - uint8_t channel; for (channel = 0; channelconfig->iccfgp[channel]; - if (cfg_channel == NULL) continue; + + if (cfg_channel == NULL || cfg_channel->mode == ICU_INPUT_DISABLED) continue; const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; - const uint8_t *ppi_channel = cfg_channel->ppi_channel; + const uint8_t *ppi_channel = cfg_channel->ppi_channel; + + /* clean channel structures and set pointers to channel configs */ + icup->channel[channel].last_active = 0; + icup->channel[channel].last_idle = 0; + icup->channel[channel].state = ICU_CH_IDLE; /* Enable interrupt for overflow events */ icup->timer->CC[channel] = ICU_WAIT_TIMEOUT; icup->timer->INTENSET = 1 << (TIMER_INTENSET_COMPARE0_Pos + channel); - /* Enable PPI channels */ - NRF_PPI->CHENSET = ((1 << ppi_channel[0]) | (1 << ppi_channel[1])); + /* Disable GPIOTE interrupts */ + NRF_GPIOTE->INTENCLR = (GPIOTE_INTENCLR_PORT_Clear << GPIOTE_INTENCLR_PORT_Pos) | + (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + NRF_GPIOTE->EVENTS_PORT = 1; - /* Enable GPIOTE interrupt */ - NRF_GPIOTE->INTENSET = (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + /* Clear GPIOTE events */ + NRF_GPIOTE->EVENTS_IN[gpiote_channel[0]] = 0; + NRF_GPIOTE->EVENTS_IN[gpiote_channel[1]] = 0; + (void) NRF_GPIOTE->EVENTS_IN[gpiote_channel[0]]; + (void) NRF_GPIOTE->EVENTS_IN[gpiote_channel[1]]; + + /* Set GPIOTE channels */ + NRF_GPIOTE->CONFIG[gpiote_channel[0]] = (NRF_GPIOTE->CONFIG[gpiote_channel[0]] & ~GPIOTE_CONFIG_MODE_Msk) | + (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos); + NRF_GPIOTE->CONFIG[gpiote_channel[1]] = (NRF_GPIOTE->CONFIG[gpiote_channel[1]] & ~GPIOTE_CONFIG_MODE_Msk) | + (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos); + + /* Enable PPI channels */ + NRF_PPI->CHENSET = (1 << ppi_channel[0]) | (1 << ppi_channel[1]); } #endif } @@ -671,7 +717,8 @@ void icu_lld_stop_capture(ICUDriver *icup) { uint8_t channel; for (channel = 0; channelconfig->iccfgp[channel]; - if (cfg_channel == NULL) continue; + + if (cfg_channel == NULL || cfg_channel->mode == ICU_INPUT_DISABLED) continue; const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; const uint8_t *ppi_channel = cfg_channel->ppi_channel; @@ -679,11 +726,19 @@ void icu_lld_stop_capture(ICUDriver *icup) { /* Disable Timer interrupt for overflow events */ icup->timer->INTENCLR = 1 << (TIMER_INTENCLR_COMPARE0_Pos + channel); - /* Disable GPIOTE interrupt */ - NRF_GPIOTE->INTENCLR = (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); - /* Disable PPI channels */ - NRF_PPI->CHENCLR = ((1 << ppi_channel[0]) | (1 << ppi_channel[1])); + NRF_PPI->CHENCLR = (1 << ppi_channel[0]) | (1 << ppi_channel[1]); + + /* Disable GPIOTE interrupts */ + NRF_GPIOTE->INTENCLR = (GPIOTE_INTENCLR_PORT_Clear << GPIOTE_INTENCLR_PORT_Pos) | + (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + NRF_GPIOTE->EVENTS_PORT = 1; + + /* Disable GPIOTE channels */ + NRF_GPIOTE->CONFIG[gpiote_channel[0]] = (NRF_GPIOTE->CONFIG[gpiote_channel[0]] & ~GPIOTE_CONFIG_MODE_Msk) | + (GPIOTE_CONFIG_MODE_Disabled << GPIOTE_CONFIG_MODE_Pos); + NRF_GPIOTE->CONFIG[gpiote_channel[1]] = (NRF_GPIOTE->CONFIG[gpiote_channel[1]] & ~GPIOTE_CONFIG_MODE_Msk) | + (GPIOTE_CONFIG_MODE_Disabled << GPIOTE_CONFIG_MODE_Pos); } #endif } @@ -703,15 +758,16 @@ void icu_lld_enable_notifications(ICUDriver *icup) { uint8_t channel; for (channel = 0; channelconfig->iccfgp[channel]; - if (cfg_channel == NULL) continue; - const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; + if (cfg_channel == NULL || cfg_channel->mode == ICU_INPUT_DISABLED) continue; /* Enable Timer interrupt */ icup->timer->INTENSET = 1 << (TIMER_INTENSET_COMPARE0_Pos + channel); /* Enable GPIOTE interrupt */ - NRF_GPIOTE->INTENSET = (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; + NRF_GPIOTE->INTENSET = (GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos) | + (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); } #endif } @@ -732,7 +788,8 @@ void icu_lld_disable_notifications(ICUDriver *icup) { uint8_t channel; for (channel = 0; channelconfig->iccfgp[channel]; - if (cfg_channel == NULL) continue; + + if (cfg_channel == NULL || cfg_channel->mode == ICU_INPUT_DISABLED) continue; const uint8_t *gpiote_channel = cfg_channel->gpiote_channel; @@ -740,7 +797,9 @@ void icu_lld_disable_notifications(ICUDriver *icup) { icup->timer->INTENCLR = 1 << (TIMER_INTENCLR_COMPARE0_Pos + channel); /* Disable GPIOTE interrupt */ - NRF_GPIOTE->INTENCLR = (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + NRF_GPIOTE->INTENCLR = (GPIOTE_INTENCLR_PORT_Clear << GPIOTE_INTENCLR_PORT_Pos) | + (1 << gpiote_channel[0]) | (1 << gpiote_channel[1]); + NRF_GPIOTE->EVENTS_PORT = 1; } #endif diff --git a/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.h b/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.h index 7fcace71..c6869731 100644 --- a/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.h +++ b/os/hal/ports/NRF5/LLD/TIMERv1/hal_icu_lld.h @@ -28,7 +28,7 @@ * @brief Number of ICU channels per ICU driver. */ #define ICU_CHANNELS 2 /* max channels */ -#define ICU_WAIT_TIMEOUT ( 0xFFFF ) /* first edge wait timeout */ +#define ICU_WAIT_TIMEOUT ( 0xFFFFFFFF ) /* first edge wait timeout */ #define ICU_FREQUENCY_16MHZ 16000000 /** @brief 16MHz */ #define ICU_FREQUENCY_8MHZ 8000000 /** @brief 8MHz */ diff --git a/os/hal/ports/NRF5/LLD/UARTEv1/driver.mk b/os/hal/ports/NRF5/LLD/UARTEv1/driver.mk new file mode 100644 index 00000000..63e4be03 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/UARTEv1/driver.mk @@ -0,0 +1,8 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/UARTEv1/hal_uart_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/UARTEv1/hal_uart_lld.c +endif +PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/UARTEv1 diff --git a/os/hal/ports/NRF5/LLD/UARTEv1/hal_uart_lld.c b/os/hal/ports/NRF5/LLD/UARTEv1/hal_uart_lld.c new file mode 100644 index 00000000..73090377 --- /dev/null +++ b/os/hal/ports/NRF5/LLD/UARTEv1/hal_uart_lld.c @@ -0,0 +1,548 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file UARTEv1/hal_uart_lld.c + * @brief NRF5 low level UART driver code. + * @author andru + * + * @addtogroup UART + * @{ + */ + +#include "hal.h" +#include + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief UART1 UART driver identifier.*/ +#if NRF5_UART_USE_UART0 || defined(__DOXYGEN__) +UARTDriver UARTD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Status bits translation. + * + * @param[in] sr UART ERRORSRC register value + * + * @return The error flags. + */ +static uartflags_t translate_errors(uint32_t sr) { + uartflags_t sts = 0; + + if (sr & UARTE_ERRORSRC_OVERRUN_Msk) + sts |= UART_OVERRUN_ERROR; + if (sr & UARTE_ERRORSRC_PARITY_Msk) + sts |= UART_PARITY_ERROR; + if (sr & UARTE_ERRORSRC_FRAMING_Msk) + sts |= UART_FRAMING_ERROR; + if (sr & UARTE_ERRORSRC_BREAK_Msk) + sts |= UART_BREAK_DETECTED; + return sts; +} + +/** + * @brief Puts the receiver in the UART_RX_IDLE state. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_enter_rx_idle_loop(UARTDriver *uartp) { + NRF_UARTE_Type *u = uartp->uart; + + /* RX DMA channel preparation, if the char callback is defined then the + interrupt is enabled too.*/ + if (uartp->config->rxchar_cb == NULL) + u->INTENCLR = UARTE_INTENCLR_ENDRX_Msk; + else + u->INTENSET = UARTE_INTENSET_ENDRX_Msk; + + u->SHORTS = UARTE_SHORTS_ENDRX_STARTRX_Msk; + + uartp->rxbuf = 0; + u->RXD.PTR = (uint32_t) &uartp->rxbuf; + u->RXD.MAXCNT = 1; + + u->TASKS_STARTRX = 1; +} + +/* + * @brief Maps a baudrate speed to a BAUDRATE register value. + */ + +/** + * @brief Common UART configuration. + * + */ +static void configure_uart(UARTDriver *uartp, const UARTConfig *config) +{ + NRF_UARTE_Type *u = uartp->uart; + uint32_t speed = UARTE_BAUDRATE_BAUDRATE_Baud250000; + + osalDbgAssert( + (config->rx_pad < TOTAL_GPIO_PADS) || (config->tx_pad < TOTAL_GPIO_PADS), + "must configure at least an RX or TX pad"); + + switch (config->speed) { + case 1200: speed = UARTE_BAUDRATE_BAUDRATE_Baud1200; break; + case 2400: speed = UARTE_BAUDRATE_BAUDRATE_Baud2400; break; + case 4800: speed = UARTE_BAUDRATE_BAUDRATE_Baud4800; break; + case 9600: speed = UARTE_BAUDRATE_BAUDRATE_Baud9600; break; + case 14400: speed = UARTE_BAUDRATE_BAUDRATE_Baud14400; break; + case 19200: speed = UARTE_BAUDRATE_BAUDRATE_Baud19200; break; + case 28800: speed = UARTE_BAUDRATE_BAUDRATE_Baud28800; break; + case 38400: speed = UARTE_BAUDRATE_BAUDRATE_Baud38400; break; + case 57600: speed = UARTE_BAUDRATE_BAUDRATE_Baud57600; break; + case 76800: speed = UARTE_BAUDRATE_BAUDRATE_Baud76800; break; + case 115200: speed = UARTE_BAUDRATE_BAUDRATE_Baud115200; break; + case 230400: speed = UARTE_BAUDRATE_BAUDRATE_Baud230400; break; + case 250000: speed = UARTE_BAUDRATE_BAUDRATE_Baud250000; break; + case 460800: speed = UARTE_BAUDRATE_BAUDRATE_Baud460800; break; + case 921600: speed = UARTE_BAUDRATE_BAUDRATE_Baud921600; break; + case 1000000: speed = UARTE_BAUDRATE_BAUDRATE_Baud1M; break; + default: osalDbgAssert(0, "invalid baudrate"); break; + }; + + /* Configure PINs mode */ + if (config->tx_pad != NRF5_UART_PAD_DISCONNECTED) { + palSetPadMode(IOPORT1, config->tx_pad, PAL_MODE_OUTPUT_PUSHPULL); + } + if (config->rx_pad != NRF5_UART_PAD_DISCONNECTED) { + palSetPadMode(IOPORT1, config->rx_pad, PAL_MODE_INPUT); + } +#if (NRF5_UART_USE_HWFLOWCTRL == TRUE) + if (config->rts_pad != NRF5_UART_PAD_DISCONNECTED) { + palSetPadMode(IOPORT1, config->rts_pad, PAL_MODE_OUTPUT_PUSHPULL); + } + if (config->cts_pad != NRF5_UART_PAD_DISCONNECTED) { + palSetPadMode(IOPORT1, config->cts_pad, PAL_MODE_INPUT); + } +#endif + + /* Select PINs used by UART */ + u->PSEL.TXD = config->tx_pad; + u->PSEL.RXD = config->rx_pad; +#if (NRF5_UART_USE_HWFLOWCTRL == TRUE) + u->PSEL.RTS = config->rts_pad; + u->PSEL.CTS = config->cts_pad; +#else + u->PSEL.RTS = NRF5_UART_PAD_DISCONNECTED; + u->PSEL.CTS = NRF5_UART_PAD_DISCONNECTED; +#endif + + /* Set baud rate */ + u->BAUDRATE = speed; + + /* Set config */ + u->CONFIG = (UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos); + + /* Adjust flow control */ +#if (NRF5_UART_USE_HWFLOWCTRL == TRUE) + if ((config->rts_pad < TOTAL_GPIO_PADS) || + (config->cts_pad < TOTAL_GPIO_PADS)) { + u->CONFIG |= UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos; + } else { + u->CONFIG &= UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos; + } +#else + u->CONFIG &= UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos; +#endif + + /* Enable UART and clear events */ + u->ENABLE = UARTE_ENABLE_ENABLE_Enabled; + + u->EVENTS_ENDRX = 0; + u->EVENTS_ENDTX = 0; + u->EVENTS_ERROR = 0; + u->EVENTS_RXTO = 0; + u->EVENTS_TXSTARTED = 0; + u->EVENTS_TXSTOPPED = 0; +#if CORTEX_MODEL >= 4 + (void)u->EVENTS_ENDRX; + (void)u->EVENTS_ENDTX; + (void)u->EVENTS_ERROR; + (void)u->EVENTS_RXTO; + (void)u->EVENTS_TXSTARTED; + (void)u->EVENTS_TXSTOPPED; +#endif + +#if (NRF5_UART_USE_HWFLOWCTRL == TRUE) + u->EVENTS_CTS = 0; + u->EVENTS_NCTS = 0; +#if CORTEX_MODEL >= 4 + (void)u->EVENTS_CTS; + (void)u->EVENTS_NCTS; +#endif +#endif +} + +/** + * @brief UART de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_stop(UARTDriver *uartp) { + NRF_UARTE_Type *u = uartp->uart; + + /* Stops RX and TX.*/ + u->TASKS_STOPRX = 1; + u->TASKS_STOPTX = 1; +} + +/** + * @brief UART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_start(UARTDriver *uartp) { + /* Defensive programming, starting from a clean state.*/ + uart_stop(uartp); + + configure_uart(uartp, uartp->config); + + /* Starting the receiver idle loop.*/ + uart_enter_rx_idle_loop(uartp); +} + +/** + * @brief RX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { + (void)flags; + NRF_UARTE_Type *u = uartp->uart; + + if (uartp->rxstate == UART_RX_IDLE) { + /* Receiver in idle state, a callback is generated, if enabled, for each + received character and then the driver stays in the same state.*/ + if (uartp->config->rxchar_cb != NULL) { + _uart_rx_idle_code(uartp); + } + } + else { + /* Receiver in active state, a callback is generated, if enabled, after + a completed transfer.*/ + u->TASKS_STOPRX = 1; + _uart_rx_complete_isr_code(uartp); + } +} + +/** + * @brief TX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { + (void)flags; + NRF_UARTE_Type *u = uartp->uart; + + /* A callback is generated, if enabled, after a completed transfer.*/ + u->TASKS_STOPTX = 1; + _uart_tx2_isr_code(uartp); +} + +/** + * @brief UART common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void serve_uart_irq(UARTDriver *uartp) { + NRF_UARTE_Type *u = uartp->uart; + uint32_t isr = u->INTENSET; + + if (u->EVENTS_ERROR) { + uint32_t sr = u->ERRORSRC; + + u->EVENTS_ERROR = 0; +#if CORTEX_MODEL >= 4 + (void)u->EVENTS_ERROR; +#endif + + _uart_rx_error_isr_code(uartp, translate_errors(sr)); + } + + if (u->EVENTS_TXSTARTED && isr & UARTE_INTENSET_TXSTARTED_Msk) { + u->INTENCLR &= UARTE_INTENCLR_TXSTARTED_Msk; + + u->EVENTS_TXSTARTED = 0; +#if CORTEX_MODEL >= 4 + (void)u->EVENTS_TXSTARTED; +#endif + + _uart_tx1_isr_code(uartp); + } + + if (u->EVENTS_ENDTX && isr & UARTE_INTENSET_ENDTX_Msk) { + /* interrupt cleared and disabled.*/ + u->INTENCLR &= UARTE_INTENCLR_ENDTX_Msk; + + u->EVENTS_ENDTX = 0; +#if CORTEX_MODEL >= 4 + (void)u->EVENTS_ENDTX; +#endif + + /* End of transmission, a callback is generated.*/ + uart_lld_serve_tx_end_irq(uartp, isr); + } + + if (u->EVENTS_ENDRX && isr & UARTE_INTENSET_ENDRX_Msk) { + /* interrupt cleared and disabled.*/ + + u->EVENTS_ENDRX = 0; +#if CORTEX_MODEL >= 4 + (void)u->EVENTS_ENDRX; +#endif + + /* End of reception, a callback is generated.*/ + uart_lld_serve_rx_end_irq(uartp, isr); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief UART0 IRQ handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector48) { + + OSAL_IRQ_PROLOGUE(); + + serve_uart_irq(&UARTD1); + + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) { + +#if NRF5_UART_USE_UART0 + uartObjectInit(&UARTD1); + UARTD1.uart = NRF_UARTE0; +#endif +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) { + NRF_UARTE_Type *u = uartp->uart; + const UARTConfig *config = uartp->config; + + if (uartp->state == UART_STOP) { + // Enable UART interrupt + u->INTENCLR = (uint32_t)-1; + u->INTENSET = UARTE_INTENSET_ERROR_Msk; + if (config->rx_pad != NRF5_UART_PAD_DISCONNECTED) { + u->INTENSET |= UARTE_INTENSET_ENDRX_Msk; + u->INTENSET |= UARTE_INTENSET_RXTO_Msk; + } + if (config->tx_pad != NRF5_UART_PAD_DISCONNECTED) { + u->INTENSET |= UARTE_INTENSET_TXSTARTED_Msk; + u->INTENSET |= UARTE_INTENSET_ENDTX_Msk; + } + + nvicEnableVector(UARTE0_UART0_IRQn, NRF5_UART_UART0_IRQ_PRIORITY); + } + + uartp->rxstate = UART_RX_IDLE; + uartp->txstate = UART_TX_IDLE; + uart_start(uartp); +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) { + NRF_UARTE_Type *u=uartp->uart; + + if (uartp->state == UART_READY) { + uart_stop(uartp); + + if (&UARTD1 == uartp) { + nvicDisableVector(UARTE0_UART0_IRQn); + u->ENABLE = UARTE_ENABLE_ENABLE_Disabled; + } + } +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, uint8_t n, const void *txbuf) { + NRF_UARTE_Type *u=uartp->uart; + + /* RAM buffer for Easy DMA.*/ + uint8_t buf[n]; + memcpy(&buf, txbuf, n); + + /* TX DMA channel preparation.*/ + u->TXD.PTR = (uint32_t) &buf; + u->TXD.MAXCNT = n; + + u->INTENSET = UARTE_INTENSET_TXSTARTED_Msk; + /* Only enable ENDTX interrupt if there's a callback attached to it or + if called from uartSendFullTimeout().*/ +#if UART_USE_WAIT == TRUE + if ((uartp->config->txend2_cb != NULL) || (uartp->early == false)) { +#else + if (uartp->config->txend2_cb != NULL) { +#endif + u->INTENSET = UARTE_INTENSET_ENDTX_Msk; + } + + u->EVENTS_ENDTX = 0; + u->EVENTS_ERROR = 0; + u->EVENTS_TXSTARTED = 0; + u->EVENTS_TXSTOPPED = 0; +#if CORTEX_MODEL >= 4 + (void)u->EVENTS_ENDTX; + (void)u->EVENTS_ERROR; + (void)u->EVENTS_TXSTARTED; + (void)u->EVENTS_TXSTOPPED; +#endif + + /* Starting transfer.*/ + u->TASKS_STARTTX = 1; +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) { + NRF_UARTE_Type *u=uartp->uart; + + u->TASKS_STOPTX = 1; + + return u->TXD.AMOUNT; +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, uint8_t n, void *rxbuf) { + NRF_UARTE_Type *u=uartp->uart; + + /* Stopping previous activity (idle state).*/ + u->TASKS_STOPRX = 1; + u->SHORTS = 0; + + /* RX DMA channel preparation.*/ + u->RXD.PTR = (uint32_t) rxbuf; + u->RXD.MAXCNT = n; + + u->EVENTS_ENDRX = 0; + u->EVENTS_ERROR = 0; + u->EVENTS_RXTO = 0; +#if CORTEX_MODEL >= 4 + (void)u->EVENTS_ENDRX; + (void)u->EVENTS_ERROR; + (void)u->EVENTS_RXTO; +#endif + + /* Starting transfer.*/ + u->TASKS_STARTRX = 1; +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) { + NRF_UARTE_Type *u=uartp->uart; + size_t n; + + u->TASKS_STOPRX = 1; + n = u->RXD.AMOUNT; + + uart_enter_rx_idle_loop(uartp); + + return n; +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/os/hal/ports/NRF5/LLD/UARTEv1/hal_uart_lld.h b/os/hal/ports/NRF5/LLD/UARTEv1/hal_uart_lld.h new file mode 100644 index 00000000..2e20fc7e --- /dev/null +++ b/os/hal/ports/NRF5/LLD/UARTEv1/hal_uart_lld.h @@ -0,0 +1,259 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file UARTEv1/hal_uart_lld.h + * @brief NRF5 low level UART driver header. + * @author andru + * + * @addtogroup UART + * @{ + */ + +#ifndef HAL_UART_LLD_H +#define HAL_UART_LLD_H + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief UART driver on UARTE enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(NRF5_UART_USE_UART0) || defined(__DOXYGEN__) +#define NRF5_UART_USE_UART0 FALSE +#endif + +/** + * @brief UART driver on UARTE enable hardware flow control switch. + * @details If set to @p TRUE the support hardware flow control is included. + * @note The default is @p FALSE. + */ +#if !defined(NRF5_UART_USE_HWFLOWCTRL) || defined(__DOXYGEN__) +#define NRF5_UART_USE_HWFLOWCTRL FALSE +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(NRF5_UART_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define NRF5_UART_UART0_IRQ_PRIORITY 3 +#endif + +/* Value indicating that no pad is connected to this UART register. */ +#define NRF5_UART_PAD_DISCONNECTED 0xFFFFFFFFU +#define NRF5_UART_INVALID_BAUDRATE 0xFFFFFFFFU + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if HAL_USE_SERIAL +#error "Only one UART or SERIAL driver can be activated" +#endif +#if !NRF5_UART_USE_UART0 +#error "UART driver activated but no USART/UART peripheral assigned" +#endif + +#if NRF5_UART_USE_UART0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_UART_UART0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART0" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Structure representing an UART driver. + */ +typedef struct UARTDriver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Start of transmission callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ + /** + * @brief Bit rate. + */ + uint32_t speed; + /** + * @brief Pin select for TXD signal. + */ + uint32_t tx_pad; + /** + * @brief Pin select for RXD signal. + */ + uint32_t rx_pad; +#if (NRF5_UART_USE_HWFLOWCTRL == TRUE) + /** + * @brief Pin select for RTS signal. + */ + uint32_t rts_pad; + /** + * @brief Pin select for CTS signal. + */ + uint32_t cts_pad; +#endif +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + */ +struct UARTDriver { + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Synchronization flag for transmit operations. + */ + bool early; + /** + * @brief Waiting thread on RX. + */ + thread_reference_t threadrx; + /** + * @brief Waiting thread on TX. + */ + thread_reference_t threadtx; +#endif /* UART_USE_WAIT */ +#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + mutex_t mutex; +#endif /* UART_USE_MUTUAL_EXCLUSION */ +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the UARTE registers block. + */ + NRF_UARTE_Type *uart; + /** + * @brief Default receive buffer while into @p UART_RX_IDLE state. + */ + volatile uint32_t rxbuf; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if NRF5_UART_USE_UART0 && !defined(__DOXYGEN__) +extern UARTDriver UARTD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void uart_lld_init(void); + void uart_lld_start(UARTDriver *uartp); + void uart_lld_stop(UARTDriver *uartp); + void uart_lld_start_send(UARTDriver *uartp, uint8_t n, const void *txbuf); + size_t uart_lld_stop_send(UARTDriver *uartp); + void uart_lld_start_receive(UARTDriver *uartp, uint8_t n, void *rxbuf); + size_t uart_lld_stop_receive(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* HAL_UART_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/NRF5/NRF52832/nrf52_isr.c b/os/hal/ports/NRF5/NRF52832/nrf52_isr.c index 431bb3b9..35f4df79 100644 --- a/os/hal/ports/NRF5/NRF52832/nrf52_isr.c +++ b/os/hal/ports/NRF5/NRF52832/nrf52_isr.c @@ -59,8 +59,22 @@ OSAL_IRQ_HANDLER(Vector58) { OSAL_IRQ_PROLOGUE(); #if (HAL_USE_ICU && NRF5_ICU_USE_GPIOTE_PPI) +#if NRF5_ICU_USE_TIMER0 icu_lld_serve_gpiote_interrupt(&ICUD1); #endif +#if NRF5_ICU_USE_TIMER1 + icu_lld_serve_gpiote_interrupt(&ICUD2); +#endif +#if NRF5_ICU_USE_TIMER2 + icu_lld_serve_gpiote_interrupt(&ICUD3); +#endif +#if NRF5_ICU_USE_TIMER3 + icu_lld_serve_gpiote_interrupt(&ICUD4); +#endif +#if NRF5_ICU_USE_TIMER4 + icu_lld_serve_gpiote_interrupt(&ICUD5); +#endif +#endif #if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) for (int ch = 0; ch < NRF5_GPIOTE_NUM_CHANNELS; ch++) diff --git a/os/hal/ports/NRF5/NRF52832/platform.mk b/os/hal/ports/NRF5/NRF52832/platform.mk index 98f8897f..54d71b29 100644 --- a/os/hal/ports/NRF5/NRF52832/platform.mk +++ b/os/hal/ports/NRF5/NRF52832/platform.mk @@ -21,6 +21,7 @@ endif include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/ADCv2/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/GPIOv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/UARTv1/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/UARTEv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/SPIv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/TWIMv1/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/PWMv2/driver.mk diff --git a/os/various/devices_lib/rf/nrf52_radio.c b/os/various/devices_lib/rf/nrf52_radio.c index e55870f8..9829935e 100644 --- a/os/various/devices_lib/rf/nrf52_radio.c +++ b/os/various/devices_lib/rf/nrf52_radio.c @@ -181,7 +181,7 @@ static uint32_t addr_conv(uint8_t const* p_addr) { } static thread_t *rfEvtThread_p; -static THD_WORKING_AREA(waRFEvtThread, 64); +static THD_WORKING_AREA(waRFEvtThread, 128); static THD_FUNCTION(rfEvtThread, arg) { (void)arg; @@ -207,7 +207,7 @@ static THD_FUNCTION(rfEvtThread, arg) { } static thread_t *rfIntThread_p; -static THD_WORKING_AREA(waRFIntThread, 64); +static THD_WORKING_AREA(waRFIntThread, 128); static THD_FUNCTION(rfIntThread, arg) { (void)arg; @@ -239,7 +239,6 @@ static THD_FUNCTION(rfIntThread, arg) { } static void serve_radio_interrupt(RFDriver *rfp) { - (void) rfp; if ((NRF_RADIO->INTENSET & RADIO_INTENSET_READY_Msk) && NRF_RADIO->EVENTS_READY) { NRF_RADIO->EVENTS_READY = 0; (void) NRF_RADIO->EVENTS_READY; @@ -268,7 +267,6 @@ OSAL_IRQ_HANDLER(Vector44) { } static void set_rf_payload_format_esb_dpl(RFDriver *rfp, uint32_t payload_length) { - (void)payload_length; #if (NRF52_MAX_PAYLOAD_LENGTH <= 32) // Using 6 bits for length NRF_RADIO->PCNF0 = (0 << RADIO_PCNF0_S0LEN_Pos) | @@ -398,14 +396,13 @@ static void reset_fifo(void) { } static void init_fifo(void) { - uint8_t i; reset_fifo(); - for (i = 0; i < NRF52_TX_FIFO_SIZE; i++) { + for (int i = 0; i < NRF52_TX_FIFO_SIZE; i++) { tx_fifo.p_payload[i] = &tx_fifo_payload[i]; } - for (i = 0; i < NRF52_RX_FIFO_SIZE; i++) { + for (int i = 0; i < NRF52_RX_FIFO_SIZE; i++) { rx_fifo.p_payload[i] = &rx_fifo_payload[i]; } } @@ -776,24 +773,30 @@ static void on_radio_disabled_rx_ack(RFDriver *rfp) { } nrf52_error_t radio_disable(void) { - RFD1.state = NRF52_STATE_IDLE; + NRF_RADIO->SHORTS = 0; + NRF_RADIO->INTENCLR = 0xFFFFFFFF; + + nvicDisableVector(RADIO_IRQn); + + NRF_RADIO->EVENTS_DISABLED = 0; + (void) NRF_RADIO->EVENTS_DISABLED; + + NRF_RADIO->TASKS_STOP = 1; + NRF_RADIO->TASKS_DISABLE = 1; + + RFD1.state = NRF52_STATE_IDLE; // Clear PPI NRF_PPI->CHENCLR = (1 << NRF52_RADIO_PPI_TIMER_START) | (1 << NRF52_RADIO_PPI_TIMER_STOP) | - (1 << NRF52_RADIO_PPI_RX_TIMEOUT); + (1 << NRF52_RADIO_PPI_RX_TIMEOUT) | + (1 << NRF52_RADIO_PPI_TX_START); reset_fifo(); memset(rx_pipe_info, 0, sizeof(rx_pipe_info)); memset(pids, 0, sizeof(pids)); - // Disable the radio - NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Enabled << RADIO_SHORTS_READY_START_Pos | - RADIO_SHORTS_END_DISABLE_Enabled << RADIO_SHORTS_END_DISABLE_Pos; - - nvicDisableVector(RADIO_IRQn); - // Terminate interrupts handle thread chThdTerminate(rfIntThread_p); chBSemSignal(&disable_sem); diff --git a/os/various/devices_lib/rf/nrf52_radio.h b/os/various/devices_lib/rf/nrf52_radio.h index 2f94465b..9cdea6fc 100644 --- a/os/various/devices_lib/rf/nrf52_radio.h +++ b/os/various/devices_lib/rf/nrf52_radio.h @@ -36,8 +36,8 @@ #define NRF52_RADIO_USE_TIMER4 FALSE /**< TIMER4 will be used by the module. */ #define NRF52_RADIO_IRQ_PRIORITY 3 /**< RADIO interrupt priority. */ -#define NRF52_RADIO_INTTHD_PRIORITY (NORMALPRIO+2) /**< Interrupts handle thread priority. */ -#define NRF52_RADIO_EVTTHD_PRIORITY (NORMALPRIO+1) /**< Events handle thread priority */ +#define NRF52_RADIO_INTTHD_PRIORITY (NORMALPRIO+4) /**< Interrupts handle thread priority. */ +#define NRF52_RADIO_EVTTHD_PRIORITY (NORMALPRIO+3) /**< Events handle thread priority */ #define NRF52_RADIO_PPI_TIMER_START 10 /**< The PPI channel used for timer start. */ #define NRF52_RADIO_PPI_TIMER_STOP 11 /**< The PPI channel used for timer stop. */ diff --git a/testhal/NRF52/NRF52832/RADIO-ESB/Makefile b/testhal/NRF52/NRF52832/RADIO-ESB/Makefile index 0d4f021c..003ad3db 100644 --- a/testhal/NRF52/NRF52832/RADIO-ESB/Makefile +++ b/testhal/NRF52/NRF52832/RADIO-ESB/Makefile @@ -80,7 +80,7 @@ endif PROJECT = ch # Imported source files and paths -CHIBIOS = ../../../../../ChibiOS +CHIBIOS = ../../../../../ChibiOS-RT CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib # Licensing files. include $(CHIBIOS)/os/license/license.mk diff --git a/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.c b/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.c index e55870f8..9829935e 100644 --- a/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.c +++ b/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.c @@ -181,7 +181,7 @@ static uint32_t addr_conv(uint8_t const* p_addr) { } static thread_t *rfEvtThread_p; -static THD_WORKING_AREA(waRFEvtThread, 64); +static THD_WORKING_AREA(waRFEvtThread, 128); static THD_FUNCTION(rfEvtThread, arg) { (void)arg; @@ -207,7 +207,7 @@ static THD_FUNCTION(rfEvtThread, arg) { } static thread_t *rfIntThread_p; -static THD_WORKING_AREA(waRFIntThread, 64); +static THD_WORKING_AREA(waRFIntThread, 128); static THD_FUNCTION(rfIntThread, arg) { (void)arg; @@ -239,7 +239,6 @@ static THD_FUNCTION(rfIntThread, arg) { } static void serve_radio_interrupt(RFDriver *rfp) { - (void) rfp; if ((NRF_RADIO->INTENSET & RADIO_INTENSET_READY_Msk) && NRF_RADIO->EVENTS_READY) { NRF_RADIO->EVENTS_READY = 0; (void) NRF_RADIO->EVENTS_READY; @@ -268,7 +267,6 @@ OSAL_IRQ_HANDLER(Vector44) { } static void set_rf_payload_format_esb_dpl(RFDriver *rfp, uint32_t payload_length) { - (void)payload_length; #if (NRF52_MAX_PAYLOAD_LENGTH <= 32) // Using 6 bits for length NRF_RADIO->PCNF0 = (0 << RADIO_PCNF0_S0LEN_Pos) | @@ -398,14 +396,13 @@ static void reset_fifo(void) { } static void init_fifo(void) { - uint8_t i; reset_fifo(); - for (i = 0; i < NRF52_TX_FIFO_SIZE; i++) { + for (int i = 0; i < NRF52_TX_FIFO_SIZE; i++) { tx_fifo.p_payload[i] = &tx_fifo_payload[i]; } - for (i = 0; i < NRF52_RX_FIFO_SIZE; i++) { + for (int i = 0; i < NRF52_RX_FIFO_SIZE; i++) { rx_fifo.p_payload[i] = &rx_fifo_payload[i]; } } @@ -776,24 +773,30 @@ static void on_radio_disabled_rx_ack(RFDriver *rfp) { } nrf52_error_t radio_disable(void) { - RFD1.state = NRF52_STATE_IDLE; + NRF_RADIO->SHORTS = 0; + NRF_RADIO->INTENCLR = 0xFFFFFFFF; + + nvicDisableVector(RADIO_IRQn); + + NRF_RADIO->EVENTS_DISABLED = 0; + (void) NRF_RADIO->EVENTS_DISABLED; + + NRF_RADIO->TASKS_STOP = 1; + NRF_RADIO->TASKS_DISABLE = 1; + + RFD1.state = NRF52_STATE_IDLE; // Clear PPI NRF_PPI->CHENCLR = (1 << NRF52_RADIO_PPI_TIMER_START) | (1 << NRF52_RADIO_PPI_TIMER_STOP) | - (1 << NRF52_RADIO_PPI_RX_TIMEOUT); + (1 << NRF52_RADIO_PPI_RX_TIMEOUT) | + (1 << NRF52_RADIO_PPI_TX_START); reset_fifo(); memset(rx_pipe_info, 0, sizeof(rx_pipe_info)); memset(pids, 0, sizeof(pids)); - // Disable the radio - NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Enabled << RADIO_SHORTS_READY_START_Pos | - RADIO_SHORTS_END_DISABLE_Enabled << RADIO_SHORTS_END_DISABLE_Pos; - - nvicDisableVector(RADIO_IRQn); - // Terminate interrupts handle thread chThdTerminate(rfIntThread_p); chBSemSignal(&disable_sem); diff --git a/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.h b/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.h index 2f94465b..9cdea6fc 100644 --- a/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.h +++ b/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.h @@ -36,8 +36,8 @@ #define NRF52_RADIO_USE_TIMER4 FALSE /**< TIMER4 will be used by the module. */ #define NRF52_RADIO_IRQ_PRIORITY 3 /**< RADIO interrupt priority. */ -#define NRF52_RADIO_INTTHD_PRIORITY (NORMALPRIO+2) /**< Interrupts handle thread priority. */ -#define NRF52_RADIO_EVTTHD_PRIORITY (NORMALPRIO+1) /**< Events handle thread priority */ +#define NRF52_RADIO_INTTHD_PRIORITY (NORMALPRIO+4) /**< Interrupts handle thread priority. */ +#define NRF52_RADIO_EVTTHD_PRIORITY (NORMALPRIO+3) /**< Events handle thread priority */ #define NRF52_RADIO_PPI_TIMER_START 10 /**< The PPI channel used for timer start. */ #define NRF52_RADIO_PPI_TIMER_STOP 11 /**< The PPI channel used for timer stop. */ diff --git a/testhal/NRF52/NRF52832/UART/Makefile b/testhal/NRF52/NRF52832/UART/Makefile new file mode 100644 index 00000000..38572db4 --- /dev/null +++ b/testhal/NRF52/NRF52832/UART/Makefile @@ -0,0 +1,211 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF5/NRF52832/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/NRF52-E73-2G4M04S/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +#include $(CHIBIOS)/test/rt/test.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD_CONTRIB)/NRF52832.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/hal/lib/streams/memstreams.c \ + $(CHIBIOS)/os/hal/lib/streams/chprintf.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(ALLASMSRC) +ASMXSRC = $(ALLXASMSRC) + +INCDIR = $(ALLINC) $(TESTINC) \ + $(CHIBIOS)/os/hal/lib/streams \ + $(TESTHAL) + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary +SREC = $(CP) -O srec + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/rules.mk diff --git a/testhal/NRF52/NRF52832/UART/chconf.h b/testhal/NRF52/NRF52832/UART/chconf.h new file mode 100644 index 00000000..6687603e --- /dev/null +++ b/testhal/NRF52/NRF52832/UART/chconf.h @@ -0,0 +1,757 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_1_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 1000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/NRF52/NRF52832/UART/halconf.h b/testhal/NRF52/NRF52832/UART/halconf.h new file mode 100644 index 00000000..b40c5dbf --- /dev/null +++ b/testhal/NRF52/NRF52832/UART/halconf.h @@ -0,0 +1,533 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_1_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/NRF52/NRF52832/UART/halconf_community.h b/testhal/NRF52/NRF52832/UART/halconf_community.h new file mode 100644 index 00000000..43fdbf86 --- /dev/null +++ b/testhal/NRF52/NRF52832/UART/halconf_community.h @@ -0,0 +1,173 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/NRF52/NRF52832/UART/main.c b/testhal/NRF52/NRF52832/UART/main.c new file mode 100644 index 00000000..4a105590 --- /dev/null +++ b/testhal/NRF52/NRF52832/UART/main.c @@ -0,0 +1,144 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static virtual_timer_t vt1, vt2; + +static void restart(void *p) { + + (void)p; + + chSysLockFromISR(); + uartStartSendI(&UARTD1, 14, "Hello World!\r\n"); + chSysUnlockFromISR(); +} + +static void ledoff(void *p) { + + (void)p; + + palSetPad(IOPORT1, LED1); +} + +/* + * This callback is invoked when a transmission buffer has been completely + * read by the driver. + */ +static void txend1(UARTDriver *uartp) { + + (void)uartp; + + palClearPad(IOPORT1, LED1); +} + +/* + * This callback is invoked when a transmission has physically completed. + */ +static void txend2(UARTDriver *uartp) { + + (void)uartp; + + palSetPad(IOPORT1, LED1); + chSysLockFromISR(); + chVTResetI(&vt1); + chVTDoSetI(&vt1, TIME_MS2I(5000), restart, NULL); + chSysUnlockFromISR(); +} + +/* + * This callback is invoked on a receive error, the errors mask is passed + * as parameter. + */ +static void rxerr(UARTDriver *uartp, uartflags_t e) { + + (void)uartp; + (void)e; +} + +/* + * This callback is invoked when a character is received but the application + * was not ready to receive it, the character is passed as parameter. + */ +static void rxchar(UARTDriver *uartp, uint16_t c) { + + (void)uartp; + (void)c; + + /* Flashing the LED each time a character is received.*/ + palClearPad(IOPORT1, LED1); + chSysLockFromISR(); + chVTResetI(&vt2); + chVTDoSetI(&vt2, TIME_MS2I(200), ledoff, NULL); + chSysUnlockFromISR(); +} + +/* + * This callback is invoked when a receive buffer has been completely written. + */ +static void rxend(UARTDriver *uartp) { + + (void)uartp; +} + +/* + * UART driver configuration structure. + */ +static UARTConfig uart_cfg_1 = { + txend1, + txend2, + rxend, + rxchar, + rxerr, + 38400, + UART_TX, + UART_RX, +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + uartStart(&UARTD1, &uart_cfg_1); + + /* + * Starts the transmission, it will be handled entirely in background. + */ + uartStartSend(&UARTD1, 13, "Starting...\r\n"); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (true) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/NRF52/NRF52832/UART/mcuconf.h b/testhal/NRF52/NRF52832/UART/mcuconf.h new file mode 100644 index 00000000..fa539736 --- /dev/null +++ b/testhal/NRF52/NRF52832/UART/mcuconf.h @@ -0,0 +1,29 @@ +/* + Copyright (C) 2015 Stephen Caudle + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +/* + * HAL driver system settings. + */ +#define NRF5_UART_USE_UART0 TRUE +#define NRF5_UART_UART0_IRQ_PRIORITY 3 +#define NRF5_ST_USE_RTC0 TRUE +#define NRF5_ST_USE_RTC1 FALSE +#define NRF5_ST_USE_TIMER0 FALSE + +#endif /* _MCUCONF_H_ */ diff --git a/testhal/NRF52/NRF52832/UART/readme.txt b/testhal/NRF52/NRF52832/UART/readme.txt new file mode 100644 index 00000000..756c920d --- /dev/null +++ b/testhal/NRF52/NRF52832/UART/readme.txt @@ -0,0 +1,17 @@ +***************************************************************************** +** ChibiOS/HAL - UART driver demo for NRF52832. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an EByte E73-2G4M04S board. + +** The Demo ** + +The application demonstrates the use of the NRF52832 UART driver. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports.