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ChibiOS-Contrib
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Merge branch 'master' of github.com:ChibiOS/ChibiOS-Contrib

This commit is contained in:
barthess 2017-01-06 11:06:52 +03:00
parent 779ea88be7 0135ff7dd3
commit 3e8fdd762a
8 changed files with 51 additions and 37 deletions
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2
os/hal/ports/NRF5/LLD/hal_qei_lld.h
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@ -166,7 +166,7 @@ typedef enum {
/**
* @brief QEI counter type.
*/
typedef int32_t qeicnt_t;
typedef int16_t qeicnt_t;
/**
* @brief QEI delta type.

2
os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h
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@ -251,7 +251,7 @@ typedef enum {
/**
* @brief QEI counter type.
*/
typedef uint16_t qeicnt_t;
typedef int16_t qeicnt_t;
/**
* @brief QEI delta type.

15
os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h
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@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -23,8 +23,8 @@
*/
#ifndef HAL_STM32_OTG_H_
#define HAL_STM32_OTG_H_
#ifndef HAL_STM32_OTG_H
#define HAL_STM32_OTG_H
/**
* @brief Number of the implemented endpoints in OTG_FS.
@ -430,12 +430,16 @@ typedef struct {
* @name GCCFG register bit definitions
* @{
*/
/* Definitions for stepping 1.*/
#define GCCFG_NOVBUSSENS (1U<<21) /**< VBUS sensing disable. */
#define GCCFG_SOFOUTEN (1U<<20) /**< SOF output enable. */
#define GCCFG_VBUSBSEN (1U<<19) /**< Enable the VBUS sensing "B"
device. */
#define GCCFG_VBUSASEN (1U<<18) /**< Enable the VBUS sensing "A"
device. */
/* Definitions for stepping 2.*/
#define GCCFG_VBDEN (1U<<21) /**< VBUS sensing enable. */
#define GCCFG_PWRDWN (1U<<16) /**< Power down. */
/** @} */
@ -590,6 +594,7 @@ typedef struct {
interrupt. */
#define HCINT_STALL (1U<<3) /**< STALL response received
interrupt. */
#define HCINT_AHBERR (1U<<2) /**< AHB error interrupt. */
#define HCINT_CHH (1U<<1) /**< Channel halted. */
#define HCINT_XFRC (1U<<0) /**< Transfer completed. */
/** @} */
@ -611,7 +616,7 @@ typedef struct {
interrupt mask. */
#define HCINTMSK_STALLM (1U<<3) /**< STALL response received
interrupt mask. */
#define HCINTMSK_AHBERRM (1U<<2)
#define HCINTMSK_AHBERRM (1U<<2) /**< AHB error interrupt mask. */
#define HCINTMSK_CHHM (1U<<1) /**< Channel halted mask. */
#define HCINTMSK_XFRCM (1U<<0) /**< Transfer completed mask. */
/** @} */
@ -924,6 +929,6 @@ typedef struct {
*/
#define OTG_HS ((stm32_otg_t *)OTG_HS_ADDR)
#endif /* _STM32_OTG_H_ */
#endif /* STM32_OTG_H */
/** @} */

11
os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
View File

@ -1361,7 +1361,8 @@ static void _usbh_start(USBHDriver *usbh) {
if (&USBHD2 == usbh) {
#endif
/* OTG HS clock enable and reset.*/
rccEnableOTG_HS(FALSE);
rccEnableOTG_HS(TRUE); // Enable HS clock when cpu is in sleep mode
rccDisableOTG_HSULPI(TRUE); // Disable HS ULPI clock when cpu is in sleep mode
rccResetOTG_HS();
otgp->GINTMSK = 0;
@ -1386,12 +1387,20 @@ static void _usbh_start(USBHDriver *usbh) {
otgp->PCGCCTL = 0;
/* Internal FS PHY activation.*/
#if STM32_OTG_STEPPING == 1
#if defined(BOARD_OTG_NOVBUSSENS)
otgp->GCCFG = GCCFG_NOVBUSSENS | GCCFG_PWRDWN;
#else
otgp->GCCFG = GCCFG_PWRDWN;
#endif
#elif STM32_OTG_STEPPING == 2
#if defined(BOARD_OTG_NOVBUSSENS)
otgp->GCCFG = GCCFG_PWRDWN;
#else
otgp->GCCFG = (GCCFG_VBDEN | GCCFG_PWRDWN);
#endif
#endif
/* 48MHz 1.1 PHY.*/
otgp->HCFG = HCFG_FSLSS | HCFG_FSLSPCS_48;

6
os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h
View File

@ -15,8 +15,8 @@
limitations under the License.
*/
#ifndef HAL_USBH_LLD_H_
#define HAL_USBH_LLD_H_
#ifndef HAL_USBH_LLD_H
#define HAL_USBH_LLD_H
#include "hal.h"
@ -150,4 +150,4 @@ uint8_t usbh_lld_roothub_get_statuschange_bitmap(USBHDriver *usbh);
#endif
#endif /* HAL_USBH_LLD_H_ */
#endif /* HAL_USBH_LLD_H */

2
os/hal/src/hal_qei.c
View File

@ -364,7 +364,7 @@ qeidelta_t qeiUpdateI(QEIDriver *qeip) {
"invalid state");
cnt = qei_lld_get_count(qeip);
delta = cnt - qeip->last;
delta = (qeicnt_t)(cnt - qeip->last);
qeip->last = cnt;
return delta;